include/asm-x86/processor.h

   1 #ifndef __ASM_X86_PROCESSOR_H
   2 #define __ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* migration helper, for KVM - will be removed in 2.6.25: */
   7 #define Xgt_desc_struct desc_ptr
   8
   9 /* Forward declaration, a strange C thing */
  10 struct task_struct;
  11 struct mm_struct;
  12
  13 #include <asm/vm86.h>
  14 #include <asm/math_emu.h>
  15 #include <asm/segment.h>
  16 #include <asm/types.h>
  17 #include <asm/sigcontext.h>
  18 #include <asm/current.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/system.h>
  21 #include <asm/page.h>
  22 #include <asm/percpu.h>
  23 #include <asm/msr.h>
  24 #include <asm/desc_defs.h>
  25 #include <asm/nops.h>
  26
  27 #include <linux/personality.h>
  28 #include <linux/cpumask.h>
  29 #include <linux/cache.h>
  30 #include <linux/threads.h>
  31 #include <linux/init.h>
  32
  33 /*
  34  * Default implementation of macro that returns current
  35  * instruction pointer ("program counter").
  36  */
  37 static inline void *current_text_addr(void)
  38 {
  39         void *pc;
  40
  41         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  42
  43         return pc;
  44 }
  45
  46 #ifdef CONFIG_X86_VSMP
  47 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  48 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  49 #else
  50 # define ARCH_MIN_TASKALIGN             16
  51 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  52 #endif
  53
  54 /*
  55  *  CPU type and hardware bug flags. Kept separately for each CPU.
  56  *  Members of this structure are referenced in head.S, so think twice
  57  *  before touching them. [mj]
  58  */
  59
  60 struct cpuinfo_x86 {
  61         __u8                    x86;            /* CPU family */
  62         __u8                    x86_vendor;     /* CPU vendor */
  63         __u8                    x86_model;
  64         __u8                    x86_mask;
  65 #ifdef CONFIG_X86_32
  66         char                    wp_works_ok;    /* It doesn't on 386's */
  67
  68         /* Problems on some 486Dx4's and old 386's: */
  69         char                    hlt_works_ok;
  70         char                    hard_math;
  71         char                    rfu;
  72         char                    fdiv_bug;
  73         char                    f00f_bug;
  74         char                    coma_bug;
  75         char                    pad0;
  76 #else
  77         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  78         int                      x86_tlbsize;
  79         __u8                    x86_virt_bits;
  80         __u8                    x86_phys_bits;
  81         /* CPUID returned core id bits: */
  82         __u8                    x86_coreid_bits;
  83         /* Max extended CPUID function supported: */
  84         __u32                   extended_cpuid_level;
  85 #endif
  86         /* Maximum supported CPUID level, -1=no CPUID: */
  87         int                     cpuid_level;
  88         __u32                   x86_capability[NCAPINTS];
  89         char                    x86_vendor_id[16];
  90         char                    x86_model_id[64];
  91         /* in KB - valid for CPUS which support this call: */
  92         int                     x86_cache_size;
  93         int                     x86_cache_alignment;    /* In bytes */
  94         int                     x86_power;
  95         unsigned long           loops_per_jiffy;
  96 #ifdef CONFIG_SMP
  97         /* cpus sharing the last level cache: */
  98         cpumask_t               llc_shared_map;
  99 #endif
 100         /* cpuid returned max cores value: */
 101         u16                      x86_max_cores;
 102         u16                     apicid;
 103         u16                     initial_apicid;
 104         u16                     x86_clflush_size;
 105 #ifdef CONFIG_SMP
 106         /* number of cores as seen by the OS: */
 107         u16                     booted_cores;
 108         /* Physical processor id: */
 109         u16                     phys_proc_id;
 110         /* Core id: */
 111         u16                     cpu_core_id;
 112         /* Index into per_cpu list: */
 113         u16                     cpu_index;
 114 #endif
 115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 116
 117 #define X86_VENDOR_INTEL        0
 118 #define X86_VENDOR_CYRIX        1
 119 #define X86_VENDOR_AMD          2
 120 #define X86_VENDOR_UMC          3
 121 #define X86_VENDOR_NEXGEN       4
 122 #define X86_VENDOR_CENTAUR      5
 123 #define X86_VENDOR_TRANSMETA    7
 124 #define X86_VENDOR_NSC          8
 125 #define X86_VENDOR_NUM          9
 126
 127 #define X86_VENDOR_UNKNOWN      0xff
 128
 129 /*
 130  * capabilities of CPUs
 131  */
 132 extern struct cpuinfo_x86       boot_cpu_data;
 133 extern struct cpuinfo_x86       new_cpu_data;
 134
 135 extern struct tss_struct        doublefault_tss;
 136 extern __u32                    cleared_cpu_caps[NCAPINTS];
 137
 138 #ifdef CONFIG_SMP
 139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 140 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 141 #define current_cpu_data        cpu_data(smp_processor_id())
 142 #else
 143 #define cpu_data(cpu)           boot_cpu_data
 144 #define current_cpu_data        boot_cpu_data
 145 #endif
 146
 147 static inline int hlt_works(int cpu)
 148 {
 149 #ifdef CONFIG_X86_32
 150         return cpu_data(cpu).hlt_works_ok;
 151 #else
 152         return 1;
 153 #endif
 154 }
 155
 156 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 157
 158 extern void cpu_detect(struct cpuinfo_x86 *c);
 159
 160 extern void identify_cpu(struct cpuinfo_x86 *);
 161 extern void identify_boot_cpu(void);
 162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 163 extern void print_cpu_info(struct cpuinfo_x86 *);
 164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 166 extern unsigned short num_cache_leaves;
 167
 168 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
 169 extern void detect_ht(struct cpuinfo_x86 *c);
 170 #else
 171 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 172 #endif
 173
 174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 175                                 unsigned int *ecx, unsigned int *edx)
 176 {
 177         /* ecx is often an input as well as an output. */
 178         asm("cpuid"
 179             : "=a" (*eax),
 180               "=b" (*ebx),
 181               "=c" (*ecx),
 182               "=d" (*edx)
 183             : "0" (*eax), "2" (*ecx));
 184 }
 185
 186 static inline void load_cr3(pgd_t *pgdir)
 187 {
 188         write_cr3(__pa(pgdir));
 189 }
 190
 191 #ifdef CONFIG_X86_32
 192 /* This is the TSS defined by the hardware. */
 193 struct x86_hw_tss {
 194         unsigned short          back_link, __blh;
 195         unsigned long           sp0;
 196         unsigned short          ss0, __ss0h;
 197         unsigned long           sp1;
 198         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 199         unsigned short          ss1, __ss1h;
 200         unsigned long           sp2;
 201         unsigned short          ss2, __ss2h;
 202         unsigned long           __cr3;
 203         unsigned long           ip;
 204         unsigned long           flags;
 205         unsigned long           ax;
 206         unsigned long           cx;
 207         unsigned long           dx;
 208         unsigned long           bx;
 209         unsigned long           sp;
 210         unsigned long           bp;
 211         unsigned long           si;
 212         unsigned long           di;
 213         unsigned short          es, __esh;
 214         unsigned short          cs, __csh;
 215         unsigned short          ss, __ssh;
 216         unsigned short          ds, __dsh;
 217         unsigned short          fs, __fsh;
 218         unsigned short          gs, __gsh;
 219         unsigned short          ldt, __ldth;
 220         unsigned short          trace;
 221         unsigned short          io_bitmap_base;
 222
 223 } __attribute__((packed));
 224 #else
 225 struct x86_hw_tss {
 226         u32                     reserved1;
 227         u64                     sp0;
 228         u64                     sp1;
 229         u64                     sp2;
 230         u64                     reserved2;
 231         u64                     ist[7];
 232         u32                     reserved3;
 233         u32                     reserved4;
 234         u16                     reserved5;
 235         u16                     io_bitmap_base;
 236
 237 } __attribute__((packed)) ____cacheline_aligned;
 238 #endif
 239
 240 /*
 241  * IO-bitmap sizes:
 242  */
 243 #define IO_BITMAP_BITS                  65536
 244 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 245 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 246 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 247 #define INVALID_IO_BITMAP_OFFSET        0x8000
 248 #define INVALID_IO_BITMAP_OFFSET_LAZY   0x9000
 249
 250 struct tss_struct {
 251         /*
 252          * The hardware state:
 253          */
 254         struct x86_hw_tss       x86_tss;
 255
 256         /*
 257          * The extra 1 is there because the CPU will access an
 258          * additional byte beyond the end of the IO permission
 259          * bitmap. The extra byte must be all 1 bits, and must
 260          * be within the limit.
 261          */
 262         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 263         /*
 264          * Cache the current maximum and the last task that used the bitmap:
 265          */
 266         unsigned long           io_bitmap_max;
 267         struct thread_struct    *io_bitmap_owner;
 268
 269         /*
 270          * Pad the TSS to be cacheline-aligned (size is 0x100):
 271          */
 272         unsigned long           __cacheline_filler[35];
 273         /*
 274          * .. and then another 0x100 bytes for the emergency kernel stack:
 275          */
 276         unsigned long           stack[64];
 277
 278 } __attribute__((packed));
 279
 280 DECLARE_PER_CPU(struct tss_struct, init_tss);
 281
 282 /*
 283  * Save the original ist values for checking stack pointers during debugging
 284  */
 285 struct orig_ist {
 286         unsigned long           ist[7];
 287 };
 288
 289 #define MXCSR_DEFAULT           0x1f80
 290
 291 struct i387_fsave_struct {
 292         u32                     cwd;    /* FPU Control Word             */
 293         u32                     swd;    /* FPU Status Word              */
 294         u32                     twd;    /* FPU Tag Word                 */
 295         u32                     fip;    /* FPU IP Offset                */
 296         u32                     fcs;    /* FPU IP Selector              */
 297         u32                     foo;    /* FPU Operand Pointer Offset   */
 298         u32                     fos;    /* FPU Operand Pointer Selector */
 299
 300         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 301         u32                     st_space[20];
 302
 303         /* Software status information [not touched by FSAVE ]:         */
 304         u32                     status;
 305 };
 306
 307 struct i387_fxsave_struct {
 308         u16                     cwd; /* Control Word                    */
 309         u16                     swd; /* Status Word                     */
 310         u16                     twd; /* Tag Word                        */
 311         u16                     fop; /* Last Instruction Opcode         */
 312         union {
 313                 struct {
 314                         u64     rip; /* Instruction Pointer             */
 315                         u64     rdp; /* Data Pointer                    */
 316                 };
 317                 struct {
 318                         u32     fip; /* FPU IP Offset                   */
 319                         u32     fcs; /* FPU IP Selector                 */
 320                         u32     foo; /* FPU Operand Offset              */
 321                         u32     fos; /* FPU Operand Selector            */
 322                 };
 323         };
 324         u32                     mxcsr;          /* MXCSR Register State */
 325         u32                     mxcsr_mask;     /* MXCSR Mask           */
 326
 327         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 328         u32                     st_space[32];
 329
 330         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 331         u32                     xmm_space[64];
 332
 333         u32                     padding[24];
 334
 335 } __attribute__((aligned(16)));
 336
 337 struct i387_soft_struct {
 338         u32                     cwd;
 339         u32                     swd;
 340         u32                     twd;
 341         u32                     fip;
 342         u32                     fcs;
 343         u32                     foo;
 344         u32                     fos;
 345         /* 8*10 bytes for each FP-reg = 80 bytes: */
 346         u32                     st_space[20];
 347         u8                      ftop;
 348         u8                      changed;
 349         u8                      lookahead;
 350         u8                      no_update;
 351         u8                      rm;
 352         u8                      alimit;
 353         struct info             *info;
 354         u32                     entry_eip;
 355 };
 356
 357 union thread_xstate {
 358         struct i387_fsave_struct        fsave;
 359         struct i387_fxsave_struct       fxsave;
 360         struct i387_soft_struct         soft;
 361 };
 362
 363 #ifdef CONFIG_X86_64
 364 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 365 #endif
 366
 367 extern void print_cpu_info(struct cpuinfo_x86 *);
 368 extern unsigned int xstate_size;
 369 extern void free_thread_xstate(struct task_struct *);
 370 extern struct kmem_cache *task_xstate_cachep;
 371 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 372 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 373 extern unsigned short num_cache_leaves;
 374
 375 struct thread_struct {
 376         /* Cached TLS descriptors: */
 377         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 378         unsigned long           sp0;
 379         unsigned long           sp;
 380 #ifdef CONFIG_X86_32
 381         unsigned long           sysenter_cs;
 382 #else
 383         unsigned long           usersp; /* Copy from PDA */
 384         unsigned short          es;
 385         unsigned short          ds;
 386         unsigned short          fsindex;
 387         unsigned short          gsindex;
 388 #endif
 389         unsigned long           ip;
 390         unsigned long           fs;
 391         unsigned long           gs;
 392         /* Hardware debugging registers: */
 393         unsigned long           debugreg0;
 394         unsigned long           debugreg1;
 395         unsigned long           debugreg2;
 396         unsigned long           debugreg3;
 397         unsigned long           debugreg6;
 398         unsigned long           debugreg7;
 399         /* Fault info: */
 400         unsigned long           cr2;
 401         unsigned long           trap_no;
 402         unsigned long           error_code;
 403         /* floating point and extended processor state */
 404         union thread_xstate     *xstate;
 405 #ifdef CONFIG_X86_32
 406         /* Virtual 86 mode info */
 407         struct vm86_struct __user *vm86_info;
 408         unsigned long           screen_bitmap;
 409         unsigned long           v86flags;
 410         unsigned long           v86mask;
 411         unsigned long           saved_sp0;
 412         unsigned int            saved_fs;
 413         unsigned int            saved_gs;
 414 #endif
 415         /* IO permissions: */
 416         unsigned long           *io_bitmap_ptr;
 417         unsigned long           iopl;
 418         /* Max allowed port in the bitmap, in bytes: */
 419         unsigned                io_bitmap_max;
 420 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 421         unsigned long   debugctlmsr;
 422 /* Debug Store - if not 0 points to a DS Save Area configuration;
 423  *               goes into MSR_IA32_DS_AREA */
 424         unsigned long   ds_area_msr;
 425 };
 426
 427 static inline unsigned long native_get_debugreg(int regno)
 428 {
 429         unsigned long val = 0;  /* Damn you, gcc! */
 430
 431         switch (regno) {
 432         case 0:
 433                 asm("mov %%db0, %0" :"=r" (val));
 434                 break;
 435         case 1:
 436                 asm("mov %%db1, %0" :"=r" (val));
 437                 break;
 438         case 2:
 439                 asm("mov %%db2, %0" :"=r" (val));
 440                 break;
 441         case 3:
 442                 asm("mov %%db3, %0" :"=r" (val));
 443                 break;
 444         case 6:
 445                 asm("mov %%db6, %0" :"=r" (val));
 446                 break;
 447         case 7:
 448                 asm("mov %%db7, %0" :"=r" (val));
 449                 break;
 450         default:
 451                 BUG();
 452         }
 453         return val;
 454 }
 455
 456 static inline void native_set_debugreg(int regno, unsigned long value)
 457 {
 458         switch (regno) {
 459         case 0:
 460                 asm("mov %0, %%db0"     ::"r" (value));
 461                 break;
 462         case 1:
 463                 asm("mov %0, %%db1"     ::"r" (value));
 464                 break;
 465         case 2:
 466                 asm("mov %0, %%db2"     ::"r" (value));
 467                 break;
 468         case 3:
 469                 asm("mov %0, %%db3"     ::"r" (value));
 470                 break;
 471         case 6:
 472                 asm("mov %0, %%db6"     ::"r" (value));
 473                 break;
 474         case 7:
 475                 asm("mov %0, %%db7"     ::"r" (value));
 476                 break;
 477         default:
 478                 BUG();
 479         }
 480 }
 481
 482 /*
 483  * Set IOPL bits in EFLAGS from given mask
 484  */
 485 static inline void native_set_iopl_mask(unsigned mask)
 486 {
 487 #ifdef CONFIG_X86_32
 488         unsigned int reg;
 489
 490         asm volatile ("pushfl;"
 491                       "popl %0;"
 492                       "andl %1, %0;"
 493                       "orl %2, %0;"
 494                       "pushl %0;"
 495                       "popfl"
 496                       : "=&r" (reg)
 497                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 498 #endif
 499 }
 500
 501 static inline void
 502 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 503 {
 504         tss->x86_tss.sp0 = thread->sp0;
 505 #ifdef CONFIG_X86_32
 506         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 507         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 508                 tss->x86_tss.ss1 = thread->sysenter_cs;
 509                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 510         }
 511 #endif
 512 }
 513
 514 static inline void native_swapgs(void)
 515 {
 516 #ifdef CONFIG_X86_64
 517         asm volatile("swapgs" ::: "memory");
 518 #endif
 519 }
 520
 521 #ifdef CONFIG_PARAVIRT
 522 #include <asm/paravirt.h>
 523 #else
 524 #define __cpuid                 native_cpuid
 525 #define paravirt_enabled()      0
 526
 527 /*
 528  * These special macros can be used to get or set a debugging register
 529  */
 530 #define get_debugreg(var, register)                             \
 531         (var) = native_get_debugreg(register)
 532 #define set_debugreg(value, register)                           \
 533         native_set_debugreg(register, value)
 534
 535 static inline void load_sp0(struct tss_struct *tss,
 536                             struct thread_struct *thread)
 537 {
 538         native_load_sp0(tss, thread);
 539 }
 540
 541 #define set_iopl_mask native_set_iopl_mask
 542 #define SWAPGS  swapgs
 543 #endif /* CONFIG_PARAVIRT */
 544
 545 /*
 546  * Save the cr4 feature set we're using (ie
 547  * Pentium 4MB enable and PPro Global page
 548  * enable), so that any CPU's that boot up
 549  * after us can get the correct flags.
 550  */
 551 extern unsigned long            mmu_cr4_features;
 552
 553 static inline void set_in_cr4(unsigned long mask)
 554 {
 555         unsigned cr4;
 556
 557         mmu_cr4_features |= mask;
 558         cr4 = read_cr4();
 559         cr4 |= mask;
 560         write_cr4(cr4);
 561 }
 562
 563 static inline void clear_in_cr4(unsigned long mask)
 564 {
 565         unsigned cr4;
 566
 567         mmu_cr4_features &= ~mask;
 568         cr4 = read_cr4();
 569         cr4 &= ~mask;
 570         write_cr4(cr4);
 571 }
 572
 573 struct microcode_header {
 574         unsigned int            hdrver;
 575         unsigned int            rev;
 576         unsigned int            date;
 577         unsigned int            sig;
 578         unsigned int            cksum;
 579         unsigned int            ldrver;
 580         unsigned int            pf;
 581         unsigned int            datasize;
 582         unsigned int            totalsize;
 583         unsigned int            reserved[3];
 584 };
 585
 586 struct microcode {
 587         struct microcode_header hdr;
 588         unsigned int            bits[0];
 589 };
 590
 591 typedef struct microcode        microcode_t;
 592 typedef struct microcode_header microcode_header_t;
 593
 594 /* microcode format is extended from prescott processors */
 595 struct extended_signature {
 596         unsigned int            sig;
 597         unsigned int            pf;
 598         unsigned int            cksum;
 599 };
 600
 601 struct extended_sigtable {
 602         unsigned int            count;
 603         unsigned int            cksum;
 604         unsigned int            reserved[3];
 605         struct extended_signature sigs[0];
 606 };
 607
 608 typedef struct {
 609         unsigned long           seg;
 610 } mm_segment_t;
 611
 612
 613 /*
 614  * create a kernel thread without removing it from tasklists
 615  */
 616 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 617
 618 /* Free all resources held by a thread. */
 619 extern void release_thread(struct task_struct *);
 620
 621 /* Prepare to copy thread state - unlazy all lazy state */
 622 extern void prepare_to_copy(struct task_struct *tsk);
 623
 624 unsigned long get_wchan(struct task_struct *p);
 625
 626 /*
 627  * Generic CPUID function
 628  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 629  * resulting in stale register contents being returned.
 630  */
 631 static inline void cpuid(unsigned int op,
 632                          unsigned int *eax, unsigned int *ebx,
 633                          unsigned int *ecx, unsigned int *edx)
 634 {
 635         *eax = op;
 636         *ecx = 0;
 637         __cpuid(eax, ebx, ecx, edx);
 638 }
 639
 640 /* Some CPUID calls want 'count' to be placed in ecx */
 641 static inline void cpuid_count(unsigned int op, int count,
 642                                unsigned int *eax, unsigned int *ebx,
 643                                unsigned int *ecx, unsigned int *edx)
 644 {
 645         *eax = op;
 646         *ecx = count;
 647         __cpuid(eax, ebx, ecx, edx);
 648 }
 649
 650 /*
 651  * CPUID functions returning a single datum
 652  */
 653 static inline unsigned int cpuid_eax(unsigned int op)
 654 {
 655         unsigned int eax, ebx, ecx, edx;
 656
 657         cpuid(op, &eax, &ebx, &ecx, &edx);
 658
 659         return eax;
 660 }
 661
 662 static inline unsigned int cpuid_ebx(unsigned int op)
 663 {
 664         unsigned int eax, ebx, ecx, edx;
 665
 666         cpuid(op, &eax, &ebx, &ecx, &edx);
 667
 668         return ebx;
 669 }
 670
 671 static inline unsigned int cpuid_ecx(unsigned int op)
 672 {
 673         unsigned int eax, ebx, ecx, edx;
 674
 675         cpuid(op, &eax, &ebx, &ecx, &edx);
 676
 677         return ecx;
 678 }
 679
 680 static inline unsigned int cpuid_edx(unsigned int op)
 681 {
 682         unsigned int eax, ebx, ecx, edx;
 683
 684         cpuid(op, &eax, &ebx, &ecx, &edx);
 685
 686         return edx;
 687 }
 688
 689 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 690 static inline void rep_nop(void)
 691 {
 692         asm volatile("rep; nop" ::: "memory");
 693 }
 694
 695 static inline void cpu_relax(void)
 696 {
 697         rep_nop();
 698 }
 699
 700 /* Stop speculative execution: */
 701 static inline void sync_core(void)
 702 {
 703         int tmp;
 704
 705         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 706                      : "ebx", "ecx", "edx", "memory");
 707 }
 708
 709 static inline void __monitor(const void *eax, unsigned long ecx,
 710                              unsigned long edx)
 711 {
 712         /* "monitor %eax, %ecx, %edx;" */
 713         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 714                      :: "a" (eax), "c" (ecx), "d"(edx));
 715 }
 716
 717 static inline void __mwait(unsigned long eax, unsigned long ecx)
 718 {
 719         /* "mwait %eax, %ecx;" */
 720         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 721                      :: "a" (eax), "c" (ecx));
 722 }
 723
 724 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 725 {
 726         /* "mwait %eax, %ecx;" */
 727         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 728                      :: "a" (eax), "c" (ecx));
 729 }
 730
 731 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 732
 733 extern int                      force_mwait;
 734
 735 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 736
 737 extern unsigned long            boot_option_idle_override;
 738
 739 extern void enable_sep_cpu(void);
 740 extern int sysenter_setup(void);
 741
 742 /* Defined in head.S */
 743 extern struct desc_ptr          early_gdt_descr;
 744
 745 extern void cpu_set_gdt(int);
 746 extern void switch_to_new_gdt(void);
 747 extern void cpu_init(void);
 748 extern void init_gdt(int cpu);
 749
 750 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 751 {
 752 #ifndef CONFIG_X86_DEBUGCTLMSR
 753         if (boot_cpu_data.x86 < 6)
 754                 return;
 755 #endif
 756         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 757 }
 758
 759 /*
 760  * from system description table in BIOS. Mostly for MCA use, but
 761  * others may find it useful:
 762  */
 763 extern unsigned int             machine_id;
 764 extern unsigned int             machine_submodel_id;
 765 extern unsigned int             BIOS_revision;
 766
 767 /* Boot loader type from the setup header: */
 768 extern int                      bootloader_type;
 769
 770 extern char                     ignore_fpu_irq;
 771
 772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 773 #define ARCH_HAS_PREFETCHW
 774 #define ARCH_HAS_SPINLOCK_PREFETCH
 775
 776 #ifdef CONFIG_X86_32
 777 # define BASE_PREFETCH          ASM_NOP4
 778 # define ARCH_HAS_PREFETCH
 779 #else
 780 # define BASE_PREFETCH          "prefetcht0 (%1)"
 781 #endif
 782
 783 /*
 784  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 785  *
 786  * It's not worth to care about 3dnow prefetches for the K6
 787  * because they are microcoded there and very slow.
 788  */
 789 static inline void prefetch(const void *x)
 790 {
 791         alternative_input(BASE_PREFETCH,
 792                           "prefetchnta (%1)",
 793                           X86_FEATURE_XMM,
 794                           "r" (x));
 795 }
 796
 797 /*
 798  * 3dnow prefetch to get an exclusive cache line.
 799  * Useful for spinlocks to avoid one state transition in the
 800  * cache coherency protocol:
 801  */
 802 static inline void prefetchw(const void *x)
 803 {
 804         alternative_input(BASE_PREFETCH,
 805                           "prefetchw (%1)",
 806                           X86_FEATURE_3DNOW,
 807                           "r" (x));
 808 }
 809
 810 static inline void spin_lock_prefetch(const void *x)
 811 {
 812         prefetchw(x);
 813 }
 814
 815 #ifdef CONFIG_X86_32
 816 /*
 817  * User space process size: 3GB (default).
 818  */
 819 #define TASK_SIZE               PAGE_OFFSET
 820 #define STACK_TOP               TASK_SIZE
 821 #define STACK_TOP_MAX           STACK_TOP
 822
 823 #define INIT_THREAD  {                                                    \
 824         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 825         .vm86_info              = NULL,                                   \
 826         .sysenter_cs            = __KERNEL_CS,                            \
 827         .io_bitmap_ptr          = NULL,                                   \
 828         .fs                     = __KERNEL_PERCPU,                        \
 829 }
 830
 831 /*
 832  * Note that the .io_bitmap member must be extra-big. This is because
 833  * the CPU will access an additional byte beyond the end of the IO
 834  * permission bitmap. The extra byte must be all 1 bits, and must
 835  * be within the limit.
 836  */
 837 #define INIT_TSS  {                                                       \
 838         .x86_tss = {                                                      \
 839                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 840                 .ss0            = __KERNEL_DS,                            \
 841                 .ss1            = __KERNEL_CS,                            \
 842                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 843          },                                                               \
 844         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 845 }
 846
 847 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 848
 849 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 850 #define KSTK_TOP(info)                                                 \
 851 ({                                                                     \
 852        unsigned long *__ptr = (unsigned long *)(info);                 \
 853        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 854 })
 855
 856 /*
 857  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 858  * This is necessary to guarantee that the entire "struct pt_regs"
 859  * is accessable even if the CPU haven't stored the SS/ESP registers
 860  * on the stack (interrupt gate does not save these registers
 861  * when switching to the same priv ring).
 862  * Therefore beware: accessing the ss/esp fields of the
 863  * "struct pt_regs" is possible, but they may contain the
 864  * completely wrong values.
 865  */
 866 #define task_pt_regs(task)                                             \
 867 ({                                                                     \
 868        struct pt_regs *__regs__;                                       \
 869        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 870        __regs__ - 1;                                                   \
 871 })
 872
 873 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 874
 875 #else
 876 /*
 877  * User space process size. 47bits minus one guard page.
 878  */
 879 #define TASK_SIZE64     ((1UL << 47) - PAGE_SIZE)
 880
 881 /* This decides where the kernel will search for a free chunk of vm
 882  * space during mmap's.
 883  */
 884 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 885                                         0xc0000000 : 0xFFFFe000)
 886
 887 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 888                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 889 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 890                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 891
 892 #define STACK_TOP               TASK_SIZE
 893 #define STACK_TOP_MAX           TASK_SIZE64
 894
 895 #define INIT_THREAD  { \
 896         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 897 }
 898
 899 #define INIT_TSS  { \
 900         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 901 }
 902
 903 /*
 904  * Return saved PC of a blocked thread.
 905  * What is this good for? it will be always the scheduler or ret_from_fork.
 906  */
 907 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 908
 909 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 910 #define KSTK_ESP(tsk)           -1 /* sorry. doesn't work for syscall. */
 911 #endif /* CONFIG_X86_64 */
 912
 913 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 914                                                unsigned long new_sp);
 915
 916 /*
 917  * This decides where the kernel will search for a free chunk of vm
 918  * space during mmap's.
 919  */
 920 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 921
 922 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 923
 924 /* Get/set a process' ability to use the timestamp counter instruction */
 925 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 926 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 927
 928 extern int get_tsc_mode(unsigned long adr);
 929 extern int set_tsc_mode(unsigned int val);
 930
 931 #endif