2 * include/asm-xtensa/tlbflush.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 #ifndef _XTENSA_TLBFLUSH_H
12 #define _XTENSA_TLBFLUSH_H
18 #include <asm/processor.h>
19 #include <linux/stringify.h>
23 * - flush_tlb_all() flushes all processes TLB entries
24 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
25 * - flush_tlb_page(mm, vmaddr) flushes a single page
26 * - flush_tlb_range(mm, start, end) flushes a range of pages
29 extern void flush_tlb_all(void);
30 extern void flush_tlb_mm(struct mm_struct
*);
31 extern void flush_tlb_page(struct vm_area_struct
*,unsigned long);
32 extern void flush_tlb_range(struct vm_area_struct
*,unsigned long,unsigned long);
34 #define flush_tlb_kernel_range(start,end) flush_tlb_all()
37 /* This is calld in munmap when we have freed up some page-table pages.
38 * We don't need to do anything here, there's nothing special about our
42 static inline void flush_tlb_pgtables(struct mm_struct
*mm
,
43 unsigned long start
, unsigned long end
)
49 #define ITLB_WAYS_LOG2 XCHAL_ITLB_WAY_BITS
50 #define DTLB_WAYS_LOG2 XCHAL_DTLB_WAY_BITS
51 #define ITLB_PROBE_SUCCESS (1 << ITLB_WAYS_LOG2)
52 #define DTLB_PROBE_SUCCESS (1 << DTLB_WAYS_LOG2)
54 static inline unsigned long itlb_probe(unsigned long addr
)
57 __asm__
__volatile__("pitlb %0, %1\n\t" : "=a" (tmp
) : "a" (addr
));
61 static inline unsigned long dtlb_probe(unsigned long addr
)
64 __asm__
__volatile__("pdtlb %0, %1\n\t" : "=a" (tmp
) : "a" (addr
));
68 static inline void invalidate_itlb_entry (unsigned long probe
)
70 __asm__
__volatile__("iitlb %0; isync\n\t" : : "a" (probe
));
73 static inline void invalidate_dtlb_entry (unsigned long probe
)
75 __asm__
__volatile__("idtlb %0; dsync\n\t" : : "a" (probe
));
78 /* Use the .._no_isync functions with caution. Generally, these are
79 * handy for bulk invalidates followed by a single 'isync'. The
80 * caller must follow up with an 'isync', which can be relatively
81 * expensive on some Xtensa implementations.
83 static inline void invalidate_itlb_entry_no_isync (unsigned entry
)
85 /* Caller must follow up with 'isync'. */
86 __asm__
__volatile__ ("iitlb %0\n" : : "a" (entry
) );
89 static inline void invalidate_dtlb_entry_no_isync (unsigned entry
)
91 /* Caller must follow up with 'isync'. */
92 __asm__
__volatile__ ("idtlb %0\n" : : "a" (entry
) );
95 static inline void set_itlbcfg_register (unsigned long val
)
97 __asm__
__volatile__("wsr %0, "__stringify(ITLBCFG
)"\n\t" "isync\n\t"
101 static inline void set_dtlbcfg_register (unsigned long val
)
103 __asm__
__volatile__("wsr %0, "__stringify(DTLBCFG
)"; dsync\n\t"
107 static inline void set_ptevaddr_register (unsigned long val
)
109 __asm__
__volatile__(" wsr %0, "__stringify(PTEVADDR
)"; isync\n"
113 static inline unsigned long read_ptevaddr_register (void)
116 __asm__
__volatile__("rsr %0, "__stringify(PTEVADDR
)"\n\t" : "=a" (tmp
));
120 static inline void write_dtlb_entry (pte_t entry
, int way
)
122 __asm__
__volatile__("wdtlb %1, %0; dsync\n\t"
123 : : "r" (way
), "r" (entry
) );
126 static inline void write_itlb_entry (pte_t entry
, int way
)
128 __asm__
__volatile__("witlb %1, %0; isync\n\t"
129 : : "r" (way
), "r" (entry
) );
132 static inline void invalidate_page_directory (void)
134 invalidate_dtlb_entry (DTLB_WAY_PGTABLE
);
137 static inline void invalidate_itlb_mapping (unsigned address
)
139 unsigned long tlb_entry
;
140 while ((tlb_entry
= itlb_probe (address
)) & ITLB_PROBE_SUCCESS
)
141 invalidate_itlb_entry (tlb_entry
);
144 static inline void invalidate_dtlb_mapping (unsigned address
)
146 unsigned long tlb_entry
;
147 while ((tlb_entry
= dtlb_probe (address
)) & DTLB_PROBE_SUCCESS
)
148 invalidate_dtlb_entry (tlb_entry
);
151 #define check_pgt_cache() do { } while (0)
156 /* DO NOT USE THESE FUNCTIONS. These instructions aren't part of the Xtensa
157 * ISA and exist only for test purposes..
158 * You may find it helpful for MMU debugging, however.
160 * 'at' is the unmodified input register
161 * 'as' is the output register, as follows (specific to the Linux config):
163 * as[31..12] contain the virtual address
164 * as[11..08] are meaningless
165 * as[07..00] contain the asid
168 static inline unsigned long read_dtlb_virtual (int way
)
171 __asm__
__volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp
), "+a" (way
));
175 static inline unsigned long read_dtlb_translation (int way
)
178 __asm__
__volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp
), "+a" (way
));
182 static inline unsigned long read_itlb_virtual (int way
)
185 __asm__
__volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp
), "+a" (way
));
189 static inline unsigned long read_itlb_translation (int way
)
192 __asm__
__volatile__("ritlb1 %0, %1\n\t" : "=a" (tmp
), "+a" (way
));
196 #endif /* DEBUG_TLB */
199 #endif /* __KERNEL__ */
200 #endif /* _XTENSA_PGALLOC_H */
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