2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__
26 #include <linux/types.h>
28 #define EDID_LENGTH 128
35 } __attribute__((packed
));
37 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
38 #define EDID_TIMING_ASPECT_SHIFT 0
39 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
42 #define EDID_TIMING_VFREQ_SHIFT 2
43 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
46 u8 hsize
; /* need to multiply by 8 then add 248 */
48 } __attribute__((packed
));
50 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 6)
51 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 5)
52 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
53 #define DRM_EDID_PT_STEREO (1 << 2)
54 #define DRM_EDID_PT_INTERLACED (1 << 1)
56 /* If detailed data is pixel timing */
57 struct detailed_pixel_timing
{
65 u8 hsync_pulse_width_lo
;
66 u8 vsync_offset_pulse_width_lo
;
67 u8 hsync_vsync_offset_pulse_width_hi
;
70 u8 width_height_mm_hi
;
74 } __attribute__((packed
));
76 /* If it's not pixel timing, it'll be one of the below */
77 struct detailed_data_string
{
79 } __attribute__((packed
));
81 struct detailed_data_monitor_range
{
86 u8 pixel_clock_mhz
; /* need to multiply by 10 */
87 __le16 sec_gtf_toggle
; /* A000=use above, 20=use below */
88 u8 hfreq_start_khz
; /* need to multiply by 2 */
89 u8 c
; /* need to divide by 2 */
92 u8 j
; /* need to divide by 2 */
93 } __attribute__((packed
));
95 struct detailed_data_wpindex
{
96 u8 white_xy_lo
; /* Upper 2 bits each */
99 u8 gamma
; /* need to divide by 100 then add 1 */
100 } __attribute__((packed
));
102 struct detailed_data_color_point
{
107 } __attribute__((packed
));
109 struct detailed_non_pixel
{
111 u8 type
; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
112 fb=color point data, fa=standard timing data,
113 f9=undefined, f8=mfg. reserved */
116 struct detailed_data_string str
;
117 struct detailed_data_monitor_range range
;
118 struct detailed_data_wpindex color
;
119 struct std_timing timings
[5];
121 } __attribute__((packed
));
123 #define EDID_DETAIL_STD_MODES 0xfa
124 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
125 #define EDID_DETAIL_MONITOR_NAME 0xfc
126 #define EDID_DETAIL_MONITOR_RANGE 0xfd
127 #define EDID_DETAIL_MONITOR_STRING 0xfe
128 #define EDID_DETAIL_MONITOR_SERIAL 0xff
130 struct detailed_timing
{
131 __le16 pixel_clock
; /* need to multiply by 10 KHz */
133 struct detailed_pixel_timing pixel_data
;
134 struct detailed_non_pixel other_data
;
136 } __attribute__((packed
));
138 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 7)
139 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 5)
140 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 4)
141 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
142 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 2)
143 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 1)
144 #define DRM_EDID_INPUT_DIGITAL (1 << 0) /* bits above must be zero if set */
146 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 7)
147 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 6)
148 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 5)
149 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
150 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 2)
151 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 1)
152 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 0)
156 /* Vendor & product info */
159 u32 serial
; /* FIXME: byte order */
171 /* Color characteristics */
182 /* Est. timings and mfg rsvd timings*/
183 struct est_timings established_timings
;
184 /* Standard timings 1-8*/
185 struct std_timing standard_timings
[8];
186 /* Detailing timings 1-4 */
187 struct detailed_timing detailed_timings
[4];
188 /* Number of 128 byte ext. blocks */
192 } __attribute__((packed
));
194 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
196 #endif /* __DRM_EDID_H__ */