include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17  */
  18
  19 #ifndef __ASM_ARM_KVM_VGIC_H
  20 #define __ASM_ARM_KVM_VGIC_H
  21
  22 #include <linux/kernel.h>
  23 #include <linux/kvm.h>
  24 #include <linux/irqreturn.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27
  28 #define VGIC_NR_IRQS_LEGACY     256
  29 #define VGIC_NR_SGIS            16
  30 #define VGIC_NR_PPIS            16
  31 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  32
  33 #define VGIC_V2_MAX_LRS         (1 << 6)
  34 #define VGIC_V3_MAX_LRS         16
  35 #define VGIC_MAX_IRQS           1024
  36 #define VGIC_V2_MAX_CPUS        8
  37
  38 /* Sanity checks... */
  39 #if (KVM_MAX_VCPUS > 8)
  40 #error  Invalid number of CPU interfaces
  41 #endif
  42
  43 #if (VGIC_NR_IRQS_LEGACY & 31)
  44 #error "VGIC_NR_IRQS must be a multiple of 32"
  45 #endif
  46
  47 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
  48 #error "VGIC_NR_IRQS must be <= 1024"
  49 #endif
  50
  51 /*
  52  * The GIC distributor registers describing interrupts have two parts:
  53  * - 32 per-CPU interrupts (SGI + PPI)
  54  * - a bunch of shared interrupts (SPI)
  55  */
  56 struct vgic_bitmap {
  57         /*
  58          * - One UL per VCPU for private interrupts (assumes UL is at
  59          *   least 32 bits)
  60          * - As many UL as necessary for shared interrupts.
  61          *
  62          * The private interrupts are accessed via the "private"
  63          * field, one UL per vcpu (the state for vcpu n is in
  64          * private[n]). The shared interrupts are accessed via the
  65          * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
  66          */
  67         unsigned long *private;
  68         unsigned long *shared;
  69 };
  70
  71 struct vgic_bytemap {
  72         /*
  73          * - 8 u32 per VCPU for private interrupts
  74          * - As many u32 as necessary for shared interrupts.
  75          *
  76          * The private interrupts are accessed via the "private"
  77          * field, (the state for vcpu n is in private[n*8] to
  78          * private[n*8 + 7]). The shared interrupts are accessed via
  79          * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
  80          * shared[(n-32)/4] word).
  81          */
  82         u32 *private;
  83         u32 *shared;
  84 };
  85
  86 struct kvm_vcpu;
  87
  88 enum vgic_type {
  89         VGIC_V2,                /* Good ol' GICv2 */
  90         VGIC_V3,                /* New fancy GICv3 */
  91 };
  92
  93 #define LR_STATE_PENDING        (1 << 0)
  94 #define LR_STATE_ACTIVE         (1 << 1)
  95 #define LR_STATE_MASK           (3 << 0)
  96 #define LR_EOI_INT              (1 << 2)
  97
  98 struct vgic_lr {
  99         u16     irq;
 100         u8      source;
 101         u8      state;
 102 };
 103
 104 struct vgic_vmcr {
 105         u32     ctlr;
 106         u32     abpr;
 107         u32     bpr;
 108         u32     pmr;
 109 };
 110
 111 struct vgic_ops {
 112         struct vgic_lr  (*get_lr)(const struct kvm_vcpu *, int);
 113         void    (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
 114         void    (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
 115         u64     (*get_elrsr)(const struct kvm_vcpu *vcpu);
 116         u64     (*get_eisr)(const struct kvm_vcpu *vcpu);
 117         u32     (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
 118         void    (*enable_underflow)(struct kvm_vcpu *vcpu);
 119         void    (*disable_underflow)(struct kvm_vcpu *vcpu);
 120         void    (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 121         void    (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 122         void    (*enable)(struct kvm_vcpu *vcpu);
 123 };
 124
 125 struct vgic_params {
 126         /* vgic type */
 127         enum vgic_type  type;
 128         /* Physical address of vgic virtual cpu interface */
 129         phys_addr_t     vcpu_base;
 130         /* Number of list registers */
 131         u32             nr_lr;
 132         /* Interrupt number */
 133         unsigned int    maint_irq;
 134         /* Virtual control interface base address */
 135         void __iomem    *vctrl_base;
 136         int             max_gic_vcpus;
 137 };
 138
 139 struct vgic_vm_ops {
 140         bool    (*handle_mmio)(struct kvm_vcpu *, struct kvm_run *,
 141                                struct kvm_exit_mmio *);
 142         bool    (*queue_sgi)(struct kvm_vcpu *, int irq);
 143         void    (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
 144         int     (*init_model)(struct kvm *);
 145         int     (*map_resources)(struct kvm *, const struct vgic_params *);
 146 };
 147
 148 struct vgic_dist {
 149 #ifdef CONFIG_KVM_ARM_VGIC
 150         spinlock_t              lock;
 151         bool                    in_kernel;
 152         bool                    ready;
 153
 154         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 155         u32                     vgic_model;
 156
 157         int                     nr_cpus;
 158         int                     nr_irqs;
 159
 160         /* Virtual control interface mapping */
 161         void __iomem            *vctrl_base;
 162
 163         /* Distributor and vcpu interface mapping in the guest */
 164         phys_addr_t             vgic_dist_base;
 165         /* GICv2 and GICv3 use different mapped register blocks */
 166         union {
 167                 phys_addr_t             vgic_cpu_base;
 168                 phys_addr_t             vgic_redist_base;
 169         };
 170
 171         /* Distributor enabled */
 172         u32                     enabled;
 173
 174         /* Interrupt enabled (one bit per IRQ) */
 175         struct vgic_bitmap      irq_enabled;
 176
 177         /* Level-triggered interrupt external input is asserted */
 178         struct vgic_bitmap      irq_level;
 179
 180         /*
 181          * Interrupt state is pending on the distributor
 182          */
 183         struct vgic_bitmap      irq_pending;
 184
 185         /*
 186          * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
 187          * interrupts.  Essentially holds the state of the flip-flop in
 188          * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
 189          * Once set, it is only cleared for level-triggered interrupts on
 190          * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
 191          */
 192         struct vgic_bitmap      irq_soft_pend;
 193
 194         /* Level-triggered interrupt queued on VCPU interface */
 195         struct vgic_bitmap      irq_queued;
 196
 197         /* Interrupt priority. Not used yet. */
 198         struct vgic_bytemap     irq_priority;
 199
 200         /* Level/edge triggered */
 201         struct vgic_bitmap      irq_cfg;
 202
 203         /*
 204          * Source CPU per SGI and target CPU:
 205          *
 206          * Each byte represent a SGI observable on a VCPU, each bit of
 207          * this byte indicating if the corresponding VCPU has
 208          * generated this interrupt. This is a GICv2 feature only.
 209          *
 210          * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
 211          * the SGIs observable on VCPUn.
 212          */
 213         u8                      *irq_sgi_sources;
 214
 215         /*
 216          * Target CPU for each SPI:
 217          *
 218          * Array of available SPI, each byte indicating the target
 219          * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
 220          */
 221         u8                      *irq_spi_cpu;
 222
 223         /*
 224          * Reverse lookup of irq_spi_cpu for faster compute pending:
 225          *
 226          * Array of bitmaps, one per VCPU, describing if IRQn is
 227          * routed to a particular VCPU.
 228          */
 229         struct vgic_bitmap      *irq_spi_target;
 230
 231         /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
 232         u32                     *irq_spi_mpidr;
 233
 234         /* Bitmap indicating which CPU has something pending */
 235         unsigned long           *irq_pending_on_cpu;
 236
 237         struct vgic_vm_ops      vm_ops;
 238 #endif
 239 };
 240
 241 struct vgic_v2_cpu_if {
 242         u32             vgic_hcr;
 243         u32             vgic_vmcr;
 244         u32             vgic_misr;      /* Saved only */
 245         u64             vgic_eisr;      /* Saved only */
 246         u64             vgic_elrsr;     /* Saved only */
 247         u32             vgic_apr;
 248         u32             vgic_lr[VGIC_V2_MAX_LRS];
 249 };
 250
 251 struct vgic_v3_cpu_if {
 252 #ifdef CONFIG_ARM_GIC_V3
 253         u32             vgic_hcr;
 254         u32             vgic_vmcr;
 255         u32             vgic_sre;       /* Restored only, change ignored */
 256         u32             vgic_misr;      /* Saved only */
 257         u32             vgic_eisr;      /* Saved only */
 258         u32             vgic_elrsr;     /* Saved only */
 259         u32             vgic_ap0r[4];
 260         u32             vgic_ap1r[4];
 261         u64             vgic_lr[VGIC_V3_MAX_LRS];
 262 #endif
 263 };
 264
 265 struct vgic_cpu {
 266 #ifdef CONFIG_KVM_ARM_VGIC
 267         /* per IRQ to LR mapping */
 268         u8              *vgic_irq_lr_map;
 269
 270         /* Pending interrupts on this VCPU */
 271         DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
 272         unsigned long   *pending_shared;
 273
 274         /* Bitmap of used/free list registers */
 275         DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
 276
 277         /* Number of list registers on this CPU */
 278         int             nr_lr;
 279
 280         /* CPU vif control registers for world switch */
 281         union {
 282                 struct vgic_v2_cpu_if   vgic_v2;
 283                 struct vgic_v3_cpu_if   vgic_v3;
 284         };
 285 #endif
 286 };
 287
 288 #define LR_EMPTY        0xff
 289
 290 #define INT_STATUS_EOI          (1 << 0)
 291 #define INT_STATUS_UNDERFLOW    (1 << 1)
 292
 293 struct kvm;
 294 struct kvm_vcpu;
 295 struct kvm_run;
 296 struct kvm_exit_mmio;
 297
 298 #ifdef CONFIG_KVM_ARM_VGIC
 299 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 300 int kvm_vgic_hyp_init(void);
 301 int kvm_vgic_map_resources(struct kvm *kvm);
 302 int kvm_vgic_get_max_vcpus(void);
 303 int kvm_vgic_create(struct kvm *kvm, u32 type);
 304 void kvm_vgic_destroy(struct kvm *kvm);
 305 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 306 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 307 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 308 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
 309                         bool level);
 310 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 311 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 312 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 313                       struct kvm_exit_mmio *mmio);
 314
 315 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 316 #define vgic_initialized(k)     (!!((k)->arch.vgic.nr_cpus))
 317 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 318
 319 int vgic_v2_probe(struct device_node *vgic_node,
 320                   const struct vgic_ops **ops,
 321                   const struct vgic_params **params);
 322 #ifdef CONFIG_ARM_GIC_V3
 323 int vgic_v3_probe(struct device_node *vgic_node,
 324                   const struct vgic_ops **ops,
 325                   const struct vgic_params **params);
 326 #else
 327 static inline int vgic_v3_probe(struct device_node *vgic_node,
 328                                 const struct vgic_ops **ops,
 329                                 const struct vgic_params **params)
 330 {
 331         return -ENODEV;
 332 }
 333 #endif
 334
 335 #else
 336 static inline int kvm_vgic_hyp_init(void)
 337 {
 338         return 0;
 339 }
 340
 341 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
 342 {
 343         return 0;
 344 }
 345
 346 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
 347 {
 348         return -ENXIO;
 349 }
 350
 351 static inline int kvm_vgic_map_resources(struct kvm *kvm)
 352 {
 353         return 0;
 354 }
 355
 356 static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
 357 {
 358         return 0;
 359 }
 360
 361 static inline void kvm_vgic_destroy(struct kvm *kvm)
 362 {
 363 }
 364
 365 static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
 366 {
 367 }
 368
 369 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
 370 {
 371         return 0;
 372 }
 373
 374 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
 375 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
 376
 377 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
 378                                       unsigned int irq_num, bool level)
 379 {
 380         return 0;
 381 }
 382
 383 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
 384 {
 385         return 0;
 386 }
 387
 388 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 389                                     struct kvm_exit_mmio *mmio)
 390 {
 391         return false;
 392 }
 393
 394 static inline int irqchip_in_kernel(struct kvm *kvm)
 395 {
 396         return 0;
 397 }
 398
 399 static inline bool vgic_initialized(struct kvm *kvm)
 400 {
 401         return true;
 402 }
 403
 404 static inline bool vgic_ready(struct kvm *kvm)
 405 {
 406         return true;
 407 }
 408
 409 static inline int kvm_vgic_get_max_vcpus(void)
 410 {
 411         return KVM_MAX_VCPUS;
 412 }
 413 #endif
 414
 415 #endif