include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/types.h>
  24 #include <kvm/iodev.h>
  25 #include <linux/list.h>
  26
  27 #define VGIC_V3_MAX_CPUS        255
  28 #define VGIC_V2_MAX_CPUS        8
  29 #define VGIC_NR_IRQS_LEGACY     256
  30 #define VGIC_NR_SGIS            16
  31 #define VGIC_NR_PPIS            16
  32 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  33 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  34 #define VGIC_MAX_SPI            1019
  35 #define VGIC_MAX_RESERVED       1023
  36 #define VGIC_MIN_LPI            8192
  37
  38 enum vgic_type {
  39         VGIC_V2,                /* Good ol' GICv2 */
  40         VGIC_V3,                /* New fancy GICv3 */
  41 };
  42
  43 /* same for all guests, as depending only on the _host's_ GIC model */
  44 struct vgic_global {
  45         /* type of the host GIC */
  46         enum vgic_type          type;
  47
  48         /* Physical address of vgic virtual cpu interface */
  49         phys_addr_t             vcpu_base;
  50
  51         /* virtual control interface mapping */
  52         void __iomem            *vctrl_base;
  53
  54         /* Number of implemented list registers */
  55         int                     nr_lr;
  56
  57         /* Maintenance IRQ number */
  58         unsigned int            maint_irq;
  59
  60         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  61         int                     max_gic_vcpus;
  62
  63         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  64         bool                    can_emulate_gicv2;
  65 };
  66
  67 extern struct vgic_global kvm_vgic_global_state;
  68
  69 #define VGIC_V2_MAX_LRS         (1 << 6)
  70 #define VGIC_V3_MAX_LRS         16
  71 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  72
  73 enum vgic_irq_config {
  74         VGIC_CONFIG_EDGE = 0,
  75         VGIC_CONFIG_LEVEL
  76 };
  77
  78 struct vgic_irq {
  79         spinlock_t irq_lock;            /* Protects the content of the struct */
  80         struct list_head lpi_list;      /* Used to link all LPIs together */
  81         struct list_head ap_list;
  82
  83         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
  84                                          * SPIs and LPIs: The VCPU whose ap_list
  85                                          * this is queued on.
  86                                          */
  87
  88         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
  89                                          * be sent to, as a result of the
  90                                          * targets reg (v2) or the
  91                                          * affinity reg (v3).
  92                                          */
  93
  94         u32 intid;                      /* Guest visible INTID */
  95         bool pending;
  96         bool line_level;                /* Level only */
  97         bool soft_pending;              /* Level only */
  98         bool active;                    /* not used for LPIs */
  99         bool enabled;
 100         bool hw;                        /* Tied to HW IRQ */
 101         struct kref refcount;           /* Used for LPIs */
 102         u32 hwintid;                    /* HW INTID number */
 103         union {
 104                 u8 targets;                     /* GICv2 target VCPUs mask */
 105                 u32 mpidr;                      /* GICv3 target VCPU */
 106         };
 107         u8 source;                      /* GICv2 SGIs only */
 108         u8 priority;
 109         enum vgic_irq_config config;    /* Level or edge */
 110 };
 111
 112 struct vgic_register_region;
 113 struct vgic_its;
 114
 115 enum iodev_type {
 116         IODEV_CPUIF,
 117         IODEV_DIST,
 118         IODEV_REDIST,
 119         IODEV_ITS
 120 };
 121
 122 struct vgic_io_device {
 123         gpa_t base_addr;
 124         union {
 125                 struct kvm_vcpu *redist_vcpu;
 126                 struct vgic_its *its;
 127         };
 128         const struct vgic_register_region *regions;
 129         enum iodev_type iodev_type;
 130         int nr_regions;
 131         struct kvm_io_device dev;
 132 };
 133
 134 struct vgic_its {
 135         /* The base address of the ITS control register frame */
 136         gpa_t                   vgic_its_base;
 137
 138         bool                    enabled;
 139         bool                    initialized;
 140         struct vgic_io_device   iodev;
 141         struct kvm_device       *dev;
 142
 143         /* These registers correspond to GITS_BASER{0,1} */
 144         u64                     baser_device_table;
 145         u64                     baser_coll_table;
 146
 147         /* Protects the command queue */
 148         struct mutex            cmd_lock;
 149         u64                     cbaser;
 150         u32                     creadr;
 151         u32                     cwriter;
 152
 153         /* Protects the device and collection lists */
 154         struct mutex            its_lock;
 155         struct list_head        device_list;
 156         struct list_head        collection_list;
 157 };
 158
 159 struct vgic_dist {
 160         bool                    in_kernel;
 161         bool                    ready;
 162         bool                    initialized;
 163
 164         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 165         u32                     vgic_model;
 166
 167         /* Do injected MSIs require an additional device ID? */
 168         bool                    msis_require_devid;
 169
 170         int                     nr_spis;
 171
 172         /* TODO: Consider moving to global state */
 173         /* Virtual control interface mapping */
 174         void __iomem            *vctrl_base;
 175
 176         /* base addresses in guest physical address space: */
 177         gpa_t                   vgic_dist_base;         /* distributor */
 178         union {
 179                 /* either a GICv2 CPU interface */
 180                 gpa_t                   vgic_cpu_base;
 181                 /* or a number of GICv3 redistributor regions */
 182                 gpa_t                   vgic_redist_base;
 183         };
 184
 185         /* distributor enabled */
 186         bool                    enabled;
 187
 188         struct vgic_irq         *spis;
 189
 190         struct vgic_io_device   dist_iodev;
 191
 192         bool                    has_its;
 193
 194         /*
 195          * Contains the attributes and gpa of the LPI configuration table.
 196          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 197          * one address across all redistributors.
 198          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 199          */
 200         u64                     propbaser;
 201
 202         /* Protects the lpi_list and the count value below. */
 203         spinlock_t              lpi_list_lock;
 204         struct list_head        lpi_list_head;
 205         int                     lpi_list_count;
 206 };
 207
 208 struct vgic_v2_cpu_if {
 209         u32             vgic_hcr;
 210         u32             vgic_vmcr;
 211         u32             vgic_misr;      /* Saved only */
 212         u64             vgic_eisr;      /* Saved only */
 213         u64             vgic_elrsr;     /* Saved only */
 214         u32             vgic_apr;
 215         u32             vgic_lr[VGIC_V2_MAX_LRS];
 216 };
 217
 218 struct vgic_v3_cpu_if {
 219 #ifdef CONFIG_KVM_ARM_VGIC_V3
 220         u32             vgic_hcr;
 221         u32             vgic_vmcr;
 222         u32             vgic_sre;       /* Restored only, change ignored */
 223         u32             vgic_misr;      /* Saved only */
 224         u32             vgic_eisr;      /* Saved only */
 225         u32             vgic_elrsr;     /* Saved only */
 226         u32             vgic_ap0r[4];
 227         u32             vgic_ap1r[4];
 228         u64             vgic_lr[VGIC_V3_MAX_LRS];
 229 #endif
 230 };
 231
 232 struct vgic_cpu {
 233         /* CPU vif control registers for world switch */
 234         union {
 235                 struct vgic_v2_cpu_if   vgic_v2;
 236                 struct vgic_v3_cpu_if   vgic_v3;
 237         };
 238
 239         unsigned int used_lrs;
 240         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 241
 242         spinlock_t ap_list_lock;        /* Protects the ap_list */
 243
 244         /*
 245          * List of IRQs that this VCPU should consider because they are either
 246          * Active or Pending (hence the name; AP list), or because they recently
 247          * were one of the two and need to be migrated off this list to another
 248          * VCPU.
 249          */
 250         struct list_head ap_list_head;
 251
 252         u64 live_lrs;
 253
 254         /*
 255          * Members below are used with GICv3 emulation only and represent
 256          * parts of the redistributor.
 257          */
 258         struct vgic_io_device   rd_iodev;
 259         struct vgic_io_device   sgi_iodev;
 260
 261         /* Contains the attributes and gpa of the LPI pending tables. */
 262         u64 pendbaser;
 263
 264         bool lpis_enabled;
 265 };
 266
 267 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 268 void kvm_vgic_early_init(struct kvm *kvm);
 269 int kvm_vgic_create(struct kvm *kvm, u32 type);
 270 void kvm_vgic_destroy(struct kvm *kvm);
 271 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
 272 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 273 int kvm_vgic_map_resources(struct kvm *kvm);
 274 int kvm_vgic_hyp_init(void);
 275
 276 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 277                         bool level);
 278 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 279                                bool level);
 280 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
 281 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 282 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 283
 284 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 285
 286 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 287 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 288 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 289 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 290                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 291
 292 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 293 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 294 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 295
 296 #ifdef CONFIG_KVM_ARM_VGIC_V3
 297 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 298 #else
 299 static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
 300 {
 301 }
 302 #endif
 303
 304 /**
 305  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 306  *
 307  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 308  * can use.
 309  */
 310 static inline int kvm_vgic_get_max_vcpus(void)
 311 {
 312         return kvm_vgic_global_state.max_gic_vcpus;
 313 }
 314
 315 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 316
 317 #endif /* __KVM_ARM_VGIC_H */