2 * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
6 * Copyright (C) 2001 ARM Limited
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
15 * CLCD Controller Internal Register addresses
17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
28 #define CLCD_PL110_UCUR 0x00000028
29 #define CLCD_PL110_LCUR 0x0000002C
31 #define CLCD_PL111_CNTL 0x00000018
32 #define CLCD_PL111_IENB 0x0000001c
33 #define CLCD_PL111_RIS 0x00000020
34 #define CLCD_PL111_MIS 0x00000024
35 #define CLCD_PL111_ICR 0x00000028
36 #define CLCD_PL111_UCUR 0x0000002c
37 #define CLCD_PL111_LCUR 0x00000030
39 #define CLCD_PALL 0x00000200
40 #define CLCD_PALETTE 0x00000200
42 #define TIM2_CLKSEL (1 << 5)
43 #define TIM2_IVS (1 << 11)
44 #define TIM2_IHS (1 << 12)
45 #define TIM2_IPC (1 << 13)
46 #define TIM2_IOE (1 << 14)
47 #define TIM2_BCD (1 << 26)
49 #define CNTL_LCDEN (1 << 0)
50 #define CNTL_LCDBPP1 (0 << 1)
51 #define CNTL_LCDBPP2 (1 << 1)
52 #define CNTL_LCDBPP4 (2 << 1)
53 #define CNTL_LCDBPP8 (3 << 1)
54 #define CNTL_LCDBPP16 (4 << 1)
55 #define CNTL_LCDBPP16_565 (6 << 1)
56 #define CNTL_LCDBPP16_444 (7 << 1)
57 #define CNTL_LCDBPP24 (5 << 1)
58 #define CNTL_LCDBW (1 << 4)
59 #define CNTL_LCDTFT (1 << 5)
60 #define CNTL_LCDMONO8 (1 << 6)
61 #define CNTL_LCDDUAL (1 << 7)
62 #define CNTL_BGR (1 << 8)
63 #define CNTL_BEBO (1 << 9)
64 #define CNTL_BEPO (1 << 10)
65 #define CNTL_LCDPWR (1 << 11)
66 #define CNTL_LCDVCOMP(x) ((x) << 12)
67 #define CNTL_LDMAFIFOTIME (1 << 15)
68 #define CNTL_WATERMARK (1 << 16)
70 /* ST Microelectronics variant bits */
71 #define CNTL_ST_1XBPP_444 0x0
72 #define CNTL_ST_1XBPP_5551 (1 << 17)
73 #define CNTL_ST_1XBPP_565 (1 << 18)
74 #define CNTL_ST_CDWID_12 0x0
75 #define CNTL_ST_CDWID_16 (1 << 19)
76 #define CNTL_ST_CDWID_18 (1 << 20)
77 #define CNTL_ST_CDWID_24 ((1 << 19)|(1 << 20))
78 #define CNTL_ST_CEAEN (1 << 21)
79 #define CNTL_ST_LCDBPP24_PACKED (6 << 1)
82 /* individual formats */
83 CLCD_CAP_RGB444
= (1 << 0),
84 CLCD_CAP_RGB5551
= (1 << 1),
85 CLCD_CAP_RGB565
= (1 << 2),
86 CLCD_CAP_RGB888
= (1 << 3),
87 CLCD_CAP_BGR444
= (1 << 4),
88 CLCD_CAP_BGR5551
= (1 << 5),
89 CLCD_CAP_BGR565
= (1 << 6),
90 CLCD_CAP_BGR888
= (1 << 7),
92 /* connection layouts */
93 CLCD_CAP_444
= CLCD_CAP_RGB444
| CLCD_CAP_BGR444
,
94 CLCD_CAP_5551
= CLCD_CAP_RGB5551
| CLCD_CAP_BGR5551
,
95 CLCD_CAP_565
= CLCD_CAP_RGB565
| CLCD_CAP_BGR565
,
96 CLCD_CAP_888
= CLCD_CAP_RGB888
| CLCD_CAP_BGR888
,
98 /* red/blue ordering */
99 CLCD_CAP_RGB
= CLCD_CAP_RGB444
| CLCD_CAP_RGB5551
|
100 CLCD_CAP_RGB565
| CLCD_CAP_RGB888
,
101 CLCD_CAP_BGR
= CLCD_CAP_BGR444
| CLCD_CAP_BGR5551
|
102 CLCD_CAP_BGR565
| CLCD_CAP_BGR888
,
104 CLCD_CAP_ALL
= CLCD_CAP_BGR
| CLCD_CAP_RGB
,
107 struct backlight_device
;
110 struct fb_videomode mode
;
111 signed short width
; /* width in mm */
112 signed short height
; /* height in mm */
120 unsigned int connector
;
121 struct backlight_device
*backlight
;
123 * If the B/R lines are switched between the CLCD
124 * and the panel we need to know this and not try to
125 * compensate with the BGR bit in the control register.
136 unsigned long pixclock
;
142 * the board-type specific routines
148 * Optional. Hardware capability flags.
153 * Optional. Check whether the var structure is acceptable
156 int (*check
)(struct clcd_fb
*fb
, struct fb_var_screeninfo
*var
);
159 * Compulsory. Decode fb->fb.var into regs->*. In the case of
160 * fixed timing, set regs->* to the register values required.
162 void (*decode
)(struct clcd_fb
*fb
, struct clcd_regs
*regs
);
165 * Optional. Disable any extra display hardware.
167 void (*disable
)(struct clcd_fb
*);
170 * Optional. Enable any extra display hardware.
172 void (*enable
)(struct clcd_fb
*);
175 * Setup platform specific parts of CLCD driver
177 int (*setup
)(struct clcd_fb
*);
180 * mmap the framebuffer memory
182 int (*mmap
)(struct clcd_fb
*, struct vm_area_struct
*);
185 * Remove platform specific parts of CLCD driver
187 void (*remove
)(struct clcd_fb
*);
194 * struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
195 * variant information
197 * @clock_timregs: the CLCD needs to be clocked when accessing the
198 * timer registers, or the hardware will hang.
199 * @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
200 * so that RGB accesses 3 bytes at a time, not just on even 32bit
201 * boundaries, packing the pixel data in memory. ST Microelectronics
203 * @st_bitmux_control: ST Microelectronics have implemented output
204 * bit line multiplexing into the CLCD control register. This indicates
205 * that we need to use this.
206 * @init_board: custom board init function for this variant
207 * @init_panel: custom panel init function for this variant
209 struct clcd_vendor_data
{
211 bool packed_24_bit_pixels
;
212 bool st_bitmux_control
;
213 int (*init_board
)(struct amba_device
*adev
,
214 struct clcd_board
*board
);
215 int (*init_panel
)(struct clcd_fb
*fb
,
216 struct device_node
*panel
);
219 /* this data structure describes each frame buffer device we find */
222 struct amba_device
*dev
;
224 struct clcd_vendor_data
*vendor
;
225 struct clcd_panel
*panel
;
226 struct clcd_board
*board
;
236 static inline void clcdfb_decode(struct clcd_fb
*fb
, struct clcd_regs
*regs
)
238 struct fb_var_screeninfo
*var
= &fb
->fb
.var
;
242 * Program the CLCD controller registers and start the CLCD
244 val
= ((var
->xres
/ 16) - 1) << 2;
245 val
|= (var
->hsync_len
- 1) << 8;
246 val
|= (var
->right_margin
- 1) << 16;
247 val
|= (var
->left_margin
- 1) << 24;
251 if (fb
->panel
->cntl
& CNTL_LCDDUAL
)
254 val
|= (var
->vsync_len
- 1) << 10;
255 val
|= var
->lower_margin
<< 16;
256 val
|= var
->upper_margin
<< 24;
259 val
= fb
->panel
->tim2
;
260 val
|= var
->sync
& FB_SYNC_HOR_HIGH_ACT
? 0 : TIM2_IHS
;
261 val
|= var
->sync
& FB_SYNC_VERT_HIGH_ACT
? 0 : TIM2_IVS
;
263 cpl
= var
->xres_virtual
;
264 if (fb
->panel
->cntl
& CNTL_LCDTFT
) /* TFT */
266 else if (!var
->grayscale
) /* STN color */
268 else if (fb
->panel
->cntl
& CNTL_LCDMONO8
) /* STN monochrome, 8bit */
270 else /* STN monochrome, 4bit */
273 regs
->tim2
= val
| ((cpl
- 1) << 16);
275 regs
->tim3
= fb
->panel
->tim3
;
277 val
= fb
->panel
->cntl
;
281 if (fb
->panel
->caps
&& fb
->board
->caps
&& var
->bits_per_pixel
>= 16) {
283 * if board and panel supply capabilities, we can support
284 * changing BGR/RGB depending on supplied parameters. Here
285 * we switch to what the framebuffer is providing if need
286 * be, so if the framebuffer is BGR but the display connection
287 * is RGB (first case) we switch it around. Vice versa mutatis
288 * mutandis if the framebuffer is RGB but the display connection
289 * is BGR, we flip it around.
291 if (var
->red
.offset
== 0)
295 if (fb
->panel
->bgr_connection
)
299 switch (var
->bits_per_pixel
) {
314 * PL110 cannot choose between 5551 and 565 modes in its
315 * control register. It is possible to use 565 with
316 * custom external wiring.
318 if (amba_part(fb
->dev
) == 0x110 ||
319 var
->green
.length
== 5)
320 val
|= CNTL_LCDBPP16
;
321 else if (var
->green
.length
== 6)
322 val
|= CNTL_LCDBPP16_565
;
324 val
|= CNTL_LCDBPP16_444
;
327 /* Modified variant supporting 24 bit packed pixels */
328 val
|= CNTL_ST_LCDBPP24_PACKED
;
331 val
|= CNTL_LCDBPP24
;
336 regs
->pixclock
= var
->pixclock
;
339 static inline int clcdfb_check(struct clcd_fb
*fb
, struct fb_var_screeninfo
*var
)
341 var
->xres_virtual
= var
->xres
= (var
->xres
+ 15) & ~15;
342 var
->yres_virtual
= var
->yres
= (var
->yres
+ 1) & ~1;
344 #define CHECK(e,l,h) (var->e < l || var->e > h)
345 if (CHECK(right_margin
, (5+1), 256) || /* back porch */
346 CHECK(left_margin
, (5+1), 256) || /* front porch */
347 CHECK(hsync_len
, (5+1), 256) ||
349 var
->lower_margin
> 255 || /* back porch */
350 var
->upper_margin
> 255 || /* front porch */
351 var
->vsync_len
> 32 ||
356 /* single panel mode: PCD = max(PCD, 1) */
357 /* dual panel mode: PCD = max(PCD, 5) */
360 * You can't change the grayscale setting, and
361 * we can only do non-interlaced video.
363 if (var
->grayscale
!= fb
->fb
.var
.grayscale
||
364 (var
->vmode
& FB_VMODE_MASK
) != FB_VMODE_NONINTERLACED
)
367 #define CHECK(e) (var->e != fb->fb.var.e)
368 if (fb
->panel
->fixedtimings
&&
371 CHECK(bits_per_pixel
) ||
373 CHECK(left_margin
) ||
374 CHECK(right_margin
) ||
375 CHECK(upper_margin
) ||
376 CHECK(lower_margin
) ||
384 var
->accel_flags
= 0;
This page took 0.039837 seconds and 6 git commands to generate.