1 #ifndef _LINUX_BRCMPHY_H
2 #define _LINUX_BRCMPHY_H
4 #define PHY_ID_BCM50610 0x0143bd60
5 #define PHY_ID_BCM50610M 0x0143bd70
6 #define PHY_ID_BCM5241 0x0143bc30
7 #define PHY_ID_BCMAC131 0x0143bc70
8 #define PHY_ID_BCM5481 0x0143bca0
9 #define PHY_ID_BCM5482 0x0143bcb0
10 #define PHY_ID_BCM5411 0x00206070
11 #define PHY_ID_BCM5421 0x002060e0
12 #define PHY_ID_BCM5464 0x002060b0
13 #define PHY_ID_BCM5461 0x002060c0
14 #define PHY_ID_BCM57780 0x03625d90
16 #define PHY_ID_BCM7250 0xae025280
17 #define PHY_ID_BCM7364 0xae025260
18 #define PHY_ID_BCM7366 0x600d8490
19 #define PHY_ID_BCM7425 0x03625e60
20 #define PHY_ID_BCM7429 0x600d8730
21 #define PHY_ID_BCM7439 0x600d8480
22 #define PHY_ID_BCM7445 0x600d8510
24 #define PHY_BCM_OUI_MASK 0xfffffc00
25 #define PHY_BCM_OUI_1 0x00206000
26 #define PHY_BCM_OUI_2 0x0143bc00
27 #define PHY_BCM_OUI_3 0x03625c00
28 #define PHY_BCM_OUI_4 0x600d8400
29 #define PHY_BCM_OUI_5 0x03625e00
30 #define PHY_BCM_OUI_6 0xae025000
32 #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
33 #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
34 #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
35 #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
36 #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
37 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
38 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
39 #define PHY_BRCM_STD_IBND_DISABLE 0x00000800
40 #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
41 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
42 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
43 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
44 /* Broadcom BCM7xxx specific workarounds */
45 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
46 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
47 #define PHY_BCM_FLAGS_VALID 0x80000000
49 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
50 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
51 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
52 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
54 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
55 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
57 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
58 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
59 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
60 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
62 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
63 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
64 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
65 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
66 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
67 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
68 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
69 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
70 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
71 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
72 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
73 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
74 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
75 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
76 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
77 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
78 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
79 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
81 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
82 #define MII_BCM54XX_SHD_WRITE 0x8000
83 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
84 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
87 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
89 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
90 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
91 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
93 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
94 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
95 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
96 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
98 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
101 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
102 * BCM5482, and possibly some others.
104 #define BCM_LED_SRC_LINKSPD1 0x0
105 #define BCM_LED_SRC_LINKSPD2 0x1
106 #define BCM_LED_SRC_XMITLED 0x2
107 #define BCM_LED_SRC_ACTIVITYLED 0x3
108 #define BCM_LED_SRC_FDXLED 0x4
109 #define BCM_LED_SRC_SLAVE 0x5
110 #define BCM_LED_SRC_INTR 0x6
111 #define BCM_LED_SRC_QUALITY 0x7
112 #define BCM_LED_SRC_RCVLED 0x8
113 #define BCM_LED_SRC_MULTICOLOR1 0xa
114 #define BCM_LED_SRC_OPENSHORT 0xb
115 #define BCM_LED_SRC_OFF 0xe /* Tied high */
116 #define BCM_LED_SRC_ON 0xf /* Tied low */
120 * BCM5482: Shadow registers
121 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
122 * register to access.
124 /* 00101: Spare Control Register 3 */
125 #define BCM54XX_SHD_SCR3 0x05
126 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
127 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
128 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
130 /* 01010: Auto Power-Down */
131 #define BCM54XX_SHD_APD 0x0a
132 #define BCM54XX_SHD_APD_EN 0x0020
134 #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
135 /* LED3 / ~LINKSPD[2] selector */
136 #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
137 /* LED1 / ~LINKSPD[1] selector */
138 #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
139 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
140 #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
141 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
142 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
143 #define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
144 #define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
148 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
150 #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
151 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
152 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
153 #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
154 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
155 #define MII_BCM54XX_EXP_EXP08 0x0F08
156 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
157 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
158 #define MII_BCM54XX_EXP_EXP75 0x0f75
159 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
160 #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
161 #define MII_BCM54XX_EXP_EXP96 0x0f96
162 #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
163 #define MII_BCM54XX_EXP_EXP97 0x0f97
164 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
167 * BCM5482: Secondary SerDes registers
169 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
170 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
171 #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
172 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
173 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
176 /*****************************************************************************/
177 /* Fast Ethernet Transceiver definitions. */
178 /*****************************************************************************/
180 #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
181 #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
182 #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
183 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
184 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
185 #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
187 #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
188 #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
191 /*** Shadow register definitions ***/
193 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
194 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
196 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
197 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
198 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
200 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
201 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
204 * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
205 * 0x1c shadow registers.
207 static inline int bcm54xx_shadow_read(struct phy_device
*phydev
, u16 shadow
)
209 phy_write(phydev
, MII_BCM54XX_SHD
, MII_BCM54XX_SHD_VAL(shadow
));
210 return MII_BCM54XX_SHD_DATA(phy_read(phydev
, MII_BCM54XX_SHD
));
213 static inline int bcm54xx_shadow_write(struct phy_device
*phydev
, u16 shadow
,
216 return phy_write(phydev
, MII_BCM54XX_SHD
,
217 MII_BCM54XX_SHD_WRITE
|
218 MII_BCM54XX_SHD_VAL(shadow
) |
219 MII_BCM54XX_SHD_DATA(val
));
222 #define BRCM_CL45VEN_EEE_CONTROL 0x803d
223 #define LPI_FEATURE_EN 0x8000
224 #define LPI_FEATURE_EN_DIG1000X 0x4000
226 #endif /* _LINUX_BRCMPHY_H */
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