2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
14 #include <linux/clk.h>
18 #ifdef CONFIG_COMMON_CLK
21 * flags used across common struct clk. these flags should only affect the
22 * top-level framework. custom flags for dealing with hardware specifics
23 * belong in struct clk_foo
25 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
27 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
28 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
29 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
30 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
31 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
32 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
33 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
41 * struct clk_ops - Callback operations for hardware clocks; these are to
42 * be provided by the clock implementation, and will be called by drivers
43 * through the clk_* api.
45 * @prepare: Prepare the clock for enabling. This must not return until
46 * the clock is fully prepared, and it's safe to call clk_enable.
47 * This callback is intended to allow clock implementations to
48 * do any initialisation that may sleep. Called with
51 * @unprepare: Release the clock from its prepared state. This will typically
52 * undo any work done in the @prepare callback. Called with
55 * @is_prepared: Queries the hardware to determine if the clock is prepared.
56 * This function is allowed to sleep. Optional, if this op is not
57 * set then the prepare count will be used.
59 * @unprepare_unused: Unprepare the clock atomically. Only called from
60 * clk_disable_unused for prepare clocks with special needs.
61 * Called with prepare mutex held. This function may sleep.
63 * @enable: Enable the clock atomically. This must not return until the
64 * clock is generating a valid clock signal, usable by consumer
65 * devices. Called with enable_lock held. This function must not
68 * @disable: Disable the clock atomically. Called with enable_lock held.
69 * This function must not sleep.
71 * @is_enabled: Queries the hardware to determine if the clock is enabled.
72 * This function must not sleep. Optional, if this op is not
73 * set then the enable count will be used.
75 * @disable_unused: Disable the clock atomically. Only called from
76 * clk_disable_unused for gate clocks with special needs.
77 * Called with enable_lock held. This function must not
80 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
81 * parent rate is an input parameter. It is up to the caller to
82 * ensure that the prepare_mutex is held across this call.
83 * Returns the calculated rate. Optional, but recommended - if
84 * this op is not set then clock rate will be initialized to 0.
86 * @round_rate: Given a target rate as input, returns the closest rate actually
87 * supported by the clock. The parent rate is an input/output
90 * @determine_rate: Given a target rate as input, returns the closest rate
91 * actually supported by the clock, and optionally the parent clock
92 * that should be used to provide the clock rate.
94 * @set_parent: Change the input source of this clock; for clocks with multiple
95 * possible parents specify a new parent by passing in the index
96 * as a u8 corresponding to the parent in either the .parent_names
97 * or .parents arrays. This function in affect translates an
98 * array index into the value programmed into the hardware.
99 * Returns 0 on success, -EERROR otherwise.
101 * @get_parent: Queries the hardware to determine the parent of a clock. The
102 * return value is a u8 which specifies the index corresponding to
103 * the parent clock. This index can be applied to either the
104 * .parent_names or .parents arrays. In short, this function
105 * translates the parent value read from hardware into an array
106 * index. Currently only called when the clock is initialized by
107 * __clk_init. This callback is mandatory for clocks with
108 * multiple parents. It is optional (and unnecessary) for clocks
109 * with 0 or 1 parents.
111 * @set_rate: Change the rate of this clock. The requested rate is specified
112 * by the second argument, which should typically be the return
113 * of .round_rate call. The third argument gives the parent rate
114 * which is likely helpful for most .set_rate implementation.
115 * Returns 0 on success, -EERROR otherwise.
117 * @set_rate_and_parent: Change the rate and the parent of this clock. The
118 * requested rate is specified by the second argument, which
119 * should typically be the return of .round_rate call. The
120 * third argument gives the parent rate which is likely helpful
121 * for most .set_rate_and_parent implementation. The fourth
122 * argument gives the parent index. This callback is optional (and
123 * unnecessary) for clocks with 0 or 1 parents as well as
124 * for clocks that can tolerate switching the rate and the parent
125 * separately via calls to .set_parent and .set_rate.
126 * Returns 0 on success, -EERROR otherwise.
128 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
129 * is expressed in ppb (parts per billion). The parent accuracy is
130 * an input parameter.
131 * Returns the calculated accuracy. Optional - if this op is not
132 * set then clock accuracy will be initialized to parent accuracy
133 * or 0 (perfect clock) if clock has no parent.
135 * @get_phase: Queries the hardware to get the current phase of a clock.
136 * Returned values are 0-359 degrees on success, negative
137 * error codes on failure.
139 * @set_phase: Shift the phase this clock signal in degrees specified
140 * by the second argument. Valid values for degrees are
141 * 0-359. Return 0 on success, otherwise -EERROR.
143 * @init: Perform platform-specific initialization magic.
144 * This is not not used by any of the basic clock types.
145 * Please consider other ways of solving initialization problems
146 * before using this callback, as its use is discouraged.
148 * @debug_init: Set up type-specific debugfs entries for this clock. This
149 * is called once, after the debugfs directory entry for this
150 * clock has been created. The dentry pointer representing that
151 * directory is provided as an argument. Called with
152 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
155 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
156 * implementations to split any work between atomic (enable) and sleepable
157 * (prepare) contexts. If enabling a clock requires code that might sleep,
158 * this must be done in clk_prepare. Clock enable code that will never be
159 * called in a sleepable context may be implemented in clk_enable.
161 * Typically, drivers will call clk_prepare when a clock may be needed later
162 * (eg. when a device is opened), and clk_enable when the clock is actually
163 * required (eg. from an interrupt). Note that clk_prepare MUST have been
164 * called before clk_enable.
167 int (*prepare
)(struct clk_hw
*hw
);
168 void (*unprepare
)(struct clk_hw
*hw
);
169 int (*is_prepared
)(struct clk_hw
*hw
);
170 void (*unprepare_unused
)(struct clk_hw
*hw
);
171 int (*enable
)(struct clk_hw
*hw
);
172 void (*disable
)(struct clk_hw
*hw
);
173 int (*is_enabled
)(struct clk_hw
*hw
);
174 void (*disable_unused
)(struct clk_hw
*hw
);
175 unsigned long (*recalc_rate
)(struct clk_hw
*hw
,
176 unsigned long parent_rate
);
177 long (*round_rate
)(struct clk_hw
*hw
, unsigned long rate
,
178 unsigned long *parent_rate
);
179 long (*determine_rate
)(struct clk_hw
*hw
,
181 unsigned long min_rate
,
182 unsigned long max_rate
,
183 unsigned long *best_parent_rate
,
184 struct clk_hw
**best_parent_hw
);
185 int (*set_parent
)(struct clk_hw
*hw
, u8 index
);
186 u8 (*get_parent
)(struct clk_hw
*hw
);
187 int (*set_rate
)(struct clk_hw
*hw
, unsigned long rate
,
188 unsigned long parent_rate
);
189 int (*set_rate_and_parent
)(struct clk_hw
*hw
,
191 unsigned long parent_rate
, u8 index
);
192 unsigned long (*recalc_accuracy
)(struct clk_hw
*hw
,
193 unsigned long parent_accuracy
);
194 int (*get_phase
)(struct clk_hw
*hw
);
195 int (*set_phase
)(struct clk_hw
*hw
, int degrees
);
196 void (*init
)(struct clk_hw
*hw
);
197 int (*debug_init
)(struct clk_hw
*hw
, struct dentry
*dentry
);
201 * struct clk_init_data - holds init data that's common to all clocks and is
202 * shared between the clock provider and the common clock framework.
205 * @ops: operations this clock supports
206 * @parent_names: array of string names for all possible parents
207 * @num_parents: number of possible parents
208 * @flags: framework-level hints and quirks
210 struct clk_init_data
{
212 const struct clk_ops
*ops
;
213 const char * const *parent_names
;
219 * struct clk_hw - handle for traversing from a struct clk to its corresponding
220 * hardware-specific structure. struct clk_hw should be declared within struct
221 * clk_foo and then referenced by the struct clk instance that uses struct
224 * @core: pointer to the struct clk_core instance that points back to this
225 * struct clk_hw instance
227 * @clk: pointer to the per-user struct clk instance that can be used to call
230 * @init: pointer to struct clk_init_data that contains the init data shared
231 * with the common clock framework.
234 struct clk_core
*core
;
236 const struct clk_init_data
*init
;
240 * DOC: Basic clock implementations common to many platforms
242 * Each basic clock hardware type is comprised of a structure describing the
243 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
244 * unique flags for that hardware type, a registration function and an
245 * alternative macro for static initialization
249 * struct clk_fixed_rate - fixed-rate clock
250 * @hw: handle between common and hardware-specific interfaces
251 * @fixed_rate: constant frequency of clock
253 struct clk_fixed_rate
{
255 unsigned long fixed_rate
;
256 unsigned long fixed_accuracy
;
260 extern const struct clk_ops clk_fixed_rate_ops
;
261 struct clk
*clk_register_fixed_rate(struct device
*dev
, const char *name
,
262 const char *parent_name
, unsigned long flags
,
263 unsigned long fixed_rate
);
264 struct clk
*clk_register_fixed_rate_with_accuracy(struct device
*dev
,
265 const char *name
, const char *parent_name
, unsigned long flags
,
266 unsigned long fixed_rate
, unsigned long fixed_accuracy
);
268 void of_fixed_clk_setup(struct device_node
*np
);
271 * struct clk_gate - gating clock
273 * @hw: handle between common and hardware-specific interfaces
274 * @reg: register controlling gate
275 * @bit_idx: single bit controlling gate
276 * @flags: hardware-specific flags
277 * @lock: register lock
279 * Clock which can gate its output. Implements .enable & .disable
282 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
283 * enable the clock. Setting this flag does the opposite: setting the bit
284 * disable the clock and clearing it enables the clock
285 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
286 * of this register, and mask of gate bits are in higher 16-bit of this
287 * register. While setting the gate bits, higher 16-bit should also be
288 * updated to indicate changing gate bits.
298 #define CLK_GATE_SET_TO_DISABLE BIT(0)
299 #define CLK_GATE_HIWORD_MASK BIT(1)
301 extern const struct clk_ops clk_gate_ops
;
302 struct clk
*clk_register_gate(struct device
*dev
, const char *name
,
303 const char *parent_name
, unsigned long flags
,
304 void __iomem
*reg
, u8 bit_idx
,
305 u8 clk_gate_flags
, spinlock_t
*lock
);
306 void clk_unregister_gate(struct clk
*clk
);
308 struct clk_div_table
{
314 * struct clk_divider - adjustable divider clock
316 * @hw: handle between common and hardware-specific interfaces
317 * @reg: register containing the divider
318 * @shift: shift to the divider bit field
319 * @width: width of the divider bit field
320 * @table: array of value/divider pairs, last entry should have div = 0
321 * @lock: register lock
323 * Clock with an adjustable divider affecting its output frequency. Implements
324 * .recalc_rate, .set_rate and .round_rate
327 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
328 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
329 * the raw value read from the register, with the value of zero considered
330 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
331 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
332 * the hardware register
333 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
334 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
335 * Some hardware implementations gracefully handle this case and allow a
336 * zero divisor by not modifying their input clock
337 * (divide by one / bypass).
338 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
339 * of this register, and mask of divider bits are in higher 16-bit of this
340 * register. While setting the divider bits, higher 16-bit should also be
341 * updated to indicate changing divider bits.
342 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
343 * to the closest integer instead of the up one.
344 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
345 * not be changed by the clock framework.
353 const struct clk_div_table
*table
;
357 #define CLK_DIVIDER_ONE_BASED BIT(0)
358 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
359 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
360 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
361 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
362 #define CLK_DIVIDER_READ_ONLY BIT(5)
364 extern const struct clk_ops clk_divider_ops
;
366 unsigned long divider_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
,
367 unsigned int val
, const struct clk_div_table
*table
,
368 unsigned long flags
);
369 long divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
370 unsigned long *prate
, const struct clk_div_table
*table
,
371 u8 width
, unsigned long flags
);
372 int divider_get_val(unsigned long rate
, unsigned long parent_rate
,
373 const struct clk_div_table
*table
, u8 width
,
374 unsigned long flags
);
376 struct clk
*clk_register_divider(struct device
*dev
, const char *name
,
377 const char *parent_name
, unsigned long flags
,
378 void __iomem
*reg
, u8 shift
, u8 width
,
379 u8 clk_divider_flags
, spinlock_t
*lock
);
380 struct clk
*clk_register_divider_table(struct device
*dev
, const char *name
,
381 const char *parent_name
, unsigned long flags
,
382 void __iomem
*reg
, u8 shift
, u8 width
,
383 u8 clk_divider_flags
, const struct clk_div_table
*table
,
385 void clk_unregister_divider(struct clk
*clk
);
388 * struct clk_mux - multiplexer clock
390 * @hw: handle between common and hardware-specific interfaces
391 * @reg: register controlling multiplexer
392 * @shift: shift to multiplexer bit field
393 * @width: width of mutliplexer bit field
394 * @flags: hardware-specific flags
395 * @lock: register lock
397 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
401 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
402 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
403 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
404 * register, and mask of mux bits are in higher 16-bit of this register.
405 * While setting the mux bits, higher 16-bit should also be updated to
406 * indicate changing mux bits.
407 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
420 #define CLK_MUX_INDEX_ONE BIT(0)
421 #define CLK_MUX_INDEX_BIT BIT(1)
422 #define CLK_MUX_HIWORD_MASK BIT(2)
423 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
424 #define CLK_MUX_ROUND_CLOSEST BIT(4)
426 extern const struct clk_ops clk_mux_ops
;
427 extern const struct clk_ops clk_mux_ro_ops
;
429 struct clk
*clk_register_mux(struct device
*dev
, const char *name
,
430 const char * const *parent_names
, u8 num_parents
,
432 void __iomem
*reg
, u8 shift
, u8 width
,
433 u8 clk_mux_flags
, spinlock_t
*lock
);
435 struct clk
*clk_register_mux_table(struct device
*dev
, const char *name
,
436 const char * const *parent_names
, u8 num_parents
,
438 void __iomem
*reg
, u8 shift
, u32 mask
,
439 u8 clk_mux_flags
, u32
*table
, spinlock_t
*lock
);
441 void clk_unregister_mux(struct clk
*clk
);
443 void of_fixed_factor_clk_setup(struct device_node
*node
);
446 * struct clk_fixed_factor - fixed multiplier and divider clock
448 * @hw: handle between common and hardware-specific interfaces
452 * Clock with a fixed multiplier and divider. The output frequency is the
453 * parent clock rate divided by div and multiplied by mult.
454 * Implements .recalc_rate, .set_rate and .round_rate
457 struct clk_fixed_factor
{
463 extern const struct clk_ops clk_fixed_factor_ops
;
464 struct clk
*clk_register_fixed_factor(struct device
*dev
, const char *name
,
465 const char *parent_name
, unsigned long flags
,
466 unsigned int mult
, unsigned int div
);
469 * struct clk_fractional_divider - adjustable fractional divider clock
471 * @hw: handle between common and hardware-specific interfaces
472 * @reg: register containing the divider
473 * @mshift: shift to the numerator bit field
474 * @mwidth: width of the numerator bit field
475 * @nshift: shift to the denominator bit field
476 * @nwidth: width of the denominator bit field
477 * @lock: register lock
479 * Clock with adjustable fractional divider affecting its output frequency.
482 struct clk_fractional_divider
{
493 extern const struct clk_ops clk_fractional_divider_ops
;
494 struct clk
*clk_register_fractional_divider(struct device
*dev
,
495 const char *name
, const char *parent_name
, unsigned long flags
,
496 void __iomem
*reg
, u8 mshift
, u8 mwidth
, u8 nshift
, u8 nwidth
,
497 u8 clk_divider_flags
, spinlock_t
*lock
);
500 * struct clk_composite - aggregate clock of mux, divider and gate clocks
502 * @hw: handle between common and hardware-specific interfaces
503 * @mux_hw: handle between composite and hardware-specific mux clock
504 * @rate_hw: handle between composite and hardware-specific rate clock
505 * @gate_hw: handle between composite and hardware-specific gate clock
506 * @mux_ops: clock ops for mux
507 * @rate_ops: clock ops for rate
508 * @gate_ops: clock ops for gate
510 struct clk_composite
{
514 struct clk_hw
*mux_hw
;
515 struct clk_hw
*rate_hw
;
516 struct clk_hw
*gate_hw
;
518 const struct clk_ops
*mux_ops
;
519 const struct clk_ops
*rate_ops
;
520 const struct clk_ops
*gate_ops
;
523 struct clk
*clk_register_composite(struct device
*dev
, const char *name
,
524 const char * const *parent_names
, int num_parents
,
525 struct clk_hw
*mux_hw
, const struct clk_ops
*mux_ops
,
526 struct clk_hw
*rate_hw
, const struct clk_ops
*rate_ops
,
527 struct clk_hw
*gate_hw
, const struct clk_ops
*gate_ops
,
528 unsigned long flags
);
531 * struct clk_gpio_gate - gpio gated clock
533 * @hw: handle between common and hardware-specific interfaces
534 * @gpiod: gpio descriptor
536 * Clock with a gpio control for enabling and disabling the parent clock.
537 * Implements .enable, .disable and .is_enabled
542 struct gpio_desc
*gpiod
;
545 extern const struct clk_ops clk_gpio_gate_ops
;
546 struct clk
*clk_register_gpio_gate(struct device
*dev
, const char *name
,
547 const char *parent_name
, unsigned gpio
, bool active_low
,
548 unsigned long flags
);
550 void of_gpio_clk_gate_setup(struct device_node
*node
);
553 * clk_register - allocate a new clock, register it and return an opaque cookie
554 * @dev: device that is registering this clock
555 * @hw: link to hardware-specific clock data
557 * clk_register is the primary interface for populating the clock tree with new
558 * clock nodes. It returns a pointer to the newly allocated struct clk which
559 * cannot be dereferenced by driver code but may be used in conjuction with the
560 * rest of the clock API. In the event of an error clk_register will return an
561 * error code; drivers must test for an error code after calling clk_register.
563 struct clk
*clk_register(struct device
*dev
, struct clk_hw
*hw
);
564 struct clk
*devm_clk_register(struct device
*dev
, struct clk_hw
*hw
);
566 void clk_unregister(struct clk
*clk
);
567 void devm_clk_unregister(struct device
*dev
, struct clk
*clk
);
569 /* helper functions */
570 const char *__clk_get_name(struct clk
*clk
);
571 struct clk_hw
*__clk_get_hw(struct clk
*clk
);
572 u8
__clk_get_num_parents(struct clk
*clk
);
573 struct clk
*__clk_get_parent(struct clk
*clk
);
574 struct clk
*clk_get_parent_by_index(struct clk
*clk
, u8 index
);
575 unsigned int __clk_get_enable_count(struct clk
*clk
);
576 unsigned long __clk_get_rate(struct clk
*clk
);
577 unsigned long __clk_get_flags(struct clk
*clk
);
578 bool __clk_is_prepared(struct clk
*clk
);
579 bool __clk_is_enabled(struct clk
*clk
);
580 struct clk
*__clk_lookup(const char *name
);
581 long __clk_mux_determine_rate(struct clk_hw
*hw
, unsigned long rate
,
582 unsigned long min_rate
,
583 unsigned long max_rate
,
584 unsigned long *best_parent_rate
,
585 struct clk_hw
**best_parent_p
);
586 unsigned long __clk_determine_rate(struct clk_hw
*core
,
588 unsigned long min_rate
,
589 unsigned long max_rate
);
590 long __clk_mux_determine_rate_closest(struct clk_hw
*hw
, unsigned long rate
,
591 unsigned long min_rate
,
592 unsigned long max_rate
,
593 unsigned long *best_parent_rate
,
594 struct clk_hw
**best_parent_p
);
595 void clk_hw_reparent(struct clk_hw
*hw
, struct clk_hw
*new_parent
);
597 static inline void __clk_hw_set_clk(struct clk_hw
*dst
, struct clk_hw
*src
)
600 dst
->core
= src
->core
;
604 * FIXME clock api without lock protection
606 unsigned long __clk_round_rate(struct clk
*clk
, unsigned long rate
);
610 typedef void (*of_clk_init_cb_t
)(struct device_node
*);
612 struct clk_onecell_data
{
614 unsigned int clk_num
;
617 extern struct of_device_id __clk_of_table
;
619 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
622 int of_clk_add_provider(struct device_node
*np
,
623 struct clk
*(*clk_src_get
)(struct of_phandle_args
*args
,
626 void of_clk_del_provider(struct device_node
*np
);
627 struct clk
*of_clk_src_simple_get(struct of_phandle_args
*clkspec
,
629 struct clk
*of_clk_src_onecell_get(struct of_phandle_args
*clkspec
, void *data
);
630 int of_clk_get_parent_count(struct device_node
*np
);
631 int of_clk_parent_fill(struct device_node
*np
, const char **parents
,
633 const char *of_clk_get_parent_name(struct device_node
*np
, int index
);
635 void of_clk_init(const struct of_device_id
*matches
);
637 #else /* !CONFIG_OF */
639 static inline int of_clk_add_provider(struct device_node
*np
,
640 struct clk
*(*clk_src_get
)(struct of_phandle_args
*args
,
646 #define of_clk_del_provider(np) \
648 static inline struct clk
*of_clk_src_simple_get(
649 struct of_phandle_args
*clkspec
, void *data
)
651 return ERR_PTR(-ENOENT
);
653 static inline struct clk
*of_clk_src_onecell_get(
654 struct of_phandle_args
*clkspec
, void *data
)
656 return ERR_PTR(-ENOENT
);
658 static inline const char *of_clk_get_parent_name(struct device_node
*np
,
663 #define of_clk_init(matches) \
665 #endif /* CONFIG_OF */
668 * wrap access to peripherals in accessor routines
669 * for improved portability across platforms
672 #if IS_ENABLED(CONFIG_PPC)
674 static inline u32
clk_readl(u32 __iomem
*reg
)
676 return ioread32be(reg
);
679 static inline void clk_writel(u32 val
, u32 __iomem
*reg
)
681 iowrite32be(val
, reg
);
684 #else /* platform dependent I/O accessors */
686 static inline u32
clk_readl(u32 __iomem
*reg
)
691 static inline void clk_writel(u32 val
, u32 __iomem
*reg
)
696 #endif /* platform dependent I/O accessors */
698 #ifdef CONFIG_DEBUG_FS
699 struct dentry
*clk_debugfs_add_file(struct clk_hw
*hw
, char *name
, umode_t mode
,
700 void *data
, const struct file_operations
*fops
);
703 #endif /* CONFIG_COMMON_CLK */
704 #endif /* CLK_PROVIDER_H */