include/linux/cs5535.h

   1 /*
   2  * AMD CS5535/CS5536 definitions
   3  * Copyright (C) 2006  Advanced Micro Devices, Inc.
   4  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #ifndef _CS5535_H
  12 #define _CS5535_H
  13
  14 /* MSRs */
  15 #define MSR_GLIU_P2D_RO0        0x10000029
  16
  17 #define MSR_LX_GLD_MSR_CONFIG   0x48002001
  18 #define MSR_LX_MSR_PADSEL       0x48002011      /* NOT 0x48000011; the data
  19                                                  * sheet has the wrong value */
  20 #define MSR_GLCP_SYS_RSTPLL     0x4C000014
  21 #define MSR_GLCP_DOTPLL         0x4C000015
  22
  23 #define MSR_LBAR_SMB            0x5140000B
  24 #define MSR_LBAR_GPIO           0x5140000C
  25 #define MSR_LBAR_MFGPT          0x5140000D
  26 #define MSR_LBAR_ACPI           0x5140000E
  27 #define MSR_LBAR_PMS            0x5140000F
  28
  29 #define MSR_DIVIL_SOFT_RESET    0x51400017
  30
  31 #define MSR_PIC_YSEL_LOW        0x51400020
  32 #define MSR_PIC_YSEL_HIGH       0x51400021
  33 #define MSR_PIC_ZSEL_LOW        0x51400022
  34 #define MSR_PIC_ZSEL_HIGH       0x51400023
  35 #define MSR_PIC_IRQM_LPC        0x51400025
  36
  37 #define MSR_MFGPT_IRQ           0x51400028
  38 #define MSR_MFGPT_NR            0x51400029
  39 #define MSR_MFGPT_SETUP         0x5140002B
  40
  41 #define MSR_LX_SPARE_MSR        0x80000011      /* DC-specific */
  42
  43 #define MSR_GX_GLD_MSR_CONFIG   0xC0002001
  44 #define MSR_GX_MSR_PADSEL       0xC0002011
  45
  46 /* resource sizes */
  47 #define LBAR_GPIO_SIZE          0xFF
  48 #define LBAR_MFGPT_SIZE         0x40
  49 #define LBAR_ACPI_SIZE          0x40
  50 #define LBAR_PMS_SIZE           0x80
  51
  52 /*
  53  * PMC registers (PMS block)
  54  * It is only safe to access these registers as dword accesses.
  55  * See CS5536 Specification Update erratas 17 & 18
  56  */
  57 #define CS5536_PM_SCLK          0x10
  58 #define CS5536_PM_IN_SLPCTL     0x20
  59 #define CS5536_PM_WKXD          0x34
  60 #define CS5536_PM_WKD           0x30
  61 #define CS5536_PM_SSC           0x54
  62
  63 /*
  64  * PM registers (ACPI block)
  65  * It is only safe to access these registers as dword accesses.
  66  * See CS5536 Specification Update erratas 17 & 18
  67  */
  68 #define CS5536_PM1_STS          0x00
  69 #define CS5536_PM1_EN           0x02
  70 #define CS5536_PM1_CNT          0x08
  71 #define CS5536_PM_GPE0_STS      0x18
  72
  73 /* VSA2 magic values */
  74 #define VSA_VRC_INDEX           0xAC1C
  75 #define VSA_VRC_DATA            0xAC1E
  76 #define VSA_VR_UNLOCK           0xFC53  /* unlock virtual register */
  77 #define VSA_VR_SIGNATURE        0x0003
  78 #define VSA_VR_MEM_SIZE         0x0200
  79 #define AMD_VSA_SIG             0x4132  /* signature is ascii 'VSA2' */
  80 #define GSW_VSA_SIG             0x534d  /* General Software signature */
  81
  82 #include <linux/io.h>
  83
  84 static inline int cs5535_has_vsa2(void)
  85 {
  86         static int has_vsa2 = -1;
  87
  88         if (has_vsa2 == -1) {
  89                 uint16_t val;
  90
  91                 /*
  92                  * The VSA has virtual registers that we can query for a
  93                  * signature.
  94                  */
  95                 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
  96                 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
  97
  98                 val = inw(VSA_VRC_DATA);
  99                 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
 100         }
 101
 102         return has_vsa2;
 103 }
 104
 105 /* GPIOs */
 106 #define GPIO_OUTPUT_VAL         0x00
 107 #define GPIO_OUTPUT_ENABLE      0x04
 108 #define GPIO_OUTPUT_OPEN_DRAIN  0x08
 109 #define GPIO_OUTPUT_INVERT      0x0C
 110 #define GPIO_OUTPUT_AUX1        0x10
 111 #define GPIO_OUTPUT_AUX2        0x14
 112 #define GPIO_PULL_UP            0x18
 113 #define GPIO_PULL_DOWN          0x1C
 114 #define GPIO_INPUT_ENABLE       0x20
 115 #define GPIO_INPUT_INVERT       0x24
 116 #define GPIO_INPUT_FILTER       0x28
 117 #define GPIO_INPUT_EVENT_COUNT  0x2C
 118 #define GPIO_READ_BACK          0x30
 119 #define GPIO_INPUT_AUX1         0x34
 120 #define GPIO_EVENTS_ENABLE      0x38
 121 #define GPIO_LOCK_ENABLE        0x3C
 122 #define GPIO_POSITIVE_EDGE_EN   0x40
 123 #define GPIO_NEGATIVE_EDGE_EN   0x44
 124 #define GPIO_POSITIVE_EDGE_STS  0x48
 125 #define GPIO_NEGATIVE_EDGE_STS  0x4C
 126
 127 #define GPIO_FLTR7_AMOUNT       0xD8
 128
 129 #define GPIO_MAP_X              0xE0
 130 #define GPIO_MAP_Y              0xE4
 131 #define GPIO_MAP_Z              0xE8
 132 #define GPIO_MAP_W              0xEC
 133
 134 #define GPIO_FE7_SEL            0xF7
 135
 136 void cs5535_gpio_set(unsigned offset, unsigned int reg);
 137 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
 138 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
 139 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
 140 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
 141
 142 /* MFGPTs */
 143
 144 #define MFGPT_MAX_TIMERS        8
 145 #define MFGPT_TIMER_ANY         (-1)
 146
 147 #define MFGPT_DOMAIN_WORKING    1
 148 #define MFGPT_DOMAIN_STANDBY    2
 149 #define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
 150
 151 #define MFGPT_CMP1              0
 152 #define MFGPT_CMP2              1
 153
 154 #define MFGPT_EVENT_IRQ         0
 155 #define MFGPT_EVENT_NMI         1
 156 #define MFGPT_EVENT_RESET       3
 157
 158 #define MFGPT_REG_CMP1          0
 159 #define MFGPT_REG_CMP2          2
 160 #define MFGPT_REG_COUNTER       4
 161 #define MFGPT_REG_SETUP         6
 162
 163 #define MFGPT_SETUP_CNTEN       (1 << 15)
 164 #define MFGPT_SETUP_CMP2        (1 << 14)
 165 #define MFGPT_SETUP_CMP1        (1 << 13)
 166 #define MFGPT_SETUP_SETUP       (1 << 12)
 167 #define MFGPT_SETUP_STOPEN      (1 << 11)
 168 #define MFGPT_SETUP_EXTEN       (1 << 10)
 169 #define MFGPT_SETUP_REVEN       (1 << 5)
 170 #define MFGPT_SETUP_CLKSEL      (1 << 4)
 171
 172 struct cs5535_mfgpt_timer;
 173
 174 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
 175                 uint16_t reg);
 176 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
 177                 uint16_t value);
 178
 179 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
 180                 int event, int enable);
 181 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
 182                 int *irq, int enable);
 183 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
 184                 int domain);
 185 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
 186
 187 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
 188                 int cmp, int *irq)
 189 {
 190         return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
 191 }
 192
 193 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
 194                 int cmp, int *irq)
 195 {
 196         return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
 197 }
 198
 199 #endif