2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/dma-direction.h>
27 #include <linux/bitmap.h>
33 * typedef dma_cookie_t - an opaque DMA cookie
35 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
37 typedef s32 dma_cookie_t
;
38 #define DMA_MIN_COOKIE 1
39 #define DMA_MAX_COOKIE INT_MAX
41 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
44 * enum dma_status - DMA transaction status
45 * @DMA_SUCCESS: transaction completed successfully
46 * @DMA_IN_PROGRESS: transaction not yet processed
47 * @DMA_PAUSED: transaction is paused
48 * @DMA_ERROR: transaction failed
58 * enum dma_transaction_type - DMA transaction types/indexes
60 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
61 * automatically set as dma devices are registered.
63 enum dma_transaction_type
{
78 /* last transaction type for creation of the capabilities mask */
79 #define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
83 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
84 * control completion, and communicate status.
85 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
87 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
88 * acknowledges receipt, i.e. has has a chance to establish any dependency
90 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
91 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
92 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
93 * (if not set, do the source dma-unmapping as page)
94 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
95 * (if not set, do the destination dma-unmapping as page)
96 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
97 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
98 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
99 * sources that were the result of a previous operation, in the case of a PQ
100 * operation it continues the calculation with new sources
101 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
102 * on the result of this operation
104 enum dma_ctrl_flags
{
105 DMA_PREP_INTERRUPT
= (1 << 0),
106 DMA_CTRL_ACK
= (1 << 1),
107 DMA_COMPL_SKIP_SRC_UNMAP
= (1 << 2),
108 DMA_COMPL_SKIP_DEST_UNMAP
= (1 << 3),
109 DMA_COMPL_SRC_UNMAP_SINGLE
= (1 << 4),
110 DMA_COMPL_DEST_UNMAP_SINGLE
= (1 << 5),
111 DMA_PREP_PQ_DISABLE_P
= (1 << 6),
112 DMA_PREP_PQ_DISABLE_Q
= (1 << 7),
113 DMA_PREP_CONTINUE
= (1 << 8),
114 DMA_PREP_FENCE
= (1 << 9),
118 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
119 * on a running channel.
120 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
121 * @DMA_PAUSE: pause ongoing transfers
122 * @DMA_RESUME: resume paused transfer
123 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
124 * that need to runtime reconfigure the slave channels (as opposed to passing
125 * configuration data in statically from the platform). An additional
126 * argument of struct dma_slave_config must be passed in with this
128 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
129 * into external start mode.
136 FSLDMA_EXTERNAL_START
,
140 * enum sum_check_bits - bit position of pq_check_flags
142 enum sum_check_bits
{
148 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
149 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
150 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
152 enum sum_check_flags
{
153 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
154 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
159 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
160 * See linux/cpumask.h
162 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
165 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
166 * @memcpy_count: transaction counter
167 * @bytes_transferred: byte counter
170 struct dma_chan_percpu
{
172 unsigned long memcpy_count
;
173 unsigned long bytes_transferred
;
177 * struct dma_chan - devices supply DMA channels, clients use them
178 * @device: ptr to the dma device who supplies this channel, always !%NULL
179 * @cookie: last cookie value returned to client
180 * @chan_id: channel ID for sysfs
181 * @dev: class device for sysfs
182 * @device_node: used to add this to the device chan list
183 * @local: per-cpu pointer to a struct dma_chan_percpu
184 * @client-count: how many clients are using this channel
185 * @table_count: number of appearances in the mem-to-mem allocation table
186 * @private: private data for certain client-channel associations
189 struct dma_device
*device
;
194 struct dma_chan_dev
*dev
;
196 struct list_head device_node
;
197 struct dma_chan_percpu __percpu
*local
;
204 * struct dma_chan_dev - relate sysfs device node to backing channel device
205 * @chan - driver channel device
206 * @device - sysfs device
207 * @dev_id - parent dma_device dev_id
208 * @idr_ref - reference count to gate release of dma_device dev_id
210 struct dma_chan_dev
{
211 struct dma_chan
*chan
;
212 struct device device
;
218 * enum dma_slave_buswidth - defines bus with of the DMA slave
219 * device, source or target buses
221 enum dma_slave_buswidth
{
222 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
223 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
224 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
225 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
226 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
230 * struct dma_slave_config - dma slave channel runtime config
231 * @direction: whether the data shall go in or out on this slave
232 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
233 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
234 * need to differentiate source and target addresses.
235 * @src_addr: this is the physical address where DMA slave data
236 * should be read (RX), if the source is memory this argument is
238 * @dst_addr: this is the physical address where DMA slave data
239 * should be written (TX), if the source is memory this argument
241 * @src_addr_width: this is the width in bytes of the source (RX)
242 * register where DMA data shall be read. If the source
243 * is memory this may be ignored depending on architecture.
244 * Legal values: 1, 2, 4, 8.
245 * @dst_addr_width: same as src_addr_width but for destination
246 * target (TX) mutatis mutandis.
247 * @src_maxburst: the maximum number of words (note: words, as in
248 * units of the src_addr_width member, not bytes) that can be sent
249 * in one burst to the device. Typically something like half the
250 * FIFO depth on I/O peripherals so you don't overflow it. This
251 * may or may not be applicable on memory sources.
252 * @dst_maxburst: same as src_maxburst but for destination target
255 * This struct is passed in as configuration data to a DMA engine
256 * in order to set up a certain channel for DMA transport at runtime.
257 * The DMA device/engine has to provide support for an additional
258 * command in the channel config interface, DMA_SLAVE_CONFIG
259 * and this struct will then be passed in as an argument to the
260 * DMA engine device_control() function.
262 * The rationale for adding configuration information to this struct
263 * is as follows: if it is likely that most DMA slave controllers in
264 * the world will support the configuration option, then make it
265 * generic. If not: if it is fixed so that it be sent in static from
266 * the platform data, then prefer to do that. Else, if it is neither
267 * fixed at runtime, nor generic enough (such as bus mastership on
268 * some CPU family and whatnot) then create a custom slave config
269 * struct and pass that, then make this config a member of that
270 * struct, if applicable.
272 struct dma_slave_config
{
273 enum dma_data_direction direction
;
276 enum dma_slave_buswidth src_addr_width
;
277 enum dma_slave_buswidth dst_addr_width
;
282 static inline const char *dma_chan_name(struct dma_chan
*chan
)
284 return dev_name(&chan
->dev
->device
);
287 void dma_chan_cleanup(struct kref
*kref
);
290 * typedef dma_filter_fn - callback filter for dma_request_channel
291 * @chan: channel to be reviewed
292 * @filter_param: opaque parameter passed through dma_request_channel
294 * When this optional parameter is specified in a call to dma_request_channel a
295 * suitable channel is passed to this routine for further dispositioning before
296 * being returned. Where 'suitable' indicates a non-busy channel that
297 * satisfies the given capability mask. It returns 'true' to indicate that the
298 * channel is suitable.
300 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
302 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
304 * struct dma_async_tx_descriptor - async transaction descriptor
305 * ---dma generic offload fields---
306 * @cookie: tracking cookie for this transaction, set to -EBUSY if
307 * this tx is sitting on a dependency list
308 * @flags: flags to augment operation preparation, control completion, and
310 * @phys: physical address of the descriptor
311 * @chan: target channel for this operation
312 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
313 * @callback: routine to call after this operation is complete
314 * @callback_param: general parameter to pass to the callback routine
315 * ---async_tx api specific fields---
316 * @next: at completion submit this descriptor
317 * @parent: pointer to the next level up in the dependency chain
318 * @lock: protect the parent and next pointers
320 struct dma_async_tx_descriptor
{
322 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
324 struct dma_chan
*chan
;
325 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
326 dma_async_tx_callback callback
;
327 void *callback_param
;
328 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
329 struct dma_async_tx_descriptor
*next
;
330 struct dma_async_tx_descriptor
*parent
;
335 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
336 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
339 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
342 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
346 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
349 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
352 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
356 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
362 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
364 spin_lock_bh(&txd
->lock
);
366 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
368 spin_unlock_bh(&txd
->lock
);
370 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
375 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
379 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
383 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
387 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
394 * struct dma_tx_state - filled in to report the status of
396 * @last: last completed DMA cookie
397 * @used: last issued DMA cookie (i.e. the one in progress)
398 * @residue: the remaining number of bytes left to transmit
399 * on the selected transfer for states DMA_IN_PROGRESS and
400 * DMA_PAUSED if this is implemented in the driver, else 0
402 struct dma_tx_state
{
409 * struct dma_device - info on the entity supplying DMA services
410 * @chancnt: how many DMA channels are supported
411 * @privatecnt: how many DMA channels are requested by dma_request_channel
412 * @channels: the list of struct dma_chan
413 * @global_node: list_head for global dma_device_list
414 * @cap_mask: one or more dma_capability flags
415 * @max_xor: maximum number of xor sources, 0 if no capability
416 * @max_pq: maximum number of PQ sources and PQ-continue capability
417 * @copy_align: alignment shift for memcpy operations
418 * @xor_align: alignment shift for xor operations
419 * @pq_align: alignment shift for pq operations
420 * @fill_align: alignment shift for memset operations
421 * @dev_id: unique device ID
422 * @dev: struct device reference for dma mapping api
423 * @device_alloc_chan_resources: allocate resources and return the
424 * number of allocated descriptors
425 * @device_free_chan_resources: release DMA channel's resources
426 * @device_prep_dma_memcpy: prepares a memcpy operation
427 * @device_prep_dma_xor: prepares a xor operation
428 * @device_prep_dma_xor_val: prepares a xor validation operation
429 * @device_prep_dma_pq: prepares a pq operation
430 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
431 * @device_prep_dma_memset: prepares a memset operation
432 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
433 * @device_prep_slave_sg: prepares a slave dma operation
434 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
435 * The function takes a buffer of size buf_len. The callback function will
436 * be called after period_len bytes have been transferred.
437 * @device_control: manipulate all pending operations on a channel, returns
439 * @device_tx_status: poll for transaction completion, the optional
440 * txstate parameter can be supplied with a pointer to get a
441 * struct with auxiliary transfer status information, otherwise the call
442 * will just return a simple status code
443 * @device_issue_pending: push pending transactions to hardware
447 unsigned int chancnt
;
448 unsigned int privatecnt
;
449 struct list_head channels
;
450 struct list_head global_node
;
451 dma_cap_mask_t cap_mask
;
452 unsigned short max_xor
;
453 unsigned short max_pq
;
458 #define DMA_HAS_PQ_CONTINUE (1 << 15)
463 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
464 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
466 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
467 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
468 size_t len
, unsigned long flags
);
469 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
470 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
471 unsigned int src_cnt
, size_t len
, unsigned long flags
);
472 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
473 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
474 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
475 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
476 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
477 unsigned int src_cnt
, const unsigned char *scf
,
478 size_t len
, unsigned long flags
);
479 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
480 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
481 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
482 enum sum_check_flags
*pqres
, unsigned long flags
);
483 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
484 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
485 unsigned long flags
);
486 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
487 struct dma_chan
*chan
, unsigned long flags
);
488 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
489 struct dma_chan
*chan
,
490 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
491 struct scatterlist
*src_sg
, unsigned int src_nents
,
492 unsigned long flags
);
494 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
495 struct dma_chan
*chan
, struct scatterlist
*sgl
,
496 unsigned int sg_len
, enum dma_data_direction direction
,
497 unsigned long flags
);
498 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
499 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
500 size_t period_len
, enum dma_data_direction direction
);
501 int (*device_control
)(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
504 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
506 struct dma_tx_state
*txstate
);
507 void (*device_issue_pending
)(struct dma_chan
*chan
);
510 static inline int dmaengine_device_control(struct dma_chan
*chan
,
511 enum dma_ctrl_cmd cmd
,
514 return chan
->device
->device_control(chan
, cmd
, arg
);
517 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
518 struct dma_slave_config
*config
)
520 return dmaengine_device_control(chan
, DMA_SLAVE_CONFIG
,
521 (unsigned long)config
);
524 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
526 return dmaengine_device_control(chan
, DMA_TERMINATE_ALL
, 0);
529 static inline int dmaengine_pause(struct dma_chan
*chan
)
531 return dmaengine_device_control(chan
, DMA_PAUSE
, 0);
534 static inline int dmaengine_resume(struct dma_chan
*chan
)
536 return dmaengine_device_control(chan
, DMA_RESUME
, 0);
539 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
541 return desc
->tx_submit(desc
);
544 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
550 mask
= (1 << align
) - 1;
551 if (mask
& (off1
| off2
| len
))
556 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
557 size_t off2
, size_t len
)
559 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
562 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
563 size_t off2
, size_t len
)
565 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
568 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
569 size_t off2
, size_t len
)
571 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
574 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
575 size_t off2
, size_t len
)
577 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
581 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
585 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
588 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
590 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
593 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
595 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
597 return (flags
& mask
) == mask
;
600 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
602 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
605 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
607 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
610 /* dma_maxpq - reduce maxpq in the face of continued operations
611 * @dma - dma device with PQ capability
612 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
614 * When an engine does not support native continuation we need 3 extra
615 * source slots to reuse P and Q with the following coefficients:
616 * 1/ {00} * P : remove P from Q', but use it as a source for P'
617 * 2/ {01} * Q : use Q to continue Q' calculation
618 * 3/ {00} * Q : subtract Q from P' to cancel (2)
620 * In the case where P is disabled we only need 1 extra source:
621 * 1/ {01} * Q : use Q to continue Q' calculation
623 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
625 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
626 return dma_dev_to_maxpq(dma
);
627 else if (dmaf_p_disabled_continue(flags
))
628 return dma_dev_to_maxpq(dma
) - 1;
629 else if (dmaf_continue(flags
))
630 return dma_dev_to_maxpq(dma
) - 3;
634 /* --- public DMA engine API --- */
636 #ifdef CONFIG_DMA_ENGINE
637 void dmaengine_get(void);
638 void dmaengine_put(void);
640 static inline void dmaengine_get(void)
643 static inline void dmaengine_put(void)
648 #ifdef CONFIG_NET_DMA
649 #define net_dmaengine_get() dmaengine_get()
650 #define net_dmaengine_put() dmaengine_put()
652 static inline void net_dmaengine_get(void)
655 static inline void net_dmaengine_put(void)
660 #ifdef CONFIG_ASYNC_TX_DMA
661 #define async_dmaengine_get() dmaengine_get()
662 #define async_dmaengine_put() dmaengine_put()
663 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
664 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
666 #define async_dma_find_channel(type) dma_find_channel(type)
667 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
669 static inline void async_dmaengine_get(void)
672 static inline void async_dmaengine_put(void)
675 static inline struct dma_chan
*
676 async_dma_find_channel(enum dma_transaction_type type
)
680 #endif /* CONFIG_ASYNC_TX_DMA */
682 dma_cookie_t
dma_async_memcpy_buf_to_buf(struct dma_chan
*chan
,
683 void *dest
, void *src
, size_t len
);
684 dma_cookie_t
dma_async_memcpy_buf_to_pg(struct dma_chan
*chan
,
685 struct page
*page
, unsigned int offset
, void *kdata
, size_t len
);
686 dma_cookie_t
dma_async_memcpy_pg_to_pg(struct dma_chan
*chan
,
687 struct page
*dest_pg
, unsigned int dest_off
, struct page
*src_pg
,
688 unsigned int src_off
, size_t len
);
689 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
690 struct dma_chan
*chan
);
692 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
694 tx
->flags
|= DMA_CTRL_ACK
;
697 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
699 tx
->flags
&= ~DMA_CTRL_ACK
;
702 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
704 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
707 #define first_dma_cap(mask) __first_dma_cap(&(mask))
708 static inline int __first_dma_cap(const dma_cap_mask_t
*srcp
)
710 return min_t(int, DMA_TX_TYPE_END
,
711 find_first_bit(srcp
->bits
, DMA_TX_TYPE_END
));
714 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
715 static inline int __next_dma_cap(int n
, const dma_cap_mask_t
*srcp
)
717 return min_t(int, DMA_TX_TYPE_END
,
718 find_next_bit(srcp
->bits
, DMA_TX_TYPE_END
, n
+1));
721 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
723 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
725 set_bit(tx_type
, dstp
->bits
);
728 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
730 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
732 clear_bit(tx_type
, dstp
->bits
);
735 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
736 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
738 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
741 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
743 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
745 return test_bit(tx_type
, srcp
->bits
);
748 #define for_each_dma_cap_mask(cap, mask) \
749 for ((cap) = first_dma_cap(mask); \
750 (cap) < DMA_TX_TYPE_END; \
751 (cap) = next_dma_cap((cap), (mask)))
754 * dma_async_issue_pending - flush pending transactions to HW
755 * @chan: target DMA channel
757 * This allows drivers to push copies to HW in batches,
758 * reducing MMIO writes where possible.
760 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
762 chan
->device
->device_issue_pending(chan
);
765 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
768 * dma_async_is_tx_complete - poll for transaction completion
770 * @cookie: transaction identifier to check status of
771 * @last: returns last completed cookie, can be NULL
772 * @used: returns last issued cookie, can be NULL
774 * If @last and @used are passed in, upon return they reflect the driver
775 * internal state and can be used with dma_async_is_complete() to check
776 * the status of multiple cookies without re-checking hardware state.
778 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
779 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
781 struct dma_tx_state state
;
782 enum dma_status status
;
784 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
792 #define dma_async_memcpy_complete(chan, cookie, last, used)\
793 dma_async_is_tx_complete(chan, cookie, last, used)
796 * dma_async_is_complete - test a cookie against chan state
797 * @cookie: transaction identifier to test status of
798 * @last_complete: last know completed transaction
799 * @last_used: last cookie value handed out
801 * dma_async_is_complete() is used in dma_async_memcpy_complete()
802 * the test logic is separated for lightweight testing of multiple cookies
804 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
805 dma_cookie_t last_complete
, dma_cookie_t last_used
)
807 if (last_complete
<= last_used
) {
808 if ((cookie
<= last_complete
) || (cookie
> last_used
))
811 if ((cookie
<= last_complete
) && (cookie
> last_used
))
814 return DMA_IN_PROGRESS
;
818 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
823 st
->residue
= residue
;
827 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
828 #ifdef CONFIG_DMA_ENGINE
829 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
830 void dma_issue_pending_all(void);
831 struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
, dma_filter_fn fn
, void *fn_param
);
832 void dma_release_channel(struct dma_chan
*chan
);
834 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
838 static inline void dma_issue_pending_all(void)
841 static inline struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
,
842 dma_filter_fn fn
, void *fn_param
)
846 static inline void dma_release_channel(struct dma_chan
*chan
)
851 /* --- DMA device --- */
853 int dma_async_device_register(struct dma_device
*device
);
854 void dma_async_device_unregister(struct dma_device
*device
);
855 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
856 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
857 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
859 /* --- Helper iov-locking functions --- */
861 struct dma_page_list
{
862 char __user
*base_address
;
867 struct dma_pinned_list
{
869 struct dma_page_list page_list
[0];
872 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
873 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
875 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
876 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
877 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
878 struct dma_pinned_list
*pinned_list
, struct page
*page
,
879 unsigned int offset
, size_t len
);
881 #endif /* DMAENGINE_H */