include/linux/dmaengine.h

   1 /*
   2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef DMAENGINE_H
  22 #define DMAENGINE_H
  23
  24 #include <linux/device.h>
  25 #include <linux/uio.h>
  26 #include <linux/kref.h>
  27 #include <linux/completion.h>
  28 #include <linux/rcupdate.h>
  29 #include <linux/dma-mapping.h>
  30
  31 /**
  32  * enum dma_event - resource PNP/power managment events
  33  * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
  34  * @DMA_RESOURCE_RESUME: DMA device returning to full power
  35  * @DMA_RESOURCE_ADDED: DMA device added to the system
  36  * @DMA_RESOURCE_REMOVED: DMA device removed from the system
  37  */
  38 enum dma_event {
  39         DMA_RESOURCE_SUSPEND,
  40         DMA_RESOURCE_RESUME,
  41         DMA_RESOURCE_ADDED,
  42         DMA_RESOURCE_REMOVED,
  43 };
  44
  45 /**
  46  * typedef dma_cookie_t - an opaque DMA cookie
  47  *
  48  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  49  */
  50 typedef s32 dma_cookie_t;
  51
  52 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
  53
  54 /**
  55  * enum dma_status - DMA transaction status
  56  * @DMA_SUCCESS: transaction completed successfully
  57  * @DMA_IN_PROGRESS: transaction not yet processed
  58  * @DMA_ERROR: transaction failed
  59  */
  60 enum dma_status {
  61         DMA_SUCCESS,
  62         DMA_IN_PROGRESS,
  63         DMA_ERROR,
  64 };
  65
  66 /**
  67  * enum dma_transaction_type - DMA transaction types/indexes
  68  */
  69 enum dma_transaction_type {
  70         DMA_MEMCPY,
  71         DMA_XOR,
  72         DMA_PQ_XOR,
  73         DMA_DUAL_XOR,
  74         DMA_PQ_UPDATE,
  75         DMA_ZERO_SUM,
  76         DMA_PQ_ZERO_SUM,
  77         DMA_MEMSET,
  78         DMA_MEMCPY_CRC32C,
  79         DMA_INTERRUPT,
  80 };
  81
  82 /* last transaction type for creation of the capabilities mask */
  83 #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
  84
  85 /**
  86  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
  87  * See linux/cpumask.h
  88  */
  89 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
  90
  91 /**
  92  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
  93  * @refcount: local_t used for open-coded "bigref" counting
  94  * @memcpy_count: transaction counter
  95  * @bytes_transferred: byte counter
  96  */
  97
  98 struct dma_chan_percpu {
  99         local_t refcount;
 100         /* stats */
 101         unsigned long memcpy_count;
 102         unsigned long bytes_transferred;
 103 };
 104
 105 /**
 106  * struct dma_chan - devices supply DMA channels, clients use them
 107  * @client: ptr to the client user of this chan, will be %NULL when unused
 108  * @device: ptr to the dma device who supplies this channel, always !%NULL
 109  * @cookie: last cookie value returned to client
 110  * @chan_id: channel ID for sysfs
 111  * @class_dev: class device for sysfs
 112  * @refcount: kref, used in "bigref" slow-mode
 113  * @slow_ref: indicates that the DMA channel is free
 114  * @rcu: the DMA channel's RCU head
 115  * @client_node: used to add this to the client chan list
 116  * @device_node: used to add this to the device chan list
 117  * @local: per-cpu pointer to a struct dma_chan_percpu
 118  */
 119 struct dma_chan {
 120         struct dma_client *client;
 121         struct dma_device *device;
 122         dma_cookie_t cookie;
 123
 124         /* sysfs */
 125         int chan_id;
 126         struct class_device class_dev;
 127
 128         struct kref refcount;
 129         int slow_ref;
 130         struct rcu_head rcu;
 131
 132         struct list_head client_node;
 133         struct list_head device_node;
 134         struct dma_chan_percpu *local;
 135 };
 136
 137 void dma_chan_cleanup(struct kref *kref);
 138
 139 static inline void dma_chan_get(struct dma_chan *chan)
 140 {
 141         if (unlikely(chan->slow_ref))
 142                 kref_get(&chan->refcount);
 143         else {
 144                 local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
 145                 put_cpu();
 146         }
 147 }
 148
 149 static inline void dma_chan_put(struct dma_chan *chan)
 150 {
 151         if (unlikely(chan->slow_ref))
 152                 kref_put(&chan->refcount, dma_chan_cleanup);
 153         else {
 154                 local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
 155                 put_cpu();
 156         }
 157 }
 158
 159 /*
 160  * typedef dma_event_callback - function pointer to a DMA event callback
 161  */
 162 typedef void (*dma_event_callback) (struct dma_client *client,
 163                 struct dma_chan *chan, enum dma_event event);
 164
 165 /**
 166  * struct dma_client - info on the entity making use of DMA services
 167  * @event_callback: func ptr to call when something happens
 168  * @chan_count: number of chans allocated
 169  * @chans_desired: number of chans requested. Can be +/- chan_count
 170  * @lock: protects access to the channels list
 171  * @channels: the list of DMA channels allocated
 172  * @global_node: list_head for global dma_client_list
 173  */
 174 struct dma_client {
 175         dma_event_callback      event_callback;
 176         unsigned int            chan_count;
 177         unsigned int            chans_desired;
 178
 179         spinlock_t              lock;
 180         struct list_head        channels;
 181         struct list_head        global_node;
 182 };
 183
 184 typedef void (*dma_async_tx_callback)(void *dma_async_param);
 185 /**
 186  * struct dma_async_tx_descriptor - async transaction descriptor
 187  * ---dma generic offload fields---
 188  * @cookie: tracking cookie for this transaction, set to -EBUSY if
 189  *      this tx is sitting on a dependency list
 190  * @ack: the descriptor can not be reused until the client acknowledges
 191  *      receipt, i.e. has has a chance to establish any dependency chains
 192  * @phys: physical address of the descriptor
 193  * @tx_list: driver common field for operations that require multiple
 194  *      descriptors
 195  * @chan: target channel for this operation
 196  * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 197  * @tx_set_dest: set a destination address in a hardware descriptor
 198  * @tx_set_src: set a source address in a hardware descriptor
 199  * @callback: routine to call after this operation is complete
 200  * @callback_param: general parameter to pass to the callback routine
 201  * ---async_tx api specific fields---
 202  * @depend_list: at completion this list of transactions are submitted
 203  * @depend_node: allow this transaction to be executed after another
 204  *      transaction has completed, possibly on another channel
 205  * @parent: pointer to the next level up in the dependency chain
 206  * @lock: protect the dependency list
 207  */
 208 struct dma_async_tx_descriptor {
 209         dma_cookie_t cookie;
 210         int ack;
 211         dma_addr_t phys;
 212         struct list_head tx_list;
 213         struct dma_chan *chan;
 214         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
 215         void (*tx_set_dest)(dma_addr_t addr,
 216                 struct dma_async_tx_descriptor *tx, int index);
 217         void (*tx_set_src)(dma_addr_t addr,
 218                 struct dma_async_tx_descriptor *tx, int index);
 219         dma_async_tx_callback callback;
 220         void *callback_param;
 221         struct list_head depend_list;
 222         struct list_head depend_node;
 223         struct dma_async_tx_descriptor *parent;
 224         spinlock_t lock;
 225 };
 226
 227 /**
 228  * struct dma_device - info on the entity supplying DMA services
 229  * @chancnt: how many DMA channels are supported
 230  * @channels: the list of struct dma_chan
 231  * @global_node: list_head for global dma_device_list
 232  * @cap_mask: one or more dma_capability flags
 233  * @max_xor: maximum number of xor sources, 0 if no capability
 234  * @refcount: reference count
 235  * @done: IO completion struct
 236  * @dev_id: unique device ID
 237  * @dev: struct device reference for dma mapping api
 238  * @device_alloc_chan_resources: allocate resources and return the
 239  *      number of allocated descriptors
 240  * @device_free_chan_resources: release DMA channel's resources
 241  * @device_prep_dma_memcpy: prepares a memcpy operation
 242  * @device_prep_dma_xor: prepares a xor operation
 243  * @device_prep_dma_zero_sum: prepares a zero_sum operation
 244  * @device_prep_dma_memset: prepares a memset operation
 245  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 246  * @device_dependency_added: async_tx notifies the channel about new deps
 247  * @device_issue_pending: push pending transactions to hardware
 248  */
 249 struct dma_device {
 250
 251         unsigned int chancnt;
 252         struct list_head channels;
 253         struct list_head global_node;
 254         dma_cap_mask_t  cap_mask;
 255         int max_xor;
 256
 257         struct kref refcount;
 258         struct completion done;
 259
 260         int dev_id;
 261         struct device *dev;
 262
 263         int (*device_alloc_chan_resources)(struct dma_chan *chan);
 264         void (*device_free_chan_resources)(struct dma_chan *chan);
 265
 266         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
 267                 struct dma_chan *chan, size_t len, int int_en);
 268         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
 269                 struct dma_chan *chan, unsigned int src_cnt, size_t len,
 270                 int int_en);
 271         struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
 272                 struct dma_chan *chan, unsigned int src_cnt, size_t len,
 273                 u32 *result, int int_en);
 274         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
 275                 struct dma_chan *chan, int value, size_t len, int int_en);
 276         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
 277                 struct dma_chan *chan);
 278
 279         void (*device_dependency_added)(struct dma_chan *chan);
 280         enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
 281                         dma_cookie_t cookie, dma_cookie_t *last,
 282                         dma_cookie_t *used);
 283         void (*device_issue_pending)(struct dma_chan *chan);
 284 };
 285
 286 /* --- public DMA engine API --- */
 287
 288 struct dma_client *dma_async_client_register(dma_event_callback event_callback);
 289 void dma_async_client_unregister(struct dma_client *client);
 290 void dma_async_client_chan_request(struct dma_client *client,
 291                 unsigned int number);
 292 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
 293         void *dest, void *src, size_t len);
 294 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
 295         struct page *page, unsigned int offset, void *kdata, size_t len);
 296 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 297         struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
 298         unsigned int src_off, size_t len);
 299 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
 300         struct dma_chan *chan);
 301
 302
 303 static inline void
 304 async_tx_ack(struct dma_async_tx_descriptor *tx)
 305 {
 306         tx->ack = 1;
 307 }
 308
 309 #define first_dma_cap(mask) __first_dma_cap(&(mask))
 310 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
 311 {
 312         return min_t(int, DMA_TX_TYPE_END,
 313                 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
 314 }
 315
 316 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
 317 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
 318 {
 319         return min_t(int, DMA_TX_TYPE_END,
 320                 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
 321 }
 322
 323 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
 324 static inline void
 325 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 326 {
 327         set_bit(tx_type, dstp->bits);
 328 }
 329
 330 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
 331 static inline int
 332 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
 333 {
 334         return test_bit(tx_type, srcp->bits);
 335 }
 336
 337 #define for_each_dma_cap_mask(cap, mask) \
 338         for ((cap) = first_dma_cap(mask);       \
 339                 (cap) < DMA_TX_TYPE_END;        \
 340                 (cap) = next_dma_cap((cap), (mask)))
 341
 342 /**
 343  * dma_async_issue_pending - flush pending transactions to HW
 344  * @chan: target DMA channel
 345  *
 346  * This allows drivers to push copies to HW in batches,
 347  * reducing MMIO writes where possible.
 348  */
 349 static inline void dma_async_issue_pending(struct dma_chan *chan)
 350 {
 351         return chan->device->device_issue_pending(chan);
 352 }
 353
 354 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
 355
 356 /**
 357  * dma_async_is_tx_complete - poll for transaction completion
 358  * @chan: DMA channel
 359  * @cookie: transaction identifier to check status of
 360  * @last: returns last completed cookie, can be NULL
 361  * @used: returns last issued cookie, can be NULL
 362  *
 363  * If @last and @used are passed in, upon return they reflect the driver
 364  * internal state and can be used with dma_async_is_complete() to check
 365  * the status of multiple cookies without re-checking hardware state.
 366  */
 367 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
 368         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
 369 {
 370         return chan->device->device_is_tx_complete(chan, cookie, last, used);
 371 }
 372
 373 #define dma_async_memcpy_complete(chan, cookie, last, used)\
 374         dma_async_is_tx_complete(chan, cookie, last, used)
 375
 376 /**
 377  * dma_async_is_complete - test a cookie against chan state
 378  * @cookie: transaction identifier to test status of
 379  * @last_complete: last know completed transaction
 380  * @last_used: last cookie value handed out
 381  *
 382  * dma_async_is_complete() is used in dma_async_memcpy_complete()
 383  * the test logic is seperated for lightweight testing of multiple cookies
 384  */
 385 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
 386                         dma_cookie_t last_complete, dma_cookie_t last_used)
 387 {
 388         if (last_complete <= last_used) {
 389                 if ((cookie <= last_complete) || (cookie > last_used))
 390                         return DMA_SUCCESS;
 391         } else {
 392                 if ((cookie <= last_complete) && (cookie > last_used))
 393                         return DMA_SUCCESS;
 394         }
 395         return DMA_IN_PROGRESS;
 396 }
 397
 398 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
 399
 400 /* --- DMA device --- */
 401
 402 int dma_async_device_register(struct dma_device *device);
 403 void dma_async_device_unregister(struct dma_device *device);
 404
 405 /* --- Helper iov-locking functions --- */
 406
 407 struct dma_page_list {
 408         char *base_address;
 409         int nr_pages;
 410         struct page **pages;
 411 };
 412
 413 struct dma_pinned_list {
 414         int nr_iovecs;
 415         struct dma_page_list page_list[0];
 416 };
 417
 418 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
 419 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
 420
 421 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
 422         struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
 423 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
 424         struct dma_pinned_list *pinned_list, struct page *page,
 425         unsigned int offset, size_t len);
 426
 427 #endif /* DMAENGINE_H */