2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
17 #ifndef LINUX_DMAENGINE_H
18 #define LINUX_DMAENGINE_H
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/uio.h>
23 #include <linux/bug.h>
24 #include <linux/scatterlist.h>
25 #include <linux/bitmap.h>
26 #include <linux/types.h>
30 * typedef dma_cookie_t - an opaque DMA cookie
32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 typedef s32 dma_cookie_t
;
35 #define DMA_MIN_COOKIE 1
37 static inline int dma_submit_error(dma_cookie_t cookie
)
39 return cookie
< 0 ? cookie
: 0;
43 * enum dma_status - DMA transaction status
44 * @DMA_COMPLETE: transaction completed
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type
{
76 /* last transaction type for creation of the capabilities mask */
81 * enum dma_transfer_direction - dma transfer mode and direction indicator
82 * @DMA_MEM_TO_MEM: Async/Memcpy mode
83 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
84 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
85 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 enum dma_transfer_direction
{
96 * Interleaved Transfer Request
97 * ----------------------------
98 * A chunk is collection of contiguous bytes to be transfered.
99 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100 * ICGs may or maynot change between chunks.
101 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102 * that when repeated an integral number of times, specifies the transfer.
103 * A transfer template is specification of a Frame, the number of times
104 * it is to be repeated and other per-transfer attributes.
106 * Practically, a client driver would have ready a template for each
107 * type of transfer it is going to need during its lifetime and
108 * set only 'src_start' and 'dst_start' before submitting the requests.
111 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
112 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
119 * struct data_chunk - Element of scatter-gather list that makes a frame.
120 * @size: Number of bytes to read from source.
121 * size_dst := fn(op, size_src), so doesn't mean much for destination.
122 * @icg: Number of bytes to jump after last src/dst address of this
123 * chunk and before first src/dst address for next chunk.
124 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
126 * @dst_icg: Number of bytes to jump after last dst address of this
127 * chunk and before the first dst address for next chunk.
128 * Ignored if dst_inc is true and dst_sgl is false.
129 * @src_icg: Number of bytes to jump after last src address of this
130 * chunk and before the first src address for next chunk.
131 * Ignored if src_inc is true and src_sgl is false.
141 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
143 * @src_start: Bus address of source for the first chunk.
144 * @dst_start: Bus address of destination for the first chunk.
145 * @dir: Specifies the type of Source and Destination.
146 * @src_inc: If the source address increments after reading from it.
147 * @dst_inc: If the destination address increments after writing to it.
148 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
149 * Otherwise, source is read contiguously (icg ignored).
150 * Ignored if src_inc is false.
151 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
152 * Otherwise, destination is filled contiguously (icg ignored).
153 * Ignored if dst_inc is false.
154 * @numf: Number of frames in this template.
155 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
156 * @sgl: Array of {chunk,icg} pairs that make up a frame.
158 struct dma_interleaved_template
{
159 dma_addr_t src_start
;
160 dma_addr_t dst_start
;
161 enum dma_transfer_direction dir
;
168 struct data_chunk sgl
[0];
172 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
173 * control completion, and communicate status.
174 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
176 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
177 * acknowledges receipt, i.e. has has a chance to establish any dependency
179 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
180 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
181 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
182 * sources that were the result of a previous operation, in the case of a PQ
183 * operation it continues the calculation with new sources
184 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
185 * on the result of this operation
187 enum dma_ctrl_flags
{
188 DMA_PREP_INTERRUPT
= (1 << 0),
189 DMA_CTRL_ACK
= (1 << 1),
190 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
191 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
192 DMA_PREP_CONTINUE
= (1 << 4),
193 DMA_PREP_FENCE
= (1 << 5),
197 * enum sum_check_bits - bit position of pq_check_flags
199 enum sum_check_bits
{
205 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
206 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
207 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
209 enum sum_check_flags
{
210 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
211 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
216 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
217 * See linux/cpumask.h
219 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
222 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
223 * @memcpy_count: transaction counter
224 * @bytes_transferred: byte counter
227 struct dma_chan_percpu
{
229 unsigned long memcpy_count
;
230 unsigned long bytes_transferred
;
234 * struct dma_router - DMA router structure
235 * @dev: pointer to the DMA router device
236 * @route_free: function to be called when the route can be disconnected
240 void (*route_free
)(struct device
*dev
, void *route_data
);
244 * struct dma_chan - devices supply DMA channels, clients use them
245 * @device: ptr to the dma device who supplies this channel, always !%NULL
246 * @cookie: last cookie value returned to client
247 * @completed_cookie: last completed cookie for this channel
248 * @chan_id: channel ID for sysfs
249 * @dev: class device for sysfs
250 * @device_node: used to add this to the device chan list
251 * @local: per-cpu pointer to a struct dma_chan_percpu
252 * @client_count: how many clients are using this channel
253 * @table_count: number of appearances in the mem-to-mem allocation table
254 * @router: pointer to the DMA router structure
255 * @route_data: channel specific data for the router
256 * @private: private data for certain client-channel associations
259 struct dma_device
*device
;
261 dma_cookie_t completed_cookie
;
265 struct dma_chan_dev
*dev
;
267 struct list_head device_node
;
268 struct dma_chan_percpu __percpu
*local
;
273 struct dma_router
*router
;
280 * struct dma_chan_dev - relate sysfs device node to backing channel device
281 * @chan: driver channel device
282 * @device: sysfs device
283 * @dev_id: parent dma_device dev_id
284 * @idr_ref: reference count to gate release of dma_device dev_id
286 struct dma_chan_dev
{
287 struct dma_chan
*chan
;
288 struct device device
;
294 * enum dma_slave_buswidth - defines bus width of the DMA slave
295 * device, source or target buses
297 enum dma_slave_buswidth
{
298 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
299 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
300 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
301 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
302 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
303 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
304 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
305 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
306 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
310 * struct dma_slave_config - dma slave channel runtime config
311 * @direction: whether the data shall go in or out on this slave
312 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
313 * legal values. DEPRECATED, drivers should use the direction argument
314 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
315 * the dir field in the dma_interleaved_template structure.
316 * @src_addr: this is the physical address where DMA slave data
317 * should be read (RX), if the source is memory this argument is
319 * @dst_addr: this is the physical address where DMA slave data
320 * should be written (TX), if the source is memory this argument
322 * @src_addr_width: this is the width in bytes of the source (RX)
323 * register where DMA data shall be read. If the source
324 * is memory this may be ignored depending on architecture.
325 * Legal values: 1, 2, 4, 8.
326 * @dst_addr_width: same as src_addr_width but for destination
327 * target (TX) mutatis mutandis.
328 * @src_maxburst: the maximum number of words (note: words, as in
329 * units of the src_addr_width member, not bytes) that can be sent
330 * in one burst to the device. Typically something like half the
331 * FIFO depth on I/O peripherals so you don't overflow it. This
332 * may or may not be applicable on memory sources.
333 * @dst_maxburst: same as src_maxburst but for destination target
335 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
336 * with 'true' if peripheral should be flow controller. Direction will be
337 * selected at Runtime.
338 * @slave_id: Slave requester id. Only valid for slave channels. The dma
339 * slave peripheral will have unique id as dma requester which need to be
340 * pass as slave config.
342 * This struct is passed in as configuration data to a DMA engine
343 * in order to set up a certain channel for DMA transport at runtime.
344 * The DMA device/engine has to provide support for an additional
345 * callback in the dma_device structure, device_config and this struct
346 * will then be passed in as an argument to the function.
348 * The rationale for adding configuration information to this struct is as
349 * follows: if it is likely that more than one DMA slave controllers in
350 * the world will support the configuration option, then make it generic.
351 * If not: if it is fixed so that it be sent in static from the platform
352 * data, then prefer to do that.
354 struct dma_slave_config
{
355 enum dma_transfer_direction direction
;
358 enum dma_slave_buswidth src_addr_width
;
359 enum dma_slave_buswidth dst_addr_width
;
363 unsigned int slave_id
;
367 * enum dma_residue_granularity - Granularity of the reported transfer residue
368 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
369 * DMA channel is only able to tell whether a descriptor has been completed or
370 * not, which means residue reporting is not supported by this channel. The
371 * residue field of the dma_tx_state field will always be 0.
372 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
373 * completed segment of the transfer (For cyclic transfers this is after each
374 * period). This is typically implemented by having the hardware generate an
375 * interrupt after each transferred segment and then the drivers updates the
376 * outstanding residue by the size of the segment. Another possibility is if
377 * the hardware supports scatter-gather and the segment descriptor has a field
378 * which gets set after the segment has been completed. The driver then counts
379 * the number of segments without the flag set to compute the residue.
380 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
381 * burst. This is typically only supported if the hardware has a progress
382 * register of some sort (E.g. a register with the current read/write address
383 * or a register with the amount of bursts/beats/bytes that have been
384 * transferred or still need to be transferred).
386 enum dma_residue_granularity
{
387 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
388 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
389 DMA_RESIDUE_GRANULARITY_BURST
= 2,
392 /* struct dma_slave_caps - expose capabilities of a slave channel only
394 * @src_addr_widths: bit mask of src addr widths the channel supports
395 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
396 * @directions: bit mask of slave direction the channel supported
397 * since the enum dma_transfer_direction is not defined as bits for each
398 * type of direction, the dma controller should fill (1 << <TYPE>) and same
399 * should be checked by controller as well
400 * @cmd_pause: true, if pause and thereby resume is supported
401 * @cmd_terminate: true, if terminate cmd is supported
402 * @residue_granularity: granularity of the reported transfer residue
404 struct dma_slave_caps
{
410 enum dma_residue_granularity residue_granularity
;
413 static inline const char *dma_chan_name(struct dma_chan
*chan
)
415 return dev_name(&chan
->dev
->device
);
418 void dma_chan_cleanup(struct kref
*kref
);
421 * typedef dma_filter_fn - callback filter for dma_request_channel
422 * @chan: channel to be reviewed
423 * @filter_param: opaque parameter passed through dma_request_channel
425 * When this optional parameter is specified in a call to dma_request_channel a
426 * suitable channel is passed to this routine for further dispositioning before
427 * being returned. Where 'suitable' indicates a non-busy channel that
428 * satisfies the given capability mask. It returns 'true' to indicate that the
429 * channel is suitable.
431 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
433 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
435 struct dmaengine_unmap_data
{
447 * struct dma_async_tx_descriptor - async transaction descriptor
448 * ---dma generic offload fields---
449 * @cookie: tracking cookie for this transaction, set to -EBUSY if
450 * this tx is sitting on a dependency list
451 * @flags: flags to augment operation preparation, control completion, and
453 * @phys: physical address of the descriptor
454 * @chan: target channel for this operation
455 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
456 * descriptor pending. To be pushed on .issue_pending() call
457 * @callback: routine to call after this operation is complete
458 * @callback_param: general parameter to pass to the callback routine
459 * ---async_tx api specific fields---
460 * @next: at completion submit this descriptor
461 * @parent: pointer to the next level up in the dependency chain
462 * @lock: protect the parent and next pointers
464 struct dma_async_tx_descriptor
{
466 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
468 struct dma_chan
*chan
;
469 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
470 dma_async_tx_callback callback
;
471 void *callback_param
;
472 struct dmaengine_unmap_data
*unmap
;
473 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
474 struct dma_async_tx_descriptor
*next
;
475 struct dma_async_tx_descriptor
*parent
;
480 #ifdef CONFIG_DMA_ENGINE
481 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
482 struct dmaengine_unmap_data
*unmap
)
484 kref_get(&unmap
->kref
);
488 struct dmaengine_unmap_data
*
489 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
490 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
492 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
493 struct dmaengine_unmap_data
*unmap
)
496 static inline struct dmaengine_unmap_data
*
497 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
501 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
506 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
509 dmaengine_unmap_put(tx
->unmap
);
514 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
515 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
518 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
521 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
525 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
528 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
531 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
535 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
541 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
543 spin_lock_bh(&txd
->lock
);
545 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
547 spin_unlock_bh(&txd
->lock
);
549 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
554 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
558 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
562 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
566 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
573 * struct dma_tx_state - filled in to report the status of
575 * @last: last completed DMA cookie
576 * @used: last issued DMA cookie (i.e. the one in progress)
577 * @residue: the remaining number of bytes left to transmit
578 * on the selected transfer for states DMA_IN_PROGRESS and
579 * DMA_PAUSED if this is implemented in the driver, else 0
581 struct dma_tx_state
{
588 * struct dma_device - info on the entity supplying DMA services
589 * @chancnt: how many DMA channels are supported
590 * @privatecnt: how many DMA channels are requested by dma_request_channel
591 * @channels: the list of struct dma_chan
592 * @global_node: list_head for global dma_device_list
593 * @cap_mask: one or more dma_capability flags
594 * @max_xor: maximum number of xor sources, 0 if no capability
595 * @max_pq: maximum number of PQ sources and PQ-continue capability
596 * @copy_align: alignment shift for memcpy operations
597 * @xor_align: alignment shift for xor operations
598 * @pq_align: alignment shift for pq operations
599 * @fill_align: alignment shift for memset operations
600 * @dev_id: unique device ID
601 * @dev: struct device reference for dma mapping api
602 * @src_addr_widths: bit mask of src addr widths the device supports
603 * @dst_addr_widths: bit mask of dst addr widths the device supports
604 * @directions: bit mask of slave direction the device supports since
605 * the enum dma_transfer_direction is not defined as bits for
606 * each type of direction, the dma controller should fill (1 <<
607 * <TYPE>) and same should be checked by controller as well
608 * @residue_granularity: granularity of the transfer residue reported
610 * @device_alloc_chan_resources: allocate resources and return the
611 * number of allocated descriptors
612 * @device_free_chan_resources: release DMA channel's resources
613 * @device_prep_dma_memcpy: prepares a memcpy operation
614 * @device_prep_dma_xor: prepares a xor operation
615 * @device_prep_dma_xor_val: prepares a xor validation operation
616 * @device_prep_dma_pq: prepares a pq operation
617 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
618 * @device_prep_dma_memset: prepares a memset operation
619 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
620 * @device_prep_slave_sg: prepares a slave dma operation
621 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
622 * The function takes a buffer of size buf_len. The callback function will
623 * be called after period_len bytes have been transferred.
624 * @device_prep_interleaved_dma: Transfer expression in a generic way.
625 * @device_config: Pushes a new configuration to a channel, return 0 or an error
627 * @device_pause: Pauses any transfer happening on a channel. Returns
629 * @device_resume: Resumes any transfer on a channel previously
630 * paused. Returns 0 or an error code
631 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
633 * @device_tx_status: poll for transaction completion, the optional
634 * txstate parameter can be supplied with a pointer to get a
635 * struct with auxiliary transfer status information, otherwise the call
636 * will just return a simple status code
637 * @device_issue_pending: push pending transactions to hardware
641 unsigned int chancnt
;
642 unsigned int privatecnt
;
643 struct list_head channels
;
644 struct list_head global_node
;
645 dma_cap_mask_t cap_mask
;
646 unsigned short max_xor
;
647 unsigned short max_pq
;
652 #define DMA_HAS_PQ_CONTINUE (1 << 15)
660 enum dma_residue_granularity residue_granularity
;
662 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
663 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
665 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
666 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
667 size_t len
, unsigned long flags
);
668 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
669 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
670 unsigned int src_cnt
, size_t len
, unsigned long flags
);
671 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
672 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
673 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
674 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
675 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
676 unsigned int src_cnt
, const unsigned char *scf
,
677 size_t len
, unsigned long flags
);
678 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
679 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
680 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
681 enum sum_check_flags
*pqres
, unsigned long flags
);
682 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
683 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
684 unsigned long flags
);
685 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
686 struct dma_chan
*chan
, unsigned long flags
);
687 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
688 struct dma_chan
*chan
,
689 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
690 struct scatterlist
*src_sg
, unsigned int src_nents
,
691 unsigned long flags
);
693 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
694 struct dma_chan
*chan
, struct scatterlist
*sgl
,
695 unsigned int sg_len
, enum dma_transfer_direction direction
,
696 unsigned long flags
, void *context
);
697 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
698 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
699 size_t period_len
, enum dma_transfer_direction direction
,
700 unsigned long flags
);
701 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
702 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
703 unsigned long flags
);
705 int (*device_config
)(struct dma_chan
*chan
,
706 struct dma_slave_config
*config
);
707 int (*device_pause
)(struct dma_chan
*chan
);
708 int (*device_resume
)(struct dma_chan
*chan
);
709 int (*device_terminate_all
)(struct dma_chan
*chan
);
711 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
713 struct dma_tx_state
*txstate
);
714 void (*device_issue_pending
)(struct dma_chan
*chan
);
717 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
718 struct dma_slave_config
*config
)
720 if (chan
->device
->device_config
)
721 return chan
->device
->device_config(chan
, config
);
726 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
728 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
731 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
732 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
733 enum dma_transfer_direction dir
, unsigned long flags
)
735 struct scatterlist sg
;
736 sg_init_table(&sg
, 1);
737 sg_dma_address(&sg
) = buf
;
738 sg_dma_len(&sg
) = len
;
740 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
744 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
745 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
746 enum dma_transfer_direction dir
, unsigned long flags
)
748 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
752 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
754 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
755 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
756 enum dma_transfer_direction dir
, unsigned long flags
,
757 struct rio_dma_ext
*rio_ext
)
759 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
760 dir
, flags
, rio_ext
);
764 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
765 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
766 size_t period_len
, enum dma_transfer_direction dir
,
769 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
770 period_len
, dir
, flags
);
773 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
774 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
777 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
780 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memset(
781 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
784 if (!chan
|| !chan
->device
)
787 return chan
->device
->device_prep_dma_memset(chan
, dest
, value
,
791 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_sg(
792 struct dma_chan
*chan
,
793 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
794 struct scatterlist
*src_sg
, unsigned int src_nents
,
797 return chan
->device
->device_prep_dma_sg(chan
, dst_sg
, dst_nents
,
798 src_sg
, src_nents
, flags
);
801 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
803 if (chan
->device
->device_terminate_all
)
804 return chan
->device
->device_terminate_all(chan
);
809 static inline int dmaengine_pause(struct dma_chan
*chan
)
811 if (chan
->device
->device_pause
)
812 return chan
->device
->device_pause(chan
);
817 static inline int dmaengine_resume(struct dma_chan
*chan
)
819 if (chan
->device
->device_resume
)
820 return chan
->device
->device_resume(chan
);
825 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
826 dma_cookie_t cookie
, struct dma_tx_state
*state
)
828 return chan
->device
->device_tx_status(chan
, cookie
, state
);
831 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
833 return desc
->tx_submit(desc
);
836 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
842 mask
= (1 << align
) - 1;
843 if (mask
& (off1
| off2
| len
))
848 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
849 size_t off2
, size_t len
)
851 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
854 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
855 size_t off2
, size_t len
)
857 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
860 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
861 size_t off2
, size_t len
)
863 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
866 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
867 size_t off2
, size_t len
)
869 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
873 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
877 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
880 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
882 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
885 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
887 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
889 return (flags
& mask
) == mask
;
892 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
894 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
897 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
899 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
902 /* dma_maxpq - reduce maxpq in the face of continued operations
903 * @dma - dma device with PQ capability
904 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
906 * When an engine does not support native continuation we need 3 extra
907 * source slots to reuse P and Q with the following coefficients:
908 * 1/ {00} * P : remove P from Q', but use it as a source for P'
909 * 2/ {01} * Q : use Q to continue Q' calculation
910 * 3/ {00} * Q : subtract Q from P' to cancel (2)
912 * In the case where P is disabled we only need 1 extra source:
913 * 1/ {01} * Q : use Q to continue Q' calculation
915 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
917 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
918 return dma_dev_to_maxpq(dma
);
919 else if (dmaf_p_disabled_continue(flags
))
920 return dma_dev_to_maxpq(dma
) - 1;
921 else if (dmaf_continue(flags
))
922 return dma_dev_to_maxpq(dma
) - 3;
926 static inline size_t dmaengine_get_icg(bool inc
, bool sgl
, size_t icg
,
939 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template
*xt
,
940 struct data_chunk
*chunk
)
942 return dmaengine_get_icg(xt
->dst_inc
, xt
->dst_sgl
,
943 chunk
->icg
, chunk
->dst_icg
);
946 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template
*xt
,
947 struct data_chunk
*chunk
)
949 return dmaengine_get_icg(xt
->src_inc
, xt
->src_sgl
,
950 chunk
->icg
, chunk
->src_icg
);
953 /* --- public DMA engine API --- */
955 #ifdef CONFIG_DMA_ENGINE
956 void dmaengine_get(void);
957 void dmaengine_put(void);
959 static inline void dmaengine_get(void)
962 static inline void dmaengine_put(void)
967 #ifdef CONFIG_ASYNC_TX_DMA
968 #define async_dmaengine_get() dmaengine_get()
969 #define async_dmaengine_put() dmaengine_put()
970 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
971 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
973 #define async_dma_find_channel(type) dma_find_channel(type)
974 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
976 static inline void async_dmaengine_get(void)
979 static inline void async_dmaengine_put(void)
982 static inline struct dma_chan
*
983 async_dma_find_channel(enum dma_transaction_type type
)
987 #endif /* CONFIG_ASYNC_TX_DMA */
988 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
989 struct dma_chan
*chan
);
991 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
993 tx
->flags
|= DMA_CTRL_ACK
;
996 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
998 tx
->flags
&= ~DMA_CTRL_ACK
;
1001 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
1003 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
1006 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1008 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1010 set_bit(tx_type
, dstp
->bits
);
1013 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1015 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1017 clear_bit(tx_type
, dstp
->bits
);
1020 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1021 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
1023 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
1026 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1028 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
1030 return test_bit(tx_type
, srcp
->bits
);
1033 #define for_each_dma_cap_mask(cap, mask) \
1034 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1037 * dma_async_issue_pending - flush pending transactions to HW
1038 * @chan: target DMA channel
1040 * This allows drivers to push copies to HW in batches,
1041 * reducing MMIO writes where possible.
1043 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1045 chan
->device
->device_issue_pending(chan
);
1049 * dma_async_is_tx_complete - poll for transaction completion
1050 * @chan: DMA channel
1051 * @cookie: transaction identifier to check status of
1052 * @last: returns last completed cookie, can be NULL
1053 * @used: returns last issued cookie, can be NULL
1055 * If @last and @used are passed in, upon return they reflect the driver
1056 * internal state and can be used with dma_async_is_complete() to check
1057 * the status of multiple cookies without re-checking hardware state.
1059 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1060 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1062 struct dma_tx_state state
;
1063 enum dma_status status
;
1065 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1074 * dma_async_is_complete - test a cookie against chan state
1075 * @cookie: transaction identifier to test status of
1076 * @last_complete: last know completed transaction
1077 * @last_used: last cookie value handed out
1079 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1080 * the test logic is separated for lightweight testing of multiple cookies
1082 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1083 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1085 if (last_complete
<= last_used
) {
1086 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1087 return DMA_COMPLETE
;
1089 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1090 return DMA_COMPLETE
;
1092 return DMA_IN_PROGRESS
;
1096 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1101 st
->residue
= residue
;
1105 #ifdef CONFIG_DMA_ENGINE
1106 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1107 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1108 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1109 void dma_issue_pending_all(void);
1110 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1111 dma_filter_fn fn
, void *fn_param
);
1112 struct dma_chan
*dma_request_slave_channel_reason(struct device
*dev
,
1114 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1115 void dma_release_channel(struct dma_chan
*chan
);
1116 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1118 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1122 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1124 return DMA_COMPLETE
;
1126 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1128 return DMA_COMPLETE
;
1130 static inline void dma_issue_pending_all(void)
1133 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1134 dma_filter_fn fn
, void *fn_param
)
1138 static inline struct dma_chan
*dma_request_slave_channel_reason(
1139 struct device
*dev
, const char *name
)
1141 return ERR_PTR(-ENODEV
);
1143 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1148 static inline void dma_release_channel(struct dma_chan
*chan
)
1151 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1152 struct dma_slave_caps
*caps
)
1158 /* --- DMA device --- */
1160 int dma_async_device_register(struct dma_device
*device
);
1161 void dma_async_device_unregister(struct dma_device
*device
);
1162 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1163 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1164 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1165 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1166 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1167 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1169 static inline struct dma_chan
1170 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1171 dma_filter_fn fn
, void *fn_param
,
1172 struct device
*dev
, char *name
)
1174 struct dma_chan
*chan
;
1176 chan
= dma_request_slave_channel(dev
, name
);
1180 return __dma_request_channel(mask
, fn
, fn_param
);
1182 #endif /* DMAENGINE_H */