2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef LINUX_DMAENGINE_H
22 #define LINUX_DMAENGINE_H
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/uio.h>
27 #include <linux/bug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/bitmap.h>
30 #include <linux/types.h>
34 * typedef dma_cookie_t - an opaque DMA cookie
36 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
38 typedef s32 dma_cookie_t
;
39 #define DMA_MIN_COOKIE 1
40 #define DMA_MAX_COOKIE INT_MAX
42 static inline int dma_submit_error(dma_cookie_t cookie
)
44 return cookie
< 0 ? cookie
: 0;
48 * enum dma_status - DMA transaction status
49 * @DMA_COMPLETE: transaction completed
50 * @DMA_IN_PROGRESS: transaction not yet processed
51 * @DMA_PAUSED: transaction is paused
52 * @DMA_ERROR: transaction failed
62 * enum dma_transaction_type - DMA transaction types/indexes
64 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
65 * automatically set as dma devices are registered.
67 enum dma_transaction_type
{
80 /* last transaction type for creation of the capabilities mask */
85 * enum dma_transfer_direction - dma transfer mode and direction indicator
86 * @DMA_MEM_TO_MEM: Async/Memcpy mode
87 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
88 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
89 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
91 enum dma_transfer_direction
{
100 * Interleaved Transfer Request
101 * ----------------------------
102 * A chunk is collection of contiguous bytes to be transfered.
103 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
104 * ICGs may or maynot change between chunks.
105 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
106 * that when repeated an integral number of times, specifies the transfer.
107 * A transfer template is specification of a Frame, the number of times
108 * it is to be repeated and other per-transfer attributes.
110 * Practically, a client driver would have ready a template for each
111 * type of transfer it is going to need during its lifetime and
112 * set only 'src_start' and 'dst_start' before submitting the requests.
115 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
116 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
123 * struct data_chunk - Element of scatter-gather list that makes a frame.
124 * @size: Number of bytes to read from source.
125 * size_dst := fn(op, size_src), so doesn't mean much for destination.
126 * @icg: Number of bytes to jump after last src/dst address of this
127 * chunk and before first src/dst address for next chunk.
128 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
129 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
137 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
139 * @src_start: Bus address of source for the first chunk.
140 * @dst_start: Bus address of destination for the first chunk.
141 * @dir: Specifies the type of Source and Destination.
142 * @src_inc: If the source address increments after reading from it.
143 * @dst_inc: If the destination address increments after writing to it.
144 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
145 * Otherwise, source is read contiguously (icg ignored).
146 * Ignored if src_inc is false.
147 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
148 * Otherwise, destination is filled contiguously (icg ignored).
149 * Ignored if dst_inc is false.
150 * @numf: Number of frames in this template.
151 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
152 * @sgl: Array of {chunk,icg} pairs that make up a frame.
154 struct dma_interleaved_template
{
155 dma_addr_t src_start
;
156 dma_addr_t dst_start
;
157 enum dma_transfer_direction dir
;
164 struct data_chunk sgl
[0];
168 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
169 * control completion, and communicate status.
170 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
172 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
173 * acknowledges receipt, i.e. has has a chance to establish any dependency
175 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
176 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
177 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
178 * sources that were the result of a previous operation, in the case of a PQ
179 * operation it continues the calculation with new sources
180 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
181 * on the result of this operation
183 enum dma_ctrl_flags
{
184 DMA_PREP_INTERRUPT
= (1 << 0),
185 DMA_CTRL_ACK
= (1 << 1),
186 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
187 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
188 DMA_PREP_CONTINUE
= (1 << 4),
189 DMA_PREP_FENCE
= (1 << 5),
193 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
194 * on a running channel.
195 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
196 * @DMA_PAUSE: pause ongoing transfers
197 * @DMA_RESUME: resume paused transfer
198 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
199 * that need to runtime reconfigure the slave channels (as opposed to passing
200 * configuration data in statically from the platform). An additional
201 * argument of struct dma_slave_config must be passed in with this
203 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
204 * into external start mode.
211 FSLDMA_EXTERNAL_START
,
215 * enum sum_check_bits - bit position of pq_check_flags
217 enum sum_check_bits
{
223 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
224 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
225 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
227 enum sum_check_flags
{
228 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
229 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
234 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
235 * See linux/cpumask.h
237 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
240 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
241 * @memcpy_count: transaction counter
242 * @bytes_transferred: byte counter
245 struct dma_chan_percpu
{
247 unsigned long memcpy_count
;
248 unsigned long bytes_transferred
;
252 * struct dma_chan - devices supply DMA channels, clients use them
253 * @device: ptr to the dma device who supplies this channel, always !%NULL
254 * @cookie: last cookie value returned to client
255 * @completed_cookie: last completed cookie for this channel
256 * @chan_id: channel ID for sysfs
257 * @dev: class device for sysfs
258 * @device_node: used to add this to the device chan list
259 * @local: per-cpu pointer to a struct dma_chan_percpu
260 * @client_count: how many clients are using this channel
261 * @table_count: number of appearances in the mem-to-mem allocation table
262 * @private: private data for certain client-channel associations
265 struct dma_device
*device
;
267 dma_cookie_t completed_cookie
;
271 struct dma_chan_dev
*dev
;
273 struct list_head device_node
;
274 struct dma_chan_percpu __percpu
*local
;
281 * struct dma_chan_dev - relate sysfs device node to backing channel device
282 * @chan: driver channel device
283 * @device: sysfs device
284 * @dev_id: parent dma_device dev_id
285 * @idr_ref: reference count to gate release of dma_device dev_id
287 struct dma_chan_dev
{
288 struct dma_chan
*chan
;
289 struct device device
;
295 * enum dma_slave_buswidth - defines bus width of the DMA slave
296 * device, source or target buses
298 enum dma_slave_buswidth
{
299 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
300 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
301 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
302 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
303 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
304 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
308 * struct dma_slave_config - dma slave channel runtime config
309 * @direction: whether the data shall go in or out on this slave
310 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
312 * @src_addr: this is the physical address where DMA slave data
313 * should be read (RX), if the source is memory this argument is
315 * @dst_addr: this is the physical address where DMA slave data
316 * should be written (TX), if the source is memory this argument
318 * @src_addr_width: this is the width in bytes of the source (RX)
319 * register where DMA data shall be read. If the source
320 * is memory this may be ignored depending on architecture.
321 * Legal values: 1, 2, 4, 8.
322 * @dst_addr_width: same as src_addr_width but for destination
323 * target (TX) mutatis mutandis.
324 * @src_maxburst: the maximum number of words (note: words, as in
325 * units of the src_addr_width member, not bytes) that can be sent
326 * in one burst to the device. Typically something like half the
327 * FIFO depth on I/O peripherals so you don't overflow it. This
328 * may or may not be applicable on memory sources.
329 * @dst_maxburst: same as src_maxburst but for destination target
331 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
332 * with 'true' if peripheral should be flow controller. Direction will be
333 * selected at Runtime.
334 * @slave_id: Slave requester id. Only valid for slave channels. The dma
335 * slave peripheral will have unique id as dma requester which need to be
336 * pass as slave config.
338 * This struct is passed in as configuration data to a DMA engine
339 * in order to set up a certain channel for DMA transport at runtime.
340 * The DMA device/engine has to provide support for an additional
341 * command in the channel config interface, DMA_SLAVE_CONFIG
342 * and this struct will then be passed in as an argument to the
343 * DMA engine device_control() function.
345 * The rationale for adding configuration information to this struct is as
346 * follows: if it is likely that more than one DMA slave controllers in
347 * the world will support the configuration option, then make it generic.
348 * If not: if it is fixed so that it be sent in static from the platform
349 * data, then prefer to do that.
351 struct dma_slave_config
{
352 enum dma_transfer_direction direction
;
355 enum dma_slave_buswidth src_addr_width
;
356 enum dma_slave_buswidth dst_addr_width
;
360 unsigned int slave_id
;
364 * enum dma_residue_granularity - Granularity of the reported transfer residue
365 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
366 * DMA channel is only able to tell whether a descriptor has been completed or
367 * not, which means residue reporting is not supported by this channel. The
368 * residue field of the dma_tx_state field will always be 0.
369 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
370 * completed segment of the transfer (For cyclic transfers this is after each
371 * period). This is typically implemented by having the hardware generate an
372 * interrupt after each transferred segment and then the drivers updates the
373 * outstanding residue by the size of the segment. Another possibility is if
374 * the hardware supports scatter-gather and the segment descriptor has a field
375 * which gets set after the segment has been completed. The driver then counts
376 * the number of segments without the flag set to compute the residue.
377 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
378 * burst. This is typically only supported if the hardware has a progress
379 * register of some sort (E.g. a register with the current read/write address
380 * or a register with the amount of bursts/beats/bytes that have been
381 * transferred or still need to be transferred).
383 enum dma_residue_granularity
{
384 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
385 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
386 DMA_RESIDUE_GRANULARITY_BURST
= 2,
389 /* struct dma_slave_caps - expose capabilities of a slave channel only
391 * @src_addr_widths: bit mask of src addr widths the channel supports
392 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
393 * @directions: bit mask of slave direction the channel supported
394 * since the enum dma_transfer_direction is not defined as bits for each
395 * type of direction, the dma controller should fill (1 << <TYPE>) and same
396 * should be checked by controller as well
397 * @cmd_pause: true, if pause and thereby resume is supported
398 * @cmd_terminate: true, if terminate cmd is supported
399 * @residue_granularity: granularity of the reported transfer residue
401 struct dma_slave_caps
{
403 u32 dstn_addr_widths
;
407 enum dma_residue_granularity residue_granularity
;
410 static inline const char *dma_chan_name(struct dma_chan
*chan
)
412 return dev_name(&chan
->dev
->device
);
415 void dma_chan_cleanup(struct kref
*kref
);
418 * typedef dma_filter_fn - callback filter for dma_request_channel
419 * @chan: channel to be reviewed
420 * @filter_param: opaque parameter passed through dma_request_channel
422 * When this optional parameter is specified in a call to dma_request_channel a
423 * suitable channel is passed to this routine for further dispositioning before
424 * being returned. Where 'suitable' indicates a non-busy channel that
425 * satisfies the given capability mask. It returns 'true' to indicate that the
426 * channel is suitable.
428 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
430 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
432 struct dmaengine_unmap_data
{
444 * struct dma_async_tx_descriptor - async transaction descriptor
445 * ---dma generic offload fields---
446 * @cookie: tracking cookie for this transaction, set to -EBUSY if
447 * this tx is sitting on a dependency list
448 * @flags: flags to augment operation preparation, control completion, and
450 * @phys: physical address of the descriptor
451 * @chan: target channel for this operation
452 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
453 * @callback: routine to call after this operation is complete
454 * @callback_param: general parameter to pass to the callback routine
455 * ---async_tx api specific fields---
456 * @next: at completion submit this descriptor
457 * @parent: pointer to the next level up in the dependency chain
458 * @lock: protect the parent and next pointers
460 struct dma_async_tx_descriptor
{
462 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
464 struct dma_chan
*chan
;
465 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
466 dma_async_tx_callback callback
;
467 void *callback_param
;
468 struct dmaengine_unmap_data
*unmap
;
469 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
470 struct dma_async_tx_descriptor
*next
;
471 struct dma_async_tx_descriptor
*parent
;
476 #ifdef CONFIG_DMA_ENGINE
477 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
478 struct dmaengine_unmap_data
*unmap
)
480 kref_get(&unmap
->kref
);
484 struct dmaengine_unmap_data
*
485 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
486 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
488 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
489 struct dmaengine_unmap_data
*unmap
)
492 static inline struct dmaengine_unmap_data
*
493 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
497 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
502 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
505 dmaengine_unmap_put(tx
->unmap
);
510 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
511 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
514 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
517 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
521 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
524 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
527 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
531 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
537 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
539 spin_lock_bh(&txd
->lock
);
541 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
543 spin_unlock_bh(&txd
->lock
);
545 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
550 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
554 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
558 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
562 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
569 * struct dma_tx_state - filled in to report the status of
571 * @last: last completed DMA cookie
572 * @used: last issued DMA cookie (i.e. the one in progress)
573 * @residue: the remaining number of bytes left to transmit
574 * on the selected transfer for states DMA_IN_PROGRESS and
575 * DMA_PAUSED if this is implemented in the driver, else 0
577 struct dma_tx_state
{
584 * struct dma_device - info on the entity supplying DMA services
585 * @chancnt: how many DMA channels are supported
586 * @privatecnt: how many DMA channels are requested by dma_request_channel
587 * @channels: the list of struct dma_chan
588 * @global_node: list_head for global dma_device_list
589 * @cap_mask: one or more dma_capability flags
590 * @max_xor: maximum number of xor sources, 0 if no capability
591 * @max_pq: maximum number of PQ sources and PQ-continue capability
592 * @copy_align: alignment shift for memcpy operations
593 * @xor_align: alignment shift for xor operations
594 * @pq_align: alignment shift for pq operations
595 * @fill_align: alignment shift for memset operations
596 * @dev_id: unique device ID
597 * @dev: struct device reference for dma mapping api
598 * @device_alloc_chan_resources: allocate resources and return the
599 * number of allocated descriptors
600 * @device_free_chan_resources: release DMA channel's resources
601 * @device_prep_dma_memcpy: prepares a memcpy operation
602 * @device_prep_dma_xor: prepares a xor operation
603 * @device_prep_dma_xor_val: prepares a xor validation operation
604 * @device_prep_dma_pq: prepares a pq operation
605 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
606 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
607 * @device_prep_slave_sg: prepares a slave dma operation
608 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
609 * The function takes a buffer of size buf_len. The callback function will
610 * be called after period_len bytes have been transferred.
611 * @device_prep_interleaved_dma: Transfer expression in a generic way.
612 * @device_control: manipulate all pending operations on a channel, returns
614 * @device_tx_status: poll for transaction completion, the optional
615 * txstate parameter can be supplied with a pointer to get a
616 * struct with auxiliary transfer status information, otherwise the call
617 * will just return a simple status code
618 * @device_issue_pending: push pending transactions to hardware
619 * @device_slave_caps: return the slave channel capabilities
623 unsigned int chancnt
;
624 unsigned int privatecnt
;
625 struct list_head channels
;
626 struct list_head global_node
;
627 dma_cap_mask_t cap_mask
;
628 unsigned short max_xor
;
629 unsigned short max_pq
;
634 #define DMA_HAS_PQ_CONTINUE (1 << 15)
639 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
640 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
642 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
643 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
644 size_t len
, unsigned long flags
);
645 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
646 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
647 unsigned int src_cnt
, size_t len
, unsigned long flags
);
648 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
649 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
650 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
651 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
652 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
653 unsigned int src_cnt
, const unsigned char *scf
,
654 size_t len
, unsigned long flags
);
655 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
656 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
657 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
658 enum sum_check_flags
*pqres
, unsigned long flags
);
659 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
660 struct dma_chan
*chan
, unsigned long flags
);
661 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
662 struct dma_chan
*chan
,
663 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
664 struct scatterlist
*src_sg
, unsigned int src_nents
,
665 unsigned long flags
);
667 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
668 struct dma_chan
*chan
, struct scatterlist
*sgl
,
669 unsigned int sg_len
, enum dma_transfer_direction direction
,
670 unsigned long flags
, void *context
);
671 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
672 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
673 size_t period_len
, enum dma_transfer_direction direction
,
674 unsigned long flags
, void *context
);
675 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
676 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
677 unsigned long flags
);
678 int (*device_control
)(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
681 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
683 struct dma_tx_state
*txstate
);
684 void (*device_issue_pending
)(struct dma_chan
*chan
);
685 int (*device_slave_caps
)(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
688 static inline int dmaengine_device_control(struct dma_chan
*chan
,
689 enum dma_ctrl_cmd cmd
,
692 if (chan
->device
->device_control
)
693 return chan
->device
->device_control(chan
, cmd
, arg
);
698 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
699 struct dma_slave_config
*config
)
701 return dmaengine_device_control(chan
, DMA_SLAVE_CONFIG
,
702 (unsigned long)config
);
705 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
707 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
710 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
711 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
712 enum dma_transfer_direction dir
, unsigned long flags
)
714 struct scatterlist sg
;
715 sg_init_table(&sg
, 1);
716 sg_dma_address(&sg
) = buf
;
717 sg_dma_len(&sg
) = len
;
719 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
723 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
724 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
725 enum dma_transfer_direction dir
, unsigned long flags
)
727 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
731 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
733 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
734 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
735 enum dma_transfer_direction dir
, unsigned long flags
,
736 struct rio_dma_ext
*rio_ext
)
738 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
739 dir
, flags
, rio_ext
);
743 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
744 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
745 size_t period_len
, enum dma_transfer_direction dir
,
748 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
749 period_len
, dir
, flags
, NULL
);
752 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
753 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
756 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
759 static inline int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
)
764 /* check if the channel supports slave transactions */
765 if (!test_bit(DMA_SLAVE
, chan
->device
->cap_mask
.bits
))
768 if (chan
->device
->device_slave_caps
)
769 return chan
->device
->device_slave_caps(chan
, caps
);
774 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
776 return dmaengine_device_control(chan
, DMA_TERMINATE_ALL
, 0);
779 static inline int dmaengine_pause(struct dma_chan
*chan
)
781 return dmaengine_device_control(chan
, DMA_PAUSE
, 0);
784 static inline int dmaengine_resume(struct dma_chan
*chan
)
786 return dmaengine_device_control(chan
, DMA_RESUME
, 0);
789 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
790 dma_cookie_t cookie
, struct dma_tx_state
*state
)
792 return chan
->device
->device_tx_status(chan
, cookie
, state
);
795 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
797 return desc
->tx_submit(desc
);
800 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
806 mask
= (1 << align
) - 1;
807 if (mask
& (off1
| off2
| len
))
812 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
813 size_t off2
, size_t len
)
815 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
818 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
819 size_t off2
, size_t len
)
821 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
824 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
825 size_t off2
, size_t len
)
827 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
830 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
831 size_t off2
, size_t len
)
833 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
837 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
841 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
844 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
846 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
849 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
851 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
853 return (flags
& mask
) == mask
;
856 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
858 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
861 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
863 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
866 /* dma_maxpq - reduce maxpq in the face of continued operations
867 * @dma - dma device with PQ capability
868 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
870 * When an engine does not support native continuation we need 3 extra
871 * source slots to reuse P and Q with the following coefficients:
872 * 1/ {00} * P : remove P from Q', but use it as a source for P'
873 * 2/ {01} * Q : use Q to continue Q' calculation
874 * 3/ {00} * Q : subtract Q from P' to cancel (2)
876 * In the case where P is disabled we only need 1 extra source:
877 * 1/ {01} * Q : use Q to continue Q' calculation
879 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
881 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
882 return dma_dev_to_maxpq(dma
);
883 else if (dmaf_p_disabled_continue(flags
))
884 return dma_dev_to_maxpq(dma
) - 1;
885 else if (dmaf_continue(flags
))
886 return dma_dev_to_maxpq(dma
) - 3;
890 /* --- public DMA engine API --- */
892 #ifdef CONFIG_DMA_ENGINE
893 void dmaengine_get(void);
894 void dmaengine_put(void);
896 static inline void dmaengine_get(void)
899 static inline void dmaengine_put(void)
904 #ifdef CONFIG_NET_DMA
905 #define net_dmaengine_get() dmaengine_get()
906 #define net_dmaengine_put() dmaengine_put()
908 static inline void net_dmaengine_get(void)
911 static inline void net_dmaengine_put(void)
916 #ifdef CONFIG_ASYNC_TX_DMA
917 #define async_dmaengine_get() dmaengine_get()
918 #define async_dmaengine_put() dmaengine_put()
919 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
920 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
922 #define async_dma_find_channel(type) dma_find_channel(type)
923 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
925 static inline void async_dmaengine_get(void)
928 static inline void async_dmaengine_put(void)
931 static inline struct dma_chan
*
932 async_dma_find_channel(enum dma_transaction_type type
)
936 #endif /* CONFIG_ASYNC_TX_DMA */
938 dma_cookie_t
dma_async_memcpy_buf_to_buf(struct dma_chan
*chan
,
939 void *dest
, void *src
, size_t len
);
940 dma_cookie_t
dma_async_memcpy_buf_to_pg(struct dma_chan
*chan
,
941 struct page
*page
, unsigned int offset
, void *kdata
, size_t len
);
942 dma_cookie_t
dma_async_memcpy_pg_to_pg(struct dma_chan
*chan
,
943 struct page
*dest_pg
, unsigned int dest_off
, struct page
*src_pg
,
944 unsigned int src_off
, size_t len
);
945 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
946 struct dma_chan
*chan
);
948 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
950 tx
->flags
|= DMA_CTRL_ACK
;
953 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
955 tx
->flags
&= ~DMA_CTRL_ACK
;
958 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
960 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
963 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
965 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
967 set_bit(tx_type
, dstp
->bits
);
970 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
972 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
974 clear_bit(tx_type
, dstp
->bits
);
977 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
978 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
980 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
983 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
985 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
987 return test_bit(tx_type
, srcp
->bits
);
990 #define for_each_dma_cap_mask(cap, mask) \
991 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
994 * dma_async_issue_pending - flush pending transactions to HW
995 * @chan: target DMA channel
997 * This allows drivers to push copies to HW in batches,
998 * reducing MMIO writes where possible.
1000 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1002 chan
->device
->device_issue_pending(chan
);
1006 * dma_async_is_tx_complete - poll for transaction completion
1007 * @chan: DMA channel
1008 * @cookie: transaction identifier to check status of
1009 * @last: returns last completed cookie, can be NULL
1010 * @used: returns last issued cookie, can be NULL
1012 * If @last and @used are passed in, upon return they reflect the driver
1013 * internal state and can be used with dma_async_is_complete() to check
1014 * the status of multiple cookies without re-checking hardware state.
1016 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1017 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1019 struct dma_tx_state state
;
1020 enum dma_status status
;
1022 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1031 * dma_async_is_complete - test a cookie against chan state
1032 * @cookie: transaction identifier to test status of
1033 * @last_complete: last know completed transaction
1034 * @last_used: last cookie value handed out
1036 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1037 * the test logic is separated for lightweight testing of multiple cookies
1039 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1040 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1042 if (last_complete
<= last_used
) {
1043 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1044 return DMA_COMPLETE
;
1046 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1047 return DMA_COMPLETE
;
1049 return DMA_IN_PROGRESS
;
1053 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1058 st
->residue
= residue
;
1062 #ifdef CONFIG_DMA_ENGINE
1063 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1064 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1065 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1066 void dma_issue_pending_all(void);
1067 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1068 dma_filter_fn fn
, void *fn_param
);
1069 struct dma_chan
*dma_request_slave_channel_reason(struct device
*dev
,
1071 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1072 void dma_release_channel(struct dma_chan
*chan
);
1074 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1078 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1080 return DMA_COMPLETE
;
1082 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1084 return DMA_COMPLETE
;
1086 static inline void dma_issue_pending_all(void)
1089 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1090 dma_filter_fn fn
, void *fn_param
)
1094 static inline struct dma_chan
*dma_request_slave_channel_reason(
1095 struct device
*dev
, const char *name
)
1097 return ERR_PTR(-ENODEV
);
1099 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1104 static inline void dma_release_channel(struct dma_chan
*chan
)
1109 /* --- DMA device --- */
1111 int dma_async_device_register(struct dma_device
*device
);
1112 void dma_async_device_unregister(struct dma_device
*device
);
1113 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1114 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1115 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1116 struct dma_chan
*net_dma_find_channel(void);
1117 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1118 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1119 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1121 static inline struct dma_chan
1122 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1123 dma_filter_fn fn
, void *fn_param
,
1124 struct device
*dev
, char *name
)
1126 struct dma_chan
*chan
;
1128 chan
= dma_request_slave_channel(dev
, name
);
1132 return __dma_request_channel(mask
, fn
, fn_param
);
1135 /* --- Helper iov-locking functions --- */
1137 struct dma_page_list
{
1138 char __user
*base_address
;
1140 struct page
**pages
;
1143 struct dma_pinned_list
{
1145 struct dma_page_list page_list
[0];
1148 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
1149 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
1151 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
1152 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
1153 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
1154 struct dma_pinned_list
*pinned_list
, struct page
*page
,
1155 unsigned int offset
, size_t len
);
1157 #endif /* DMAENGINE_H */