iommu/vt-d: Introduce a rwsem to protect global data structures
[deliverable/linux.git] / include / linux / dmar.h
1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21 #ifndef __DMAR_H__
22 #define __DMAR_H__
23
24 #include <linux/acpi.h>
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/irqreturn.h>
28 #include <linux/rwsem.h>
29
30 struct acpi_dmar_header;
31
32 /* DMAR Flags */
33 #define DMAR_INTR_REMAP 0x1
34 #define DMAR_X2APIC_OPT_OUT 0x2
35
36 struct intel_iommu;
37
38 #ifdef CONFIG_DMAR_TABLE
39 extern struct acpi_table_header *dmar_tbl;
40 struct dmar_drhd_unit {
41 struct list_head list; /* list of drhd units */
42 struct acpi_dmar_header *hdr; /* ACPI header */
43 u64 reg_base_addr; /* register base address*/
44 struct pci_dev **devices; /* target device array */
45 int devices_cnt; /* target device count */
46 u16 segment; /* PCI domain */
47 u8 ignored:1; /* ignore drhd */
48 u8 include_all:1;
49 struct intel_iommu *iommu;
50 };
51
52 extern struct rw_semaphore dmar_global_lock;
53 extern struct list_head dmar_drhd_units;
54
55 #define for_each_drhd_unit(drhd) \
56 list_for_each_entry(drhd, &dmar_drhd_units, list)
57
58 #define for_each_active_drhd_unit(drhd) \
59 list_for_each_entry(drhd, &dmar_drhd_units, list) \
60 if (drhd->ignored) {} else
61
62 #define for_each_active_iommu(i, drhd) \
63 list_for_each_entry(drhd, &dmar_drhd_units, list) \
64 if (i=drhd->iommu, drhd->ignored) {} else
65
66 #define for_each_iommu(i, drhd) \
67 list_for_each_entry(drhd, &dmar_drhd_units, list) \
68 if (i=drhd->iommu, 0) {} else
69
70 #define for_each_dev_scope(a, c, p, d) \
71 for ((p) = 0; ((d) = (p) < (c) ? (a)[(p)] : NULL, (p) < (c)); (p)++)
72
73 #define for_each_active_dev_scope(a, c, p, d) \
74 for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else
75
76 extern int dmar_table_init(void);
77 extern int dmar_dev_scope_init(void);
78 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
79 struct pci_dev ***devices, u16 segment);
80 extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
81 extern void dmar_free_dev_scope(struct pci_dev ***devices, int *cnt);
82
83 /* Intel IOMMU detection */
84 extern int detect_intel_iommu(void);
85 extern int enable_drhd_fault_handling(void);
86 #else
87 static inline int detect_intel_iommu(void)
88 {
89 return -ENODEV;
90 }
91
92 static inline int dmar_table_init(void)
93 {
94 return -ENODEV;
95 }
96 static inline int enable_drhd_fault_handling(void)
97 {
98 return -1;
99 }
100 #endif /* !CONFIG_DMAR_TABLE */
101
102 struct irte {
103 union {
104 struct {
105 __u64 present : 1,
106 fpd : 1,
107 dst_mode : 1,
108 redir_hint : 1,
109 trigger_mode : 1,
110 dlvry_mode : 3,
111 avail : 4,
112 __reserved_1 : 4,
113 vector : 8,
114 __reserved_2 : 8,
115 dest_id : 32;
116 };
117 __u64 low;
118 };
119
120 union {
121 struct {
122 __u64 sid : 16,
123 sq : 2,
124 svt : 2,
125 __reserved_3 : 44;
126 };
127 __u64 high;
128 };
129 };
130
131 enum {
132 IRQ_REMAP_XAPIC_MODE,
133 IRQ_REMAP_X2APIC_MODE,
134 };
135
136 /* Can't use the common MSI interrupt functions
137 * since DMAR is not a pci device
138 */
139 struct irq_data;
140 extern void dmar_msi_unmask(struct irq_data *data);
141 extern void dmar_msi_mask(struct irq_data *data);
142 extern void dmar_msi_read(int irq, struct msi_msg *msg);
143 extern void dmar_msi_write(int irq, struct msi_msg *msg);
144 extern int dmar_set_interrupt(struct intel_iommu *iommu);
145 extern irqreturn_t dmar_fault(int irq, void *dev_id);
146 extern int arch_setup_dmar_msi(unsigned int irq);
147
148 #ifdef CONFIG_INTEL_IOMMU
149 extern int iommu_detected, no_iommu;
150 extern int dmar_parse_rmrr_atsr_dev(void);
151 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
152 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
153 extern int intel_iommu_init(void);
154 #else /* !CONFIG_INTEL_IOMMU: */
155 static inline int intel_iommu_init(void) { return -ENODEV; }
156 static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
157 {
158 return 0;
159 }
160 static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
161 {
162 return 0;
163 }
164 static inline int dmar_parse_rmrr_atsr_dev(void)
165 {
166 return 0;
167 }
168 #endif /* CONFIG_INTEL_IOMMU */
169
170 #endif /* __DMAR_H__ */
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