include/linux/irq.h

   1 #ifndef _LINUX_IRQ_H
   2 #define _LINUX_IRQ_H
   3
   4 /*
   5  * Please do not include this file in generic code.  There is currently
   6  * no requirement for any architecture to implement anything held
   7  * within this file.
   8  *
   9  * Thanks. --rmk
  10  */
  11
  12 #include <linux/smp.h>
  13 #include <linux/linkage.h>
  14 #include <linux/cache.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/cpumask.h>
  17 #include <linux/gfp.h>
  18 #include <linux/irqreturn.h>
  19 #include <linux/irqnr.h>
  20 #include <linux/errno.h>
  21 #include <linux/topology.h>
  22 #include <linux/wait.h>
  23
  24 #include <asm/irq.h>
  25 #include <asm/ptrace.h>
  26 #include <asm/irq_regs.h>
  27
  28 struct seq_file;
  29 struct module;
  30 struct irq_desc;
  31 struct irq_data;
  32 typedef void (*irq_flow_handler_t)(unsigned int irq,
  33                                             struct irq_desc *desc);
  34 typedef void (*irq_preflow_handler_t)(struct irq_data *data);
  35
  36 /*
  37  * IRQ line status.
  38  *
  39  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
  40  *
  41  * IRQ_TYPE_NONE                - default, unspecified type
  42  * IRQ_TYPE_EDGE_RISING         - rising edge triggered
  43  * IRQ_TYPE_EDGE_FALLING        - falling edge triggered
  44  * IRQ_TYPE_EDGE_BOTH           - rising and falling edge triggered
  45  * IRQ_TYPE_LEVEL_HIGH          - high level triggered
  46  * IRQ_TYPE_LEVEL_LOW           - low level triggered
  47  * IRQ_TYPE_LEVEL_MASK          - Mask to filter out the level bits
  48  * IRQ_TYPE_SENSE_MASK          - Mask for all the above bits
  49  * IRQ_TYPE_DEFAULT             - For use by some PICs to ask irq_set_type
  50  *                                to setup the HW to a sane default (used
  51  *                                by irqdomain map() callbacks to synchronize
  52  *                                the HW state and SW flags for a newly
  53  *                                allocated descriptor).
  54  *
  55  * IRQ_TYPE_PROBE               - Special flag for probing in progress
  56  *
  57  * Bits which can be modified via irq_set/clear/modify_status_flags()
  58  * IRQ_LEVEL                    - Interrupt is level type. Will be also
  59  *                                updated in the code when the above trigger
  60  *                                bits are modified via irq_set_irq_type()
  61  * IRQ_PER_CPU                  - Mark an interrupt PER_CPU. Will protect
  62  *                                it from affinity setting
  63  * IRQ_NOPROBE                  - Interrupt cannot be probed by autoprobing
  64  * IRQ_NOREQUEST                - Interrupt cannot be requested via
  65  *                                request_irq()
  66  * IRQ_NOTHREAD                 - Interrupt cannot be threaded
  67  * IRQ_NOAUTOEN                 - Interrupt is not automatically enabled in
  68  *                                request/setup_irq()
  69  * IRQ_NO_BALANCING             - Interrupt cannot be balanced (affinity set)
  70  * IRQ_MOVE_PCNTXT              - Interrupt can be migrated from process context
  71  * IRQ_NESTED_TRHEAD            - Interrupt nests into another thread
  72  * IRQ_PER_CPU_DEVID            - Dev_id is a per-cpu variable
  73  */
  74 enum {
  75         IRQ_TYPE_NONE           = 0x00000000,
  76         IRQ_TYPE_EDGE_RISING    = 0x00000001,
  77         IRQ_TYPE_EDGE_FALLING   = 0x00000002,
  78         IRQ_TYPE_EDGE_BOTH      = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
  79         IRQ_TYPE_LEVEL_HIGH     = 0x00000004,
  80         IRQ_TYPE_LEVEL_LOW      = 0x00000008,
  81         IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
  82         IRQ_TYPE_SENSE_MASK     = 0x0000000f,
  83         IRQ_TYPE_DEFAULT        = IRQ_TYPE_SENSE_MASK,
  84
  85         IRQ_TYPE_PROBE          = 0x00000010,
  86
  87         IRQ_LEVEL               = (1 <<  8),
  88         IRQ_PER_CPU             = (1 <<  9),
  89         IRQ_NOPROBE             = (1 << 10),
  90         IRQ_NOREQUEST           = (1 << 11),
  91         IRQ_NOAUTOEN            = (1 << 12),
  92         IRQ_NO_BALANCING        = (1 << 13),
  93         IRQ_MOVE_PCNTXT         = (1 << 14),
  94         IRQ_NESTED_THREAD       = (1 << 15),
  95         IRQ_NOTHREAD            = (1 << 16),
  96         IRQ_PER_CPU_DEVID       = (1 << 17),
  97 };
  98
  99 #define IRQF_MODIFY_MASK        \
 100         (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
 101          IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
 102          IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID)
 103
 104 #define IRQ_NO_BALANCING_MASK   (IRQ_PER_CPU | IRQ_NO_BALANCING)
 105
 106 /*
 107  * Return value for chip->irq_set_affinity()
 108  *
 109  * IRQ_SET_MASK_OK      - OK, core updates irq_data.affinity
 110  * IRQ_SET_MASK_NOCPY   - OK, chip did update irq_data.affinity
 111  */
 112 enum {
 113         IRQ_SET_MASK_OK = 0,
 114         IRQ_SET_MASK_OK_NOCOPY,
 115 };
 116
 117 struct msi_desc;
 118 struct irq_domain;
 119
 120 /**
 121  * struct irq_data - per irq and irq chip data passed down to chip functions
 122  * @mask:               precomputed bitmask for accessing the chip registers
 123  * @irq:                interrupt number
 124  * @hwirq:              hardware interrupt number, local to the interrupt domain
 125  * @node:               node index useful for balancing
 126  * @state_use_accessors: status information for irq chip functions.
 127  *                      Use accessor functions to deal with it
 128  * @chip:               low level interrupt hardware access
 129  * @domain:             Interrupt translation domain; responsible for mapping
 130  *                      between hwirq number and linux irq number.
 131  * @handler_data:       per-IRQ data for the irq_chip methods
 132  * @chip_data:          platform-specific per-chip private data for the chip
 133  *                      methods, to allow shared chip implementations
 134  * @msi_desc:           MSI descriptor
 135  * @affinity:           IRQ affinity on SMP
 136  *
 137  * The fields here need to overlay the ones in irq_desc until we
 138  * cleaned up the direct references and switched everything over to
 139  * irq_data.
 140  */
 141 struct irq_data {
 142         u32                     mask;
 143         unsigned int            irq;
 144         unsigned long           hwirq;
 145         unsigned int            node;
 146         unsigned int            state_use_accessors;
 147         struct irq_chip         *chip;
 148         struct irq_domain       *domain;
 149         void                    *handler_data;
 150         void                    *chip_data;
 151         struct msi_desc         *msi_desc;
 152         cpumask_var_t           affinity;
 153 };
 154
 155 /*
 156  * Bit masks for irq_data.state
 157  *
 158  * IRQD_TRIGGER_MASK            - Mask for the trigger type bits
 159  * IRQD_SETAFFINITY_PENDING     - Affinity setting is pending
 160  * IRQD_NO_BALANCING            - Balancing disabled for this IRQ
 161  * IRQD_PER_CPU                 - Interrupt is per cpu
 162  * IRQD_AFFINITY_SET            - Interrupt affinity was set
 163  * IRQD_LEVEL                   - Interrupt is level triggered
 164  * IRQD_WAKEUP_STATE            - Interrupt is configured for wakeup
 165  *                                from suspend
 166  * IRDQ_MOVE_PCNTXT             - Interrupt can be moved in process
 167  *                                context
 168  * IRQD_IRQ_DISABLED            - Disabled state of the interrupt
 169  * IRQD_IRQ_MASKED              - Masked state of the interrupt
 170  * IRQD_IRQ_INPROGRESS          - In progress state of the interrupt
 171  */
 172 enum {
 173         IRQD_TRIGGER_MASK               = 0xf,
 174         IRQD_SETAFFINITY_PENDING        = (1 <<  8),
 175         IRQD_NO_BALANCING               = (1 << 10),
 176         IRQD_PER_CPU                    = (1 << 11),
 177         IRQD_AFFINITY_SET               = (1 << 12),
 178         IRQD_LEVEL                      = (1 << 13),
 179         IRQD_WAKEUP_STATE               = (1 << 14),
 180         IRQD_MOVE_PCNTXT                = (1 << 15),
 181         IRQD_IRQ_DISABLED               = (1 << 16),
 182         IRQD_IRQ_MASKED                 = (1 << 17),
 183         IRQD_IRQ_INPROGRESS             = (1 << 18),
 184 };
 185
 186 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
 187 {
 188         return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
 189 }
 190
 191 static inline bool irqd_is_per_cpu(struct irq_data *d)
 192 {
 193         return d->state_use_accessors & IRQD_PER_CPU;
 194 }
 195
 196 static inline bool irqd_can_balance(struct irq_data *d)
 197 {
 198         return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
 199 }
 200
 201 static inline bool irqd_affinity_was_set(struct irq_data *d)
 202 {
 203         return d->state_use_accessors & IRQD_AFFINITY_SET;
 204 }
 205
 206 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
 207 {
 208         d->state_use_accessors |= IRQD_AFFINITY_SET;
 209 }
 210
 211 static inline u32 irqd_get_trigger_type(struct irq_data *d)
 212 {
 213         return d->state_use_accessors & IRQD_TRIGGER_MASK;
 214 }
 215
 216 /*
 217  * Must only be called inside irq_chip.irq_set_type() functions.
 218  */
 219 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
 220 {
 221         d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
 222         d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
 223 }
 224
 225 static inline bool irqd_is_level_type(struct irq_data *d)
 226 {
 227         return d->state_use_accessors & IRQD_LEVEL;
 228 }
 229
 230 static inline bool irqd_is_wakeup_set(struct irq_data *d)
 231 {
 232         return d->state_use_accessors & IRQD_WAKEUP_STATE;
 233 }
 234
 235 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
 236 {
 237         return d->state_use_accessors & IRQD_MOVE_PCNTXT;
 238 }
 239
 240 static inline bool irqd_irq_disabled(struct irq_data *d)
 241 {
 242         return d->state_use_accessors & IRQD_IRQ_DISABLED;
 243 }
 244
 245 static inline bool irqd_irq_masked(struct irq_data *d)
 246 {
 247         return d->state_use_accessors & IRQD_IRQ_MASKED;
 248 }
 249
 250 static inline bool irqd_irq_inprogress(struct irq_data *d)
 251 {
 252         return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
 253 }
 254
 255 /*
 256  * Functions for chained handlers which can be enabled/disabled by the
 257  * standard disable_irq/enable_irq calls. Must be called with
 258  * irq_desc->lock held.
 259  */
 260 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
 261 {
 262         d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
 263 }
 264
 265 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
 266 {
 267         d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
 268 }
 269
 270 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
 271 {
 272         return d->hwirq;
 273 }
 274
 275 /**
 276  * struct irq_chip - hardware interrupt chip descriptor
 277  *
 278  * @name:               name for /proc/interrupts
 279  * @irq_startup:        start up the interrupt (defaults to ->enable if NULL)
 280  * @irq_shutdown:       shut down the interrupt (defaults to ->disable if NULL)
 281  * @irq_enable:         enable the interrupt (defaults to chip->unmask if NULL)
 282  * @irq_disable:        disable the interrupt
 283  * @irq_ack:            start of a new interrupt
 284  * @irq_mask:           mask an interrupt source
 285  * @irq_mask_ack:       ack and mask an interrupt source
 286  * @irq_unmask:         unmask an interrupt source
 287  * @irq_eoi:            end of interrupt
 288  * @irq_set_affinity:   set the CPU affinity on SMP machines
 289  * @irq_retrigger:      resend an IRQ to the CPU
 290  * @irq_set_type:       set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 291  * @irq_set_wake:       enable/disable power-management wake-on of an IRQ
 292  * @irq_bus_lock:       function to lock access to slow bus (i2c) chips
 293  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
 294  * @irq_cpu_online:     configure an interrupt source for a secondary CPU
 295  * @irq_cpu_offline:    un-configure an interrupt source for a secondary CPU
 296  * @irq_suspend:        function called from core code on suspend once per chip
 297  * @irq_resume:         function called from core code on resume once per chip
 298  * @irq_pm_shutdown:    function called from core code on shutdown once per chip
 299  * @irq_calc_mask:      Optional function to set irq_data.mask for special cases
 300  * @irq_print_chip:     optional to print special chip info in show_interrupts
 301  * @flags:              chip specific flags
 302  */
 303 struct irq_chip {
 304         const char      *name;
 305         unsigned int    (*irq_startup)(struct irq_data *data);
 306         void            (*irq_shutdown)(struct irq_data *data);
 307         void            (*irq_enable)(struct irq_data *data);
 308         void            (*irq_disable)(struct irq_data *data);
 309
 310         void            (*irq_ack)(struct irq_data *data);
 311         void            (*irq_mask)(struct irq_data *data);
 312         void            (*irq_mask_ack)(struct irq_data *data);
 313         void            (*irq_unmask)(struct irq_data *data);
 314         void            (*irq_eoi)(struct irq_data *data);
 315
 316         int             (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
 317         int             (*irq_retrigger)(struct irq_data *data);
 318         int             (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
 319         int             (*irq_set_wake)(struct irq_data *data, unsigned int on);
 320
 321         void            (*irq_bus_lock)(struct irq_data *data);
 322         void            (*irq_bus_sync_unlock)(struct irq_data *data);
 323
 324         void            (*irq_cpu_online)(struct irq_data *data);
 325         void            (*irq_cpu_offline)(struct irq_data *data);
 326
 327         void            (*irq_suspend)(struct irq_data *data);
 328         void            (*irq_resume)(struct irq_data *data);
 329         void            (*irq_pm_shutdown)(struct irq_data *data);
 330
 331         void            (*irq_calc_mask)(struct irq_data *data);
 332
 333         void            (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
 334
 335         unsigned long   flags;
 336 };
 337
 338 /*
 339  * irq_chip specific flags
 340  *
 341  * IRQCHIP_SET_TYPE_MASKED:     Mask before calling chip.irq_set_type()
 342  * IRQCHIP_EOI_IF_HANDLED:      Only issue irq_eoi() when irq was handled
 343  * IRQCHIP_MASK_ON_SUSPEND:     Mask non wake irqs in the suspend path
 344  * IRQCHIP_ONOFFLINE_ENABLED:   Only call irq_on/off_line callbacks
 345  *                              when irq enabled
 346  * IRQCHIP_SKIP_SET_WAKE:       Skip chip.irq_set_wake(), for this irq chip
 347  */
 348 enum {
 349         IRQCHIP_SET_TYPE_MASKED         = (1 <<  0),
 350         IRQCHIP_EOI_IF_HANDLED          = (1 <<  1),
 351         IRQCHIP_MASK_ON_SUSPEND         = (1 <<  2),
 352         IRQCHIP_ONOFFLINE_ENABLED       = (1 <<  3),
 353         IRQCHIP_SKIP_SET_WAKE           = (1 <<  4),
 354         IRQCHIP_ONESHOT_SAFE            = (1 <<  5),
 355 };
 356
 357 /* This include will go away once we isolated irq_desc usage to core code */
 358 #include <linux/irqdesc.h>
 359
 360 /*
 361  * Pick up the arch-dependent methods:
 362  */
 363 #include <asm/hw_irq.h>
 364
 365 #ifndef NR_IRQS_LEGACY
 366 # define NR_IRQS_LEGACY 0
 367 #endif
 368
 369 #ifndef ARCH_IRQ_INIT_FLAGS
 370 # define ARCH_IRQ_INIT_FLAGS    0
 371 #endif
 372
 373 #define IRQ_DEFAULT_INIT_FLAGS  ARCH_IRQ_INIT_FLAGS
 374
 375 struct irqaction;
 376 extern int setup_irq(unsigned int irq, struct irqaction *new);
 377 extern void remove_irq(unsigned int irq, struct irqaction *act);
 378 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
 379 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
 380
 381 extern void irq_cpu_online(void);
 382 extern void irq_cpu_offline(void);
 383 extern int __irq_set_affinity_locked(struct irq_data *data,  const struct cpumask *cpumask);
 384
 385 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
 386 void irq_move_irq(struct irq_data *data);
 387 void irq_move_masked_irq(struct irq_data *data);
 388 #else
 389 static inline void irq_move_irq(struct irq_data *data) { }
 390 static inline void irq_move_masked_irq(struct irq_data *data) { }
 391 #endif
 392
 393 extern int no_irq_affinity;
 394
 395 #ifdef CONFIG_HARDIRQS_SW_RESEND
 396 int irq_set_parent(int irq, int parent_irq);
 397 #else
 398 static inline int irq_set_parent(int irq, int parent_irq)
 399 {
 400         return 0;
 401 }
 402 #endif
 403
 404 /*
 405  * Built-in IRQ handlers for various IRQ types,
 406  * callable via desc->handle_irq()
 407  */
 408 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
 409 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
 410 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
 411 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
 412 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
 413 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
 414 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
 415 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
 416 extern void handle_nested_irq(unsigned int irq);
 417
 418 /* Handling of unhandled and spurious interrupts: */
 419 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
 420                            irqreturn_t action_ret);
 421
 422
 423 /* Enable/disable irq debugging output: */
 424 extern int noirqdebug_setup(char *str);
 425
 426 /* Checks whether the interrupt can be requested by request_irq(): */
 427 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
 428
 429 /* Dummy irq-chip implementations: */
 430 extern struct irq_chip no_irq_chip;
 431 extern struct irq_chip dummy_irq_chip;
 432
 433 extern void
 434 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
 435                               irq_flow_handler_t handle, const char *name);
 436
 437 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
 438                                             irq_flow_handler_t handle)
 439 {
 440         irq_set_chip_and_handler_name(irq, chip, handle, NULL);
 441 }
 442
 443 extern int irq_set_percpu_devid(unsigned int irq);
 444
 445 extern void
 446 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
 447                   const char *name);
 448
 449 static inline void
 450 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
 451 {
 452         __irq_set_handler(irq, handle, 0, NULL);
 453 }
 454
 455 /*
 456  * Set a highlevel chained flow handler for a given IRQ.
 457  * (a chained handler is automatically enabled and set to
 458  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
 459  */
 460 static inline void
 461 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
 462 {
 463         __irq_set_handler(irq, handle, 1, NULL);
 464 }
 465
 466 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
 467
 468 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
 469 {
 470         irq_modify_status(irq, 0, set);
 471 }
 472
 473 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
 474 {
 475         irq_modify_status(irq, clr, 0);
 476 }
 477
 478 static inline void irq_set_noprobe(unsigned int irq)
 479 {
 480         irq_modify_status(irq, 0, IRQ_NOPROBE);
 481 }
 482
 483 static inline void irq_set_probe(unsigned int irq)
 484 {
 485         irq_modify_status(irq, IRQ_NOPROBE, 0);
 486 }
 487
 488 static inline void irq_set_nothread(unsigned int irq)
 489 {
 490         irq_modify_status(irq, 0, IRQ_NOTHREAD);
 491 }
 492
 493 static inline void irq_set_thread(unsigned int irq)
 494 {
 495         irq_modify_status(irq, IRQ_NOTHREAD, 0);
 496 }
 497
 498 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
 499 {
 500         if (nest)
 501                 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
 502         else
 503                 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
 504 }
 505
 506 static inline void irq_set_percpu_devid_flags(unsigned int irq)
 507 {
 508         irq_set_status_flags(irq,
 509                              IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
 510                              IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
 511 }
 512
 513 /* Handle dynamic irq creation and destruction */
 514 extern unsigned int create_irq_nr(unsigned int irq_want, int node);
 515 extern unsigned int __create_irqs(unsigned int from, unsigned int count,
 516                                   int node);
 517 extern int create_irq(void);
 518 extern void destroy_irq(unsigned int irq);
 519 extern void destroy_irqs(unsigned int irq, unsigned int count);
 520
 521 /*
 522  * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
 523  * irq_free_desc instead.
 524  */
 525 extern void dynamic_irq_cleanup(unsigned int irq);
 526 static inline void dynamic_irq_init(unsigned int irq)
 527 {
 528         dynamic_irq_cleanup(irq);
 529 }
 530
 531 /* Set/get chip/data for an IRQ: */
 532 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
 533 extern int irq_set_handler_data(unsigned int irq, void *data);
 534 extern int irq_set_chip_data(unsigned int irq, void *data);
 535 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
 536 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
 537 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
 538                                 struct msi_desc *entry);
 539 extern struct irq_data *irq_get_irq_data(unsigned int irq);
 540
 541 static inline struct irq_chip *irq_get_chip(unsigned int irq)
 542 {
 543         struct irq_data *d = irq_get_irq_data(irq);
 544         return d ? d->chip : NULL;
 545 }
 546
 547 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
 548 {
 549         return d->chip;
 550 }
 551
 552 static inline void *irq_get_chip_data(unsigned int irq)
 553 {
 554         struct irq_data *d = irq_get_irq_data(irq);
 555         return d ? d->chip_data : NULL;
 556 }
 557
 558 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
 559 {
 560         return d->chip_data;
 561 }
 562
 563 static inline void *irq_get_handler_data(unsigned int irq)
 564 {
 565         struct irq_data *d = irq_get_irq_data(irq);
 566         return d ? d->handler_data : NULL;
 567 }
 568
 569 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
 570 {
 571         return d->handler_data;
 572 }
 573
 574 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
 575 {
 576         struct irq_data *d = irq_get_irq_data(irq);
 577         return d ? d->msi_desc : NULL;
 578 }
 579
 580 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
 581 {
 582         return d->msi_desc;
 583 }
 584
 585 static inline u32 irq_get_trigger_type(unsigned int irq)
 586 {
 587         struct irq_data *d = irq_get_irq_data(irq);
 588         return d ? irqd_get_trigger_type(d) : 0;
 589 }
 590
 591 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
 592                 struct module *owner);
 593
 594 /* use macros to avoid needing export.h for THIS_MODULE */
 595 #define irq_alloc_descs(irq, from, cnt, node)   \
 596         __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
 597
 598 #define irq_alloc_desc(node)                    \
 599         irq_alloc_descs(-1, 0, 1, node)
 600
 601 #define irq_alloc_desc_at(at, node)             \
 602         irq_alloc_descs(at, at, 1, node)
 603
 604 #define irq_alloc_desc_from(from, node)         \
 605         irq_alloc_descs(-1, from, 1, node)
 606
 607 #define irq_alloc_descs_from(from, cnt, node)   \
 608         irq_alloc_descs(-1, from, cnt, node)
 609
 610 void irq_free_descs(unsigned int irq, unsigned int cnt);
 611 int irq_reserve_irqs(unsigned int from, unsigned int cnt);
 612
 613 static inline void irq_free_desc(unsigned int irq)
 614 {
 615         irq_free_descs(irq, 1);
 616 }
 617
 618 static inline int irq_reserve_irq(unsigned int irq)
 619 {
 620         return irq_reserve_irqs(irq, 1);
 621 }
 622
 623 #ifndef irq_reg_writel
 624 # define irq_reg_writel(val, addr)      writel(val, addr)
 625 #endif
 626 #ifndef irq_reg_readl
 627 # define irq_reg_readl(addr)            readl(addr)
 628 #endif
 629
 630 /**
 631  * struct irq_chip_regs - register offsets for struct irq_gci
 632  * @enable:     Enable register offset to reg_base
 633  * @disable:    Disable register offset to reg_base
 634  * @mask:       Mask register offset to reg_base
 635  * @ack:        Ack register offset to reg_base
 636  * @eoi:        Eoi register offset to reg_base
 637  * @type:       Type configuration register offset to reg_base
 638  * @polarity:   Polarity configuration register offset to reg_base
 639  */
 640 struct irq_chip_regs {
 641         unsigned long           enable;
 642         unsigned long           disable;
 643         unsigned long           mask;
 644         unsigned long           ack;
 645         unsigned long           eoi;
 646         unsigned long           type;
 647         unsigned long           polarity;
 648 };
 649
 650 /**
 651  * struct irq_chip_type - Generic interrupt chip instance for a flow type
 652  * @chip:               The real interrupt chip which provides the callbacks
 653  * @regs:               Register offsets for this chip
 654  * @handler:            Flow handler associated with this chip
 655  * @type:               Chip can handle these flow types
 656  * @mask_cache_priv:    Cached mask register private to the chip type
 657  * @mask_cache:         Pointer to cached mask register
 658  *
 659  * A irq_generic_chip can have several instances of irq_chip_type when
 660  * it requires different functions and register offsets for different
 661  * flow types.
 662  */
 663 struct irq_chip_type {
 664         struct irq_chip         chip;
 665         struct irq_chip_regs    regs;
 666         irq_flow_handler_t      handler;
 667         u32                     type;
 668         u32                     mask_cache_priv;
 669         u32                     *mask_cache;
 670 };
 671
 672 /**
 673  * struct irq_chip_generic - Generic irq chip data structure
 674  * @lock:               Lock to protect register and cache data access
 675  * @reg_base:           Register base address (virtual)
 676  * @irq_base:           Interrupt base nr for this chip
 677  * @irq_cnt:            Number of interrupts handled by this chip
 678  * @mask_cache:         Cached mask register shared between all chip types
 679  * @type_cache:         Cached type register
 680  * @polarity_cache:     Cached polarity register
 681  * @wake_enabled:       Interrupt can wakeup from suspend
 682  * @wake_active:        Interrupt is marked as an wakeup from suspend source
 683  * @num_ct:             Number of available irq_chip_type instances (usually 1)
 684  * @private:            Private data for non generic chip callbacks
 685  * @installed:          bitfield to denote installed interrupts
 686  * @unused:             bitfield to denote unused interrupts
 687  * @domain:             irq domain pointer
 688  * @list:               List head for keeping track of instances
 689  * @chip_types:         Array of interrupt irq_chip_types
 690  *
 691  * Note, that irq_chip_generic can have multiple irq_chip_type
 692  * implementations which can be associated to a particular irq line of
 693  * an irq_chip_generic instance. That allows to share and protect
 694  * state in an irq_chip_generic instance when we need to implement
 695  * different flow mechanisms (level/edge) for it.
 696  */
 697 struct irq_chip_generic {
 698         raw_spinlock_t          lock;
 699         void __iomem            *reg_base;
 700         unsigned int            irq_base;
 701         unsigned int            irq_cnt;
 702         u32                     mask_cache;
 703         u32                     type_cache;
 704         u32                     polarity_cache;
 705         u32                     wake_enabled;
 706         u32                     wake_active;
 707         unsigned int            num_ct;
 708         void                    *private;
 709         unsigned long           installed;
 710         unsigned long           unused;
 711         struct irq_domain       *domain;
 712         struct list_head        list;
 713         struct irq_chip_type    chip_types[0];
 714 };
 715
 716 /**
 717  * enum irq_gc_flags - Initialization flags for generic irq chips
 718  * @IRQ_GC_INIT_MASK_CACHE:     Initialize the mask_cache by reading mask reg
 719  * @IRQ_GC_INIT_NESTED_LOCK:    Set the lock class of the irqs to nested for
 720  *                              irq chips which need to call irq_set_wake() on
 721  *                              the parent irq. Usually GPIO implementations
 722  * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
 723  * @IRQ_GC_NO_MASK:             Do not calculate irq_data->mask
 724  */
 725 enum irq_gc_flags {
 726         IRQ_GC_INIT_MASK_CACHE          = 1 << 0,
 727         IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
 728         IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
 729         IRQ_GC_NO_MASK                  = 1 << 3,
 730 };
 731
 732 /*
 733  * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
 734  * @irqs_per_chip:      Number of interrupts per chip
 735  * @num_chips:          Number of chips
 736  * @irq_flags_to_set:   IRQ* flags to set on irq setup
 737  * @irq_flags_to_clear: IRQ* flags to clear on irq setup
 738  * @gc_flags:           Generic chip specific setup flags
 739  * @gc:                 Array of pointers to generic interrupt chips
 740  */
 741 struct irq_domain_chip_generic {
 742         unsigned int            irqs_per_chip;
 743         unsigned int            num_chips;
 744         unsigned int            irq_flags_to_clear;
 745         unsigned int            irq_flags_to_set;
 746         enum irq_gc_flags       gc_flags;
 747         struct irq_chip_generic *gc[0];
 748 };
 749
 750 /* Generic chip callback functions */
 751 void irq_gc_noop(struct irq_data *d);
 752 void irq_gc_mask_disable_reg(struct irq_data *d);
 753 void irq_gc_mask_set_bit(struct irq_data *d);
 754 void irq_gc_mask_clr_bit(struct irq_data *d);
 755 void irq_gc_unmask_enable_reg(struct irq_data *d);
 756 void irq_gc_ack_set_bit(struct irq_data *d);
 757 void irq_gc_ack_clr_bit(struct irq_data *d);
 758 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
 759 void irq_gc_eoi(struct irq_data *d);
 760 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
 761
 762 /* Setup functions for irq_chip_generic */
 763 struct irq_chip_generic *
 764 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
 765                        void __iomem *reg_base, irq_flow_handler_t handler);
 766 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 767                             enum irq_gc_flags flags, unsigned int clr,
 768                             unsigned int set);
 769 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
 770 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 771                              unsigned int clr, unsigned int set);
 772
 773 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
 774 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 775                                    int num_ct, const char *name,
 776                                    irq_flow_handler_t handler,
 777                                    unsigned int clr, unsigned int set,
 778                                    enum irq_gc_flags flags);
 779
 780
 781 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
 782 {
 783         return container_of(d->chip, struct irq_chip_type, chip);
 784 }
 785
 786 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
 787
 788 #ifdef CONFIG_SMP
 789 static inline void irq_gc_lock(struct irq_chip_generic *gc)
 790 {
 791         raw_spin_lock(&gc->lock);
 792 }
 793
 794 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
 795 {
 796         raw_spin_unlock(&gc->lock);
 797 }
 798 #else
 799 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
 800 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
 801 #endif
 802
 803 #endif /* _LINUX_IRQ_H */