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Merge branch 'overlayfs-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mszere...
[deliverable/linux.git] / include / linux / irq.h
1 #ifndef _LINUX_IRQ_H
2 #define _LINUX_IRQ_H
3
4 /*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
24 #include <linux/io.h>
25
26 #include <asm/irq.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
29
30 struct seq_file;
31 struct module;
32 struct msi_msg;
33 enum irqchip_irq_state;
34
35 /*
36 * IRQ line status.
37 *
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
39 *
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
53 *
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
55 *
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
64 * request_irq()
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
67 * request/setup_irq()
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 */
76 enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
86
87 IRQ_TYPE_PROBE = 0x00000010,
88
89 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
97 IRQ_NOTHREAD = (1 << 16),
98 IRQ_PER_CPU_DEVID = (1 << 17),
99 IRQ_IS_POLLED = (1 << 18),
100 };
101
102 #define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 IRQ_IS_POLLED)
107
108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
109
110 /*
111 * Return value for chip->irq_set_affinity()
112 *
113 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
118 */
119 enum {
120 IRQ_SET_MASK_OK = 0,
121 IRQ_SET_MASK_OK_NOCOPY,
122 IRQ_SET_MASK_OK_DONE,
123 };
124
125 struct msi_desc;
126 struct irq_domain;
127
128 /**
129 * struct irq_common_data - per irq data shared by all irqchips
130 * @state_use_accessors: status information for irq chip functions.
131 * Use accessor functions to deal with it
132 */
133 struct irq_common_data {
134 unsigned int state_use_accessors;
135 };
136
137 /**
138 * struct irq_data - per irq chip data passed down to chip functions
139 * @mask: precomputed bitmask for accessing the chip registers
140 * @irq: interrupt number
141 * @hwirq: hardware interrupt number, local to the interrupt domain
142 * @node: node index useful for balancing
143 * @common: point to data shared by all irqchips
144 * @chip: low level interrupt hardware access
145 * @domain: Interrupt translation domain; responsible for mapping
146 * between hwirq number and linux irq number.
147 * @parent_data: pointer to parent struct irq_data to support hierarchy
148 * irq_domain
149 * @handler_data: per-IRQ data for the irq_chip methods
150 * @chip_data: platform-specific per-chip private data for the chip
151 * methods, to allow shared chip implementations
152 * @msi_desc: MSI descriptor
153 * @affinity: IRQ affinity on SMP
154 *
155 * The fields here need to overlay the ones in irq_desc until we
156 * cleaned up the direct references and switched everything over to
157 * irq_data.
158 */
159 struct irq_data {
160 u32 mask;
161 unsigned int irq;
162 unsigned long hwirq;
163 unsigned int node;
164 struct irq_common_data *common;
165 struct irq_chip *chip;
166 struct irq_domain *domain;
167 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
168 struct irq_data *parent_data;
169 #endif
170 void *handler_data;
171 void *chip_data;
172 struct msi_desc *msi_desc;
173 cpumask_var_t affinity;
174 };
175
176 /*
177 * Bit masks for irq_common_data.state_use_accessors
178 *
179 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
180 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
181 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
182 * IRQD_PER_CPU - Interrupt is per cpu
183 * IRQD_AFFINITY_SET - Interrupt affinity was set
184 * IRQD_LEVEL - Interrupt is level triggered
185 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
186 * from suspend
187 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
188 * context
189 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
190 * IRQD_IRQ_MASKED - Masked state of the interrupt
191 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
192 * IRQD_WAKEUP_ARMED - Wakeup mode armed
193 */
194 enum {
195 IRQD_TRIGGER_MASK = 0xf,
196 IRQD_SETAFFINITY_PENDING = (1 << 8),
197 IRQD_NO_BALANCING = (1 << 10),
198 IRQD_PER_CPU = (1 << 11),
199 IRQD_AFFINITY_SET = (1 << 12),
200 IRQD_LEVEL = (1 << 13),
201 IRQD_WAKEUP_STATE = (1 << 14),
202 IRQD_MOVE_PCNTXT = (1 << 15),
203 IRQD_IRQ_DISABLED = (1 << 16),
204 IRQD_IRQ_MASKED = (1 << 17),
205 IRQD_IRQ_INPROGRESS = (1 << 18),
206 IRQD_WAKEUP_ARMED = (1 << 19),
207 };
208
209 #define __irqd_to_state(d) ((d)->common->state_use_accessors)
210
211 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
212 {
213 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
214 }
215
216 static inline bool irqd_is_per_cpu(struct irq_data *d)
217 {
218 return __irqd_to_state(d) & IRQD_PER_CPU;
219 }
220
221 static inline bool irqd_can_balance(struct irq_data *d)
222 {
223 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
224 }
225
226 static inline bool irqd_affinity_was_set(struct irq_data *d)
227 {
228 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
229 }
230
231 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
232 {
233 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
234 }
235
236 static inline u32 irqd_get_trigger_type(struct irq_data *d)
237 {
238 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
239 }
240
241 /*
242 * Must only be called inside irq_chip.irq_set_type() functions.
243 */
244 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
245 {
246 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
247 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
248 }
249
250 static inline bool irqd_is_level_type(struct irq_data *d)
251 {
252 return __irqd_to_state(d) & IRQD_LEVEL;
253 }
254
255 static inline bool irqd_is_wakeup_set(struct irq_data *d)
256 {
257 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
258 }
259
260 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
261 {
262 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
263 }
264
265 static inline bool irqd_irq_disabled(struct irq_data *d)
266 {
267 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
268 }
269
270 static inline bool irqd_irq_masked(struct irq_data *d)
271 {
272 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
273 }
274
275 static inline bool irqd_irq_inprogress(struct irq_data *d)
276 {
277 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
278 }
279
280 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
281 {
282 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
283 }
284
285
286 /*
287 * Functions for chained handlers which can be enabled/disabled by the
288 * standard disable_irq/enable_irq calls. Must be called with
289 * irq_desc->lock held.
290 */
291 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
292 {
293 __irqd_to_state(d) |= IRQD_IRQ_INPROGRESS;
294 }
295
296 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
297 {
298 __irqd_to_state(d) &= ~IRQD_IRQ_INPROGRESS;
299 }
300
301 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
302 {
303 return d->hwirq;
304 }
305
306 /**
307 * struct irq_chip - hardware interrupt chip descriptor
308 *
309 * @name: name for /proc/interrupts
310 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
311 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
312 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
313 * @irq_disable: disable the interrupt
314 * @irq_ack: start of a new interrupt
315 * @irq_mask: mask an interrupt source
316 * @irq_mask_ack: ack and mask an interrupt source
317 * @irq_unmask: unmask an interrupt source
318 * @irq_eoi: end of interrupt
319 * @irq_set_affinity: set the CPU affinity on SMP machines
320 * @irq_retrigger: resend an IRQ to the CPU
321 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
322 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
323 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
324 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
325 * @irq_cpu_online: configure an interrupt source for a secondary CPU
326 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
327 * @irq_suspend: function called from core code on suspend once per chip
328 * @irq_resume: function called from core code on resume once per chip
329 * @irq_pm_shutdown: function called from core code on shutdown once per chip
330 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
331 * @irq_print_chip: optional to print special chip info in show_interrupts
332 * @irq_request_resources: optional to request resources before calling
333 * any other callback related to this irq
334 * @irq_release_resources: optional to release resources acquired with
335 * irq_request_resources
336 * @irq_compose_msi_msg: optional to compose message content for MSI
337 * @irq_write_msi_msg: optional to write message content for MSI
338 * @irq_get_irqchip_state: return the internal state of an interrupt
339 * @irq_set_irqchip_state: set the internal state of a interrupt
340 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
341 * @flags: chip specific flags
342 */
343 struct irq_chip {
344 const char *name;
345 unsigned int (*irq_startup)(struct irq_data *data);
346 void (*irq_shutdown)(struct irq_data *data);
347 void (*irq_enable)(struct irq_data *data);
348 void (*irq_disable)(struct irq_data *data);
349
350 void (*irq_ack)(struct irq_data *data);
351 void (*irq_mask)(struct irq_data *data);
352 void (*irq_mask_ack)(struct irq_data *data);
353 void (*irq_unmask)(struct irq_data *data);
354 void (*irq_eoi)(struct irq_data *data);
355
356 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
357 int (*irq_retrigger)(struct irq_data *data);
358 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
359 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
360
361 void (*irq_bus_lock)(struct irq_data *data);
362 void (*irq_bus_sync_unlock)(struct irq_data *data);
363
364 void (*irq_cpu_online)(struct irq_data *data);
365 void (*irq_cpu_offline)(struct irq_data *data);
366
367 void (*irq_suspend)(struct irq_data *data);
368 void (*irq_resume)(struct irq_data *data);
369 void (*irq_pm_shutdown)(struct irq_data *data);
370
371 void (*irq_calc_mask)(struct irq_data *data);
372
373 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
374 int (*irq_request_resources)(struct irq_data *data);
375 void (*irq_release_resources)(struct irq_data *data);
376
377 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
378 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
379
380 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
381 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
382
383 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
384
385 unsigned long flags;
386 };
387
388 /*
389 * irq_chip specific flags
390 *
391 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
392 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
393 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
394 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
395 * when irq enabled
396 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
397 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
398 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
399 */
400 enum {
401 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
402 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
403 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
404 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
405 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
406 IRQCHIP_ONESHOT_SAFE = (1 << 5),
407 IRQCHIP_EOI_THREADED = (1 << 6),
408 };
409
410 #include <linux/irqdesc.h>
411
412 /*
413 * Pick up the arch-dependent methods:
414 */
415 #include <asm/hw_irq.h>
416
417 #ifndef NR_IRQS_LEGACY
418 # define NR_IRQS_LEGACY 0
419 #endif
420
421 #ifndef ARCH_IRQ_INIT_FLAGS
422 # define ARCH_IRQ_INIT_FLAGS 0
423 #endif
424
425 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
426
427 struct irqaction;
428 extern int setup_irq(unsigned int irq, struct irqaction *new);
429 extern void remove_irq(unsigned int irq, struct irqaction *act);
430 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
431 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
432
433 extern void irq_cpu_online(void);
434 extern void irq_cpu_offline(void);
435 extern int irq_set_affinity_locked(struct irq_data *data,
436 const struct cpumask *cpumask, bool force);
437 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
438
439 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
440 void irq_move_irq(struct irq_data *data);
441 void irq_move_masked_irq(struct irq_data *data);
442 #else
443 static inline void irq_move_irq(struct irq_data *data) { }
444 static inline void irq_move_masked_irq(struct irq_data *data) { }
445 #endif
446
447 extern int no_irq_affinity;
448
449 #ifdef CONFIG_HARDIRQS_SW_RESEND
450 int irq_set_parent(int irq, int parent_irq);
451 #else
452 static inline int irq_set_parent(int irq, int parent_irq)
453 {
454 return 0;
455 }
456 #endif
457
458 /*
459 * Built-in IRQ handlers for various IRQ types,
460 * callable via desc->handle_irq()
461 */
462 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
463 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
464 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
465 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
466 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
467 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
468 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
469 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
470 extern void handle_nested_irq(unsigned int irq);
471
472 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
473 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
474 extern void irq_chip_enable_parent(struct irq_data *data);
475 extern void irq_chip_disable_parent(struct irq_data *data);
476 extern void irq_chip_ack_parent(struct irq_data *data);
477 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
478 extern void irq_chip_mask_parent(struct irq_data *data);
479 extern void irq_chip_unmask_parent(struct irq_data *data);
480 extern void irq_chip_eoi_parent(struct irq_data *data);
481 extern int irq_chip_set_affinity_parent(struct irq_data *data,
482 const struct cpumask *dest,
483 bool force);
484 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
485 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
486 void *vcpu_info);
487 #endif
488
489 /* Handling of unhandled and spurious interrupts: */
490 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
491 irqreturn_t action_ret);
492
493
494 /* Enable/disable irq debugging output: */
495 extern int noirqdebug_setup(char *str);
496
497 /* Checks whether the interrupt can be requested by request_irq(): */
498 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
499
500 /* Dummy irq-chip implementations: */
501 extern struct irq_chip no_irq_chip;
502 extern struct irq_chip dummy_irq_chip;
503
504 extern void
505 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
506 irq_flow_handler_t handle, const char *name);
507
508 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
509 irq_flow_handler_t handle)
510 {
511 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
512 }
513
514 extern int irq_set_percpu_devid(unsigned int irq);
515
516 extern void
517 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
518 const char *name);
519
520 static inline void
521 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
522 {
523 __irq_set_handler(irq, handle, 0, NULL);
524 }
525
526 /*
527 * Set a highlevel chained flow handler for a given IRQ.
528 * (a chained handler is automatically enabled and set to
529 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
530 */
531 static inline void
532 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
533 {
534 __irq_set_handler(irq, handle, 1, NULL);
535 }
536
537 /*
538 * Set a highlevel chained flow handler and its data for a given IRQ.
539 * (a chained handler is automatically enabled and set to
540 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
541 */
542 void
543 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
544 void *data);
545
546 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
547
548 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
549 {
550 irq_modify_status(irq, 0, set);
551 }
552
553 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
554 {
555 irq_modify_status(irq, clr, 0);
556 }
557
558 static inline void irq_set_noprobe(unsigned int irq)
559 {
560 irq_modify_status(irq, 0, IRQ_NOPROBE);
561 }
562
563 static inline void irq_set_probe(unsigned int irq)
564 {
565 irq_modify_status(irq, IRQ_NOPROBE, 0);
566 }
567
568 static inline void irq_set_nothread(unsigned int irq)
569 {
570 irq_modify_status(irq, 0, IRQ_NOTHREAD);
571 }
572
573 static inline void irq_set_thread(unsigned int irq)
574 {
575 irq_modify_status(irq, IRQ_NOTHREAD, 0);
576 }
577
578 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
579 {
580 if (nest)
581 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
582 else
583 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
584 }
585
586 static inline void irq_set_percpu_devid_flags(unsigned int irq)
587 {
588 irq_set_status_flags(irq,
589 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
590 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
591 }
592
593 /* Set/get chip/data for an IRQ: */
594 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
595 extern int irq_set_handler_data(unsigned int irq, void *data);
596 extern int irq_set_chip_data(unsigned int irq, void *data);
597 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
598 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
599 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
600 struct msi_desc *entry);
601 extern struct irq_data *irq_get_irq_data(unsigned int irq);
602
603 static inline struct irq_chip *irq_get_chip(unsigned int irq)
604 {
605 struct irq_data *d = irq_get_irq_data(irq);
606 return d ? d->chip : NULL;
607 }
608
609 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
610 {
611 return d->chip;
612 }
613
614 static inline void *irq_get_chip_data(unsigned int irq)
615 {
616 struct irq_data *d = irq_get_irq_data(irq);
617 return d ? d->chip_data : NULL;
618 }
619
620 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
621 {
622 return d->chip_data;
623 }
624
625 static inline void *irq_get_handler_data(unsigned int irq)
626 {
627 struct irq_data *d = irq_get_irq_data(irq);
628 return d ? d->handler_data : NULL;
629 }
630
631 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
632 {
633 return d->handler_data;
634 }
635
636 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
637 {
638 struct irq_data *d = irq_get_irq_data(irq);
639 return d ? d->msi_desc : NULL;
640 }
641
642 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
643 {
644 return d->msi_desc;
645 }
646
647 static inline u32 irq_get_trigger_type(unsigned int irq)
648 {
649 struct irq_data *d = irq_get_irq_data(irq);
650 return d ? irqd_get_trigger_type(d) : 0;
651 }
652
653 static inline int irq_data_get_node(struct irq_data *d)
654 {
655 return d->node;
656 }
657
658 static inline struct cpumask *irq_get_affinity_mask(int irq)
659 {
660 struct irq_data *d = irq_get_irq_data(irq);
661
662 return d ? d->affinity : NULL;
663 }
664
665 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
666 {
667 return d->affinity;
668 }
669
670 unsigned int arch_dynirq_lower_bound(unsigned int from);
671
672 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
673 struct module *owner);
674
675 /* use macros to avoid needing export.h for THIS_MODULE */
676 #define irq_alloc_descs(irq, from, cnt, node) \
677 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
678
679 #define irq_alloc_desc(node) \
680 irq_alloc_descs(-1, 0, 1, node)
681
682 #define irq_alloc_desc_at(at, node) \
683 irq_alloc_descs(at, at, 1, node)
684
685 #define irq_alloc_desc_from(from, node) \
686 irq_alloc_descs(-1, from, 1, node)
687
688 #define irq_alloc_descs_from(from, cnt, node) \
689 irq_alloc_descs(-1, from, cnt, node)
690
691 void irq_free_descs(unsigned int irq, unsigned int cnt);
692 static inline void irq_free_desc(unsigned int irq)
693 {
694 irq_free_descs(irq, 1);
695 }
696
697 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
698 unsigned int irq_alloc_hwirqs(int cnt, int node);
699 static inline unsigned int irq_alloc_hwirq(int node)
700 {
701 return irq_alloc_hwirqs(1, node);
702 }
703 void irq_free_hwirqs(unsigned int from, int cnt);
704 static inline void irq_free_hwirq(unsigned int irq)
705 {
706 return irq_free_hwirqs(irq, 1);
707 }
708 int arch_setup_hwirq(unsigned int irq, int node);
709 void arch_teardown_hwirq(unsigned int irq);
710 #endif
711
712 #ifdef CONFIG_GENERIC_IRQ_LEGACY
713 void irq_init_desc(unsigned int irq);
714 #endif
715
716 /**
717 * struct irq_chip_regs - register offsets for struct irq_gci
718 * @enable: Enable register offset to reg_base
719 * @disable: Disable register offset to reg_base
720 * @mask: Mask register offset to reg_base
721 * @ack: Ack register offset to reg_base
722 * @eoi: Eoi register offset to reg_base
723 * @type: Type configuration register offset to reg_base
724 * @polarity: Polarity configuration register offset to reg_base
725 */
726 struct irq_chip_regs {
727 unsigned long enable;
728 unsigned long disable;
729 unsigned long mask;
730 unsigned long ack;
731 unsigned long eoi;
732 unsigned long type;
733 unsigned long polarity;
734 };
735
736 /**
737 * struct irq_chip_type - Generic interrupt chip instance for a flow type
738 * @chip: The real interrupt chip which provides the callbacks
739 * @regs: Register offsets for this chip
740 * @handler: Flow handler associated with this chip
741 * @type: Chip can handle these flow types
742 * @mask_cache_priv: Cached mask register private to the chip type
743 * @mask_cache: Pointer to cached mask register
744 *
745 * A irq_generic_chip can have several instances of irq_chip_type when
746 * it requires different functions and register offsets for different
747 * flow types.
748 */
749 struct irq_chip_type {
750 struct irq_chip chip;
751 struct irq_chip_regs regs;
752 irq_flow_handler_t handler;
753 u32 type;
754 u32 mask_cache_priv;
755 u32 *mask_cache;
756 };
757
758 /**
759 * struct irq_chip_generic - Generic irq chip data structure
760 * @lock: Lock to protect register and cache data access
761 * @reg_base: Register base address (virtual)
762 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
763 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
764 * @irq_base: Interrupt base nr for this chip
765 * @irq_cnt: Number of interrupts handled by this chip
766 * @mask_cache: Cached mask register shared between all chip types
767 * @type_cache: Cached type register
768 * @polarity_cache: Cached polarity register
769 * @wake_enabled: Interrupt can wakeup from suspend
770 * @wake_active: Interrupt is marked as an wakeup from suspend source
771 * @num_ct: Number of available irq_chip_type instances (usually 1)
772 * @private: Private data for non generic chip callbacks
773 * @installed: bitfield to denote installed interrupts
774 * @unused: bitfield to denote unused interrupts
775 * @domain: irq domain pointer
776 * @list: List head for keeping track of instances
777 * @chip_types: Array of interrupt irq_chip_types
778 *
779 * Note, that irq_chip_generic can have multiple irq_chip_type
780 * implementations which can be associated to a particular irq line of
781 * an irq_chip_generic instance. That allows to share and protect
782 * state in an irq_chip_generic instance when we need to implement
783 * different flow mechanisms (level/edge) for it.
784 */
785 struct irq_chip_generic {
786 raw_spinlock_t lock;
787 void __iomem *reg_base;
788 u32 (*reg_readl)(void __iomem *addr);
789 void (*reg_writel)(u32 val, void __iomem *addr);
790 unsigned int irq_base;
791 unsigned int irq_cnt;
792 u32 mask_cache;
793 u32 type_cache;
794 u32 polarity_cache;
795 u32 wake_enabled;
796 u32 wake_active;
797 unsigned int num_ct;
798 void *private;
799 unsigned long installed;
800 unsigned long unused;
801 struct irq_domain *domain;
802 struct list_head list;
803 struct irq_chip_type chip_types[0];
804 };
805
806 /**
807 * enum irq_gc_flags - Initialization flags for generic irq chips
808 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
809 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
810 * irq chips which need to call irq_set_wake() on
811 * the parent irq. Usually GPIO implementations
812 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
813 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
814 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
815 */
816 enum irq_gc_flags {
817 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
818 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
819 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
820 IRQ_GC_NO_MASK = 1 << 3,
821 IRQ_GC_BE_IO = 1 << 4,
822 };
823
824 /*
825 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
826 * @irqs_per_chip: Number of interrupts per chip
827 * @num_chips: Number of chips
828 * @irq_flags_to_set: IRQ* flags to set on irq setup
829 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
830 * @gc_flags: Generic chip specific setup flags
831 * @gc: Array of pointers to generic interrupt chips
832 */
833 struct irq_domain_chip_generic {
834 unsigned int irqs_per_chip;
835 unsigned int num_chips;
836 unsigned int irq_flags_to_clear;
837 unsigned int irq_flags_to_set;
838 enum irq_gc_flags gc_flags;
839 struct irq_chip_generic *gc[0];
840 };
841
842 /* Generic chip callback functions */
843 void irq_gc_noop(struct irq_data *d);
844 void irq_gc_mask_disable_reg(struct irq_data *d);
845 void irq_gc_mask_set_bit(struct irq_data *d);
846 void irq_gc_mask_clr_bit(struct irq_data *d);
847 void irq_gc_unmask_enable_reg(struct irq_data *d);
848 void irq_gc_ack_set_bit(struct irq_data *d);
849 void irq_gc_ack_clr_bit(struct irq_data *d);
850 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
851 void irq_gc_eoi(struct irq_data *d);
852 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
853
854 /* Setup functions for irq_chip_generic */
855 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
856 irq_hw_number_t hw_irq);
857 struct irq_chip_generic *
858 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
859 void __iomem *reg_base, irq_flow_handler_t handler);
860 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
861 enum irq_gc_flags flags, unsigned int clr,
862 unsigned int set);
863 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
864 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
865 unsigned int clr, unsigned int set);
866
867 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
868 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
869 int num_ct, const char *name,
870 irq_flow_handler_t handler,
871 unsigned int clr, unsigned int set,
872 enum irq_gc_flags flags);
873
874
875 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
876 {
877 return container_of(d->chip, struct irq_chip_type, chip);
878 }
879
880 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
881
882 #ifdef CONFIG_SMP
883 static inline void irq_gc_lock(struct irq_chip_generic *gc)
884 {
885 raw_spin_lock(&gc->lock);
886 }
887
888 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
889 {
890 raw_spin_unlock(&gc->lock);
891 }
892 #else
893 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
894 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
895 #endif
896
897 static inline void irq_reg_writel(struct irq_chip_generic *gc,
898 u32 val, int reg_offset)
899 {
900 if (gc->reg_writel)
901 gc->reg_writel(val, gc->reg_base + reg_offset);
902 else
903 writel(val, gc->reg_base + reg_offset);
904 }
905
906 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
907 int reg_offset)
908 {
909 if (gc->reg_readl)
910 return gc->reg_readl(gc->reg_base + reg_offset);
911 else
912 return readl(gc->reg_base + reg_offset);
913 }
914
915 #endif /* _LINUX_IRQ_H */
Linux kernel - Deliverables
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