2 * Definitions for the ST M41T00 family of i2c rtc chips.
4 * Author: Mark A. Greer <mgreer@mvista.com>
6 * 2005, 2006 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
15 #define M41T00_DRV_NAME "m41t00"
16 #define M41T00_I2C_ADDR 0x68
18 #define M41T00_TYPE_M41T00 0
19 #define M41T00_TYPE_M41T81 81
20 #define M41T00_TYPE_M41T85 85
22 struct m41t00_platform_data
{
28 /* SQW output disabled, this is default value by power on */
29 #define M41T00_SQW_DISABLE (0)
31 #define M41T00_SQW_32KHZ (1<<4) /* 32.768 KHz */
32 #define M41T00_SQW_8KHZ (2<<4) /* 8.192 KHz */
33 #define M41T00_SQW_4KHZ (3<<4) /* 4.096 KHz */
34 #define M41T00_SQW_2KHZ (4<<4) /* 2.048 KHz */
35 #define M41T00_SQW_1KHZ (5<<4) /* 1.024 KHz */
36 #define M41T00_SQW_512HZ (6<<4) /* 512 Hz */
37 #define M41T00_SQW_256HZ (7<<4) /* 256 Hz */
38 #define M41T00_SQW_128HZ (8<<4) /* 128 Hz */
39 #define M41T00_SQW_64HZ (9<<4) /* 64 Hz */
40 #define M41T00_SQW_32HZ (10<<4) /* 32 Hz */
41 #define M41T00_SQW_16HZ (11<<4) /* 16 Hz */
42 #define M41T00_SQW_8HZ (12<<4) /* 8 Hz */
43 #define M41T00_SQW_4HZ (13<<4) /* 4 Hz */
44 #define M41T00_SQW_2HZ (14<<4) /* 2 Hz */
45 #define M41T00_SQW_1HZ (15<<4) /* 1 Hz */
47 extern ulong
m41t00_get_rtc_time(void);
48 extern int m41t00_set_rtc_time(ulong nowtime
);
50 #endif /* _M41T00_H */
This page took 0.039003 seconds and 5 git commands to generate.