include/linux/mfd/arizona/pdata.h

   1 /*
   2  * Platform data for Arizona devices
   3  *
   4  * Copyright 2012 Wolfson Microelectronics. PLC.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef _ARIZONA_PDATA_H
  12 #define _ARIZONA_PDATA_H
  13
  14 #define ARIZONA_GPN_DIR                          0x8000  /* GPN_DIR */
  15 #define ARIZONA_GPN_DIR_MASK                     0x8000  /* GPN_DIR */
  16 #define ARIZONA_GPN_DIR_SHIFT                        15  /* GPN_DIR */
  17 #define ARIZONA_GPN_DIR_WIDTH                         1  /* GPN_DIR */
  18 #define ARIZONA_GPN_PU                           0x4000  /* GPN_PU */
  19 #define ARIZONA_GPN_PU_MASK                      0x4000  /* GPN_PU */
  20 #define ARIZONA_GPN_PU_SHIFT                         14  /* GPN_PU */
  21 #define ARIZONA_GPN_PU_WIDTH                          1  /* GPN_PU */
  22 #define ARIZONA_GPN_PD                           0x2000  /* GPN_PD */
  23 #define ARIZONA_GPN_PD_MASK                      0x2000  /* GPN_PD */
  24 #define ARIZONA_GPN_PD_SHIFT                         13  /* GPN_PD */
  25 #define ARIZONA_GPN_PD_WIDTH                          1  /* GPN_PD */
  26 #define ARIZONA_GPN_LVL                          0x0800  /* GPN_LVL */
  27 #define ARIZONA_GPN_LVL_MASK                     0x0800  /* GPN_LVL */
  28 #define ARIZONA_GPN_LVL_SHIFT                        11  /* GPN_LVL */
  29 #define ARIZONA_GPN_LVL_WIDTH                         1  /* GPN_LVL */
  30 #define ARIZONA_GPN_POL                          0x0400  /* GPN_POL */
  31 #define ARIZONA_GPN_POL_MASK                     0x0400  /* GPN_POL */
  32 #define ARIZONA_GPN_POL_SHIFT                        10  /* GPN_POL */
  33 #define ARIZONA_GPN_POL_WIDTH                         1  /* GPN_POL */
  34 #define ARIZONA_GPN_OP_CFG                       0x0200  /* GPN_OP_CFG */
  35 #define ARIZONA_GPN_OP_CFG_MASK                  0x0200  /* GPN_OP_CFG */
  36 #define ARIZONA_GPN_OP_CFG_SHIFT                      9  /* GPN_OP_CFG */
  37 #define ARIZONA_GPN_OP_CFG_WIDTH                      1  /* GPN_OP_CFG */
  38 #define ARIZONA_GPN_DB                           0x0100  /* GPN_DB */
  39 #define ARIZONA_GPN_DB_MASK                      0x0100  /* GPN_DB */
  40 #define ARIZONA_GPN_DB_SHIFT                          8  /* GPN_DB */
  41 #define ARIZONA_GPN_DB_WIDTH                          1  /* GPN_DB */
  42 #define ARIZONA_GPN_FN_MASK                      0x007F  /* GPN_FN - [6:0] */
  43 #define ARIZONA_GPN_FN_SHIFT                          0  /* GPN_FN - [6:0] */
  44 #define ARIZONA_GPN_FN_WIDTH                          7  /* GPN_FN - [6:0] */
  45
  46 #define ARIZONA_MAX_GPIO 5
  47
  48 #define ARIZONA_32KZ_MCLK1 1
  49 #define ARIZONA_32KZ_MCLK2 2
  50 #define ARIZONA_32KZ_NONE  3
  51
  52 #define ARIZONA_MAX_INPUT 4
  53
  54 #define ARIZONA_DMIC_MICVDD   0
  55 #define ARIZONA_DMIC_MICBIAS1 1
  56 #define ARIZONA_DMIC_MICBIAS2 2
  57 #define ARIZONA_DMIC_MICBIAS3 3
  58
  59 #define ARIZONA_INMODE_DIFF 0
  60 #define ARIZONA_INMODE_SE   1
  61 #define ARIZONA_INMODE_DMIC 2
  62
  63 #define ARIZONA_MAX_OUTPUT 6
  64
  65 #define ARIZONA_MAX_AIF 3
  66
  67 #define ARIZONA_HAP_ACT_ERM 0
  68 #define ARIZONA_HAP_ACT_LRA 2
  69
  70 #define ARIZONA_MAX_PDM_SPK 2
  71
  72 struct regulator_init_data;
  73
  74 struct arizona_micd_config {
  75         unsigned int src;
  76         unsigned int bias;
  77         bool gpio;
  78 };
  79
  80 struct arizona_pdata {
  81         int reset;      /** GPIO controlling /RESET, if any */
  82         int ldoena;     /** GPIO controlling LODENA, if any */
  83
  84         /** Regulator configuration for MICVDD */
  85         struct regulator_init_data *micvdd;
  86
  87         /** Regulator configuration for LDO1 */
  88         struct regulator_init_data *ldo1;
  89
  90         /** If a direct 32kHz clock is provided on an MCLK specify it here */
  91         int clk32k_src;
  92
  93         bool irq_active_high; /** IRQ polarity */
  94
  95         /* Base GPIO */
  96         int gpio_base;
  97
  98         /** Pin state for GPIO pins */
  99         int gpio_defaults[ARIZONA_MAX_GPIO];
 100
 101         /**
 102          * Maximum number of channels clocks will be generated for,
 103          * useful for systems where and I2S bus with multiple data
 104          * lines is mastered.
 105          */
 106         int max_channels_clocked[ARIZONA_MAX_AIF];
 107
 108         /** GPIO for mic detection polarity */
 109         int micd_pol_gpio;
 110
 111         /** Headset polarity configurations */
 112         struct arizona_micd_config *micd_configs;
 113         int num_micd_configs;
 114
 115         /** Reference voltage for DMIC inputs */
 116         int dmic_ref[ARIZONA_MAX_INPUT];
 117
 118         /** Mode of input structures */
 119         int inmode[ARIZONA_MAX_INPUT];
 120
 121         /** Mode for outputs */
 122         bool out_mono[ARIZONA_MAX_OUTPUT];
 123
 124         /** PDM speaker mute setting */
 125         unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
 126
 127         /** PDM speaker format */
 128         unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
 129
 130         /** Haptic actuator type */
 131         unsigned int hap_act;
 132 };
 133
 134 #endif