2 * Copyright (C) ST Ericsson SA 2011
4 * License Terms: GNU General Public License v2
11 #include <linux/interrupt.h>
12 #include <linux/notifier.h>
13 #include <linux/err.h>
15 /* PRCMU Wakeup defines */
16 enum prcmu_wakeup_index
{
17 PRCMU_WAKEUP_INDEX_RTC
,
18 PRCMU_WAKEUP_INDEX_RTT0
,
19 PRCMU_WAKEUP_INDEX_RTT1
,
20 PRCMU_WAKEUP_INDEX_HSI0
,
21 PRCMU_WAKEUP_INDEX_HSI1
,
22 PRCMU_WAKEUP_INDEX_USB
,
23 PRCMU_WAKEUP_INDEX_ABB
,
24 PRCMU_WAKEUP_INDEX_ABB_FIFO
,
25 PRCMU_WAKEUP_INDEX_ARM
,
26 PRCMU_WAKEUP_INDEX_CD_IRQ
,
27 NUM_PRCMU_WAKEUP_INDICES
29 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
31 /* EPOD (power domain) IDs */
35 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39 * - EPOD_ID_SGA: power domain for SGA
40 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43 * - NUM_EPOD_ID: number of power domains
45 * TODO: These should be prefixed.
47 #define EPOD_ID_SVAMMDSP 0
48 #define EPOD_ID_SVAPIPE 1
49 #define EPOD_ID_SIAMMDSP 2
50 #define EPOD_ID_SIAPIPE 3
52 #define EPOD_ID_B2R2_MCDE 5
53 #define EPOD_ID_ESRAM12 6
54 #define EPOD_ID_ESRAM34 7
58 * state definition for EPOD (power domain)
59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
60 * - EPOD_STATE_OFF: The EPOD is switched off
61 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
63 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
64 * - EPOD_STATE_ON: Same as above, but with clock enabled
66 #define EPOD_STATE_NO_CHANGE 0x00
67 #define EPOD_STATE_OFF 0x01
68 #define EPOD_STATE_RAMRET 0x02
69 #define EPOD_STATE_ON_CLK_OFF 0x03
70 #define EPOD_STATE_ON 0x04
75 #define PRCMU_CLKSRC_CLK38M 0x00
76 #define PRCMU_CLKSRC_ACLK 0x01
77 #define PRCMU_CLKSRC_SYSCLK 0x02
78 #define PRCMU_CLKSRC_LCDCLK 0x03
79 #define PRCMU_CLKSRC_SDMMCCLK 0x04
80 #define PRCMU_CLKSRC_TVCLK 0x05
81 #define PRCMU_CLKSRC_TIMCLK 0x06
82 #define PRCMU_CLKSRC_CLK009 0x07
83 /* These are only valid for CLKOUT1: */
84 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
85 #define PRCMU_CLKSRC_I2CCLK 0x41
86 #define PRCMU_CLKSRC_MSP02CLK 0x42
87 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
88 #define PRCMU_CLKSRC_HSIRXCLK 0x44
89 #define PRCMU_CLKSRC_HSITXCLK 0x45
90 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
91 #define PRCMU_CLKSRC_HDMICLK 0x47
133 PRCMU_NUM_REG_CLOCKS
,
134 PRCMU_SYSCLK
= PRCMU_NUM_REG_CLOCKS
,
150 * enum ape_opp - APE OPP states definition
152 * @APE_NO_CHANGE: The APE operating point is unchanged
153 * @APE_100_OPP: The new APE operating point is ape100opp
155 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
159 APE_NO_CHANGE
= 0x01,
162 APE_50_PARTLY_25_OPP
= 0xFF,
166 * enum arm_opp - ARM OPP states definition
168 * @ARM_NO_CHANGE: The ARM operating point is unchanged
169 * @ARM_100_OPP: The new ARM operating point is arm100opp
170 * @ARM_50_OPP: The new ARM operating point is arm50opp
171 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
172 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
173 * @ARM_EXTCLK: The new ARM operating point is armExtClk
177 ARM_NO_CHANGE
= 0x01,
181 ARM_MAX_FREQ100OPP
= 0x05,
186 * enum ddr_opp - DDR OPP states definition
187 * @DDR_100_OPP: The new DDR operating point is ddr100opp
188 * @DDR_50_OPP: The new DDR operating point is ddr50opp
189 * @DDR_25_OPP: The new DDR operating point is ddr25opp
198 * Definitions for controlling ESRAM0 in deep sleep.
200 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
201 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
204 * enum ddr_pwrst - DDR power states definition
205 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
207 * @DDR_PWR_STATE_OFFLOWLAT:
208 * @DDR_PWR_STATE_OFFHIGHLAT:
211 DDR_PWR_STATE_UNCHANGED
= 0x00,
212 DDR_PWR_STATE_ON
= 0x01,
213 DDR_PWR_STATE_OFFLOWLAT
= 0x02,
214 DDR_PWR_STATE_OFFHIGHLAT
= 0x03
217 #include <linux/mfd/db8500-prcmu.h>
219 #if defined(CONFIG_UX500_SOC_DB8500)
223 static inline void __init
prcmu_early_init(void)
225 return db8500_prcmu_early_init();
228 static inline int prcmu_set_power_state(u8 state
, bool keep_ulp_clk
,
231 return db8500_prcmu_set_power_state(state
, keep_ulp_clk
,
235 static inline u8
prcmu_get_power_state_result(void)
237 return db8500_prcmu_get_power_state_result();
240 static inline int prcmu_gic_decouple(void)
242 return db8500_prcmu_gic_decouple();
245 static inline int prcmu_gic_recouple(void)
247 return db8500_prcmu_gic_recouple();
250 static inline bool prcmu_gic_pending_irq(void)
252 return db8500_prcmu_gic_pending_irq();
255 static inline bool prcmu_is_cpu_in_wfi(int cpu
)
257 return db8500_prcmu_is_cpu_in_wfi(cpu
);
260 static inline int prcmu_copy_gic_settings(void)
262 return db8500_prcmu_copy_gic_settings();
265 static inline bool prcmu_pending_irq(void)
267 return db8500_prcmu_pending_irq();
270 static inline int prcmu_set_epod(u16 epod_id
, u8 epod_state
)
272 return db8500_prcmu_set_epod(epod_id
, epod_state
);
275 static inline void prcmu_enable_wakeups(u32 wakeups
)
277 db8500_prcmu_enable_wakeups(wakeups
);
280 static inline void prcmu_disable_wakeups(void)
282 prcmu_enable_wakeups(0);
285 static inline void prcmu_config_abb_event_readout(u32 abb_events
)
287 db8500_prcmu_config_abb_event_readout(abb_events
);
290 static inline void prcmu_get_abb_event_buffer(void __iomem
**buf
)
292 db8500_prcmu_get_abb_event_buffer(buf
);
295 int prcmu_abb_read(u8 slave
, u8 reg
, u8
*value
, u8 size
);
296 int prcmu_abb_write(u8 slave
, u8 reg
, u8
*value
, u8 size
);
297 int prcmu_abb_write_masked(u8 slave
, u8 reg
, u8
*value
, u8
*mask
, u8 size
);
299 int prcmu_config_clkout(u8 clkout
, u8 source
, u8 div
);
301 static inline int prcmu_request_clock(u8 clock
, bool enable
)
303 return db8500_prcmu_request_clock(clock
, enable
);
306 unsigned long prcmu_clock_rate(u8 clock
);
307 long prcmu_round_clock_rate(u8 clock
, unsigned long rate
);
308 int prcmu_set_clock_rate(u8 clock
, unsigned long rate
);
310 static inline int prcmu_set_ddr_opp(u8 opp
)
312 return db8500_prcmu_set_ddr_opp(opp
);
314 static inline int prcmu_get_ddr_opp(void)
316 return db8500_prcmu_get_ddr_opp();
319 static inline int prcmu_set_arm_opp(u8 opp
)
321 return db8500_prcmu_set_arm_opp(opp
);
324 static inline int prcmu_get_arm_opp(void)
326 return db8500_prcmu_get_arm_opp();
329 static inline int prcmu_set_ape_opp(u8 opp
)
331 return db8500_prcmu_set_ape_opp(opp
);
334 static inline int prcmu_get_ape_opp(void)
336 return db8500_prcmu_get_ape_opp();
339 static inline int prcmu_request_ape_opp_100_voltage(bool enable
)
341 return db8500_prcmu_request_ape_opp_100_voltage(enable
);
344 static inline void prcmu_system_reset(u16 reset_code
)
346 return db8500_prcmu_system_reset(reset_code
);
349 static inline u16
prcmu_get_reset_code(void)
351 return db8500_prcmu_get_reset_code();
354 int prcmu_ac_wake_req(void);
355 void prcmu_ac_sleep_req(void);
356 static inline void prcmu_modem_reset(void)
358 return db8500_prcmu_modem_reset();
361 static inline bool prcmu_is_ac_wake_requested(void)
363 return db8500_prcmu_is_ac_wake_requested();
366 static inline int prcmu_set_display_clocks(void)
368 return db8500_prcmu_set_display_clocks();
371 static inline int prcmu_disable_dsipll(void)
373 return db8500_prcmu_disable_dsipll();
376 static inline int prcmu_enable_dsipll(void)
378 return db8500_prcmu_enable_dsipll();
381 static inline int prcmu_config_esram0_deep_sleep(u8 state
)
383 return db8500_prcmu_config_esram0_deep_sleep(state
);
386 static inline int prcmu_config_hotdog(u8 threshold
)
388 return db8500_prcmu_config_hotdog(threshold
);
391 static inline int prcmu_config_hotmon(u8 low
, u8 high
)
393 return db8500_prcmu_config_hotmon(low
, high
);
396 static inline int prcmu_start_temp_sense(u16 cycles32k
)
398 return db8500_prcmu_start_temp_sense(cycles32k
);
401 static inline int prcmu_stop_temp_sense(void)
403 return db8500_prcmu_stop_temp_sense();
406 static inline u32
prcmu_read(unsigned int reg
)
408 return db8500_prcmu_read(reg
);
411 static inline void prcmu_write(unsigned int reg
, u32 value
)
413 db8500_prcmu_write(reg
, value
);
416 static inline void prcmu_write_masked(unsigned int reg
, u32 mask
, u32 value
)
418 db8500_prcmu_write_masked(reg
, mask
, value
);
421 static inline int prcmu_enable_a9wdog(u8 id
)
423 return db8500_prcmu_enable_a9wdog(id
);
426 static inline int prcmu_disable_a9wdog(u8 id
)
428 return db8500_prcmu_disable_a9wdog(id
);
431 static inline int prcmu_kick_a9wdog(u8 id
)
433 return db8500_prcmu_kick_a9wdog(id
);
436 static inline int prcmu_load_a9wdog(u8 id
, u32 timeout
)
438 return db8500_prcmu_load_a9wdog(id
, timeout
);
441 static inline int prcmu_config_a9wdog(u8 num
, bool sleep_auto_off
)
443 return db8500_prcmu_config_a9wdog(num
, sleep_auto_off
);
447 static inline void __init
prcmu_early_init(void) {}
449 static inline int prcmu_set_power_state(u8 state
, bool keep_ulp_clk
,
455 static inline int prcmu_set_epod(u16 epod_id
, u8 epod_state
)
460 static inline void prcmu_enable_wakeups(u32 wakeups
) {}
462 static inline void prcmu_disable_wakeups(void) {}
464 static inline int prcmu_abb_read(u8 slave
, u8 reg
, u8
*value
, u8 size
)
469 static inline int prcmu_abb_write(u8 slave
, u8 reg
, u8
*value
, u8 size
)
474 static inline int prcmu_abb_write_masked(u8 slave
, u8 reg
, u8
*value
, u8
*mask
,
480 static inline int prcmu_config_clkout(u8 clkout
, u8 source
, u8 div
)
485 static inline int prcmu_request_clock(u8 clock
, bool enable
)
490 static inline long prcmu_round_clock_rate(u8 clock
, unsigned long rate
)
495 static inline int prcmu_set_clock_rate(u8 clock
, unsigned long rate
)
500 static inline unsigned long prcmu_clock_rate(u8 clock
)
505 static inline int prcmu_set_ape_opp(u8 opp
)
510 static inline int prcmu_get_ape_opp(void)
515 static inline int prcmu_request_ape_opp_100_voltage(bool enable
)
520 static inline int prcmu_set_arm_opp(u8 opp
)
525 static inline int prcmu_get_arm_opp(void)
530 static inline int prcmu_set_ddr_opp(u8 opp
)
535 static inline int prcmu_get_ddr_opp(void)
540 static inline void prcmu_system_reset(u16 reset_code
) {}
542 static inline u16
prcmu_get_reset_code(void)
547 static inline int prcmu_ac_wake_req(void)
552 static inline void prcmu_ac_sleep_req(void) {}
554 static inline void prcmu_modem_reset(void) {}
556 static inline bool prcmu_is_ac_wake_requested(void)
561 static inline int prcmu_set_display_clocks(void)
566 static inline int prcmu_disable_dsipll(void)
571 static inline int prcmu_enable_dsipll(void)
576 static inline int prcmu_config_esram0_deep_sleep(u8 state
)
581 static inline void prcmu_config_abb_event_readout(u32 abb_events
) {}
583 static inline void prcmu_get_abb_event_buffer(void __iomem
**buf
)
588 static inline int prcmu_config_hotdog(u8 threshold
)
593 static inline int prcmu_config_hotmon(u8 low
, u8 high
)
598 static inline int prcmu_start_temp_sense(u16 cycles32k
)
603 static inline int prcmu_stop_temp_sense(void)
608 static inline u32
prcmu_read(unsigned int reg
)
613 static inline void prcmu_write(unsigned int reg
, u32 value
) {}
615 static inline void prcmu_write_masked(unsigned int reg
, u32 mask
, u32 value
) {}
619 static inline void prcmu_set(unsigned int reg
, u32 bits
)
621 prcmu_write_masked(reg
, bits
, bits
);
624 static inline void prcmu_clear(unsigned int reg
, u32 bits
)
626 prcmu_write_masked(reg
, bits
, 0);
629 #if defined(CONFIG_UX500_SOC_DB8500)
632 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
634 static inline void prcmu_enable_spi2(void)
637 prcmu_set(DB8500_PRCM_GPIOCR
, DB8500_PRCM_GPIOCR_SPI2_SELECT
);
641 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
643 static inline void prcmu_disable_spi2(void)
646 prcmu_clear(DB8500_PRCM_GPIOCR
, DB8500_PRCM_GPIOCR_SPI2_SELECT
);
650 * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
651 * and UARTMOD on OtherAlternateC3.
653 static inline void prcmu_enable_stm_mod_uart(void)
655 if (cpu_is_u8500()) {
656 prcmu_set(DB8500_PRCM_GPIOCR
,
657 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1
|
658 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0
));
663 * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
664 * and UARTMOD on OtherAlternateC3.
666 static inline void prcmu_disable_stm_mod_uart(void)
668 if (cpu_is_u8500()) {
669 prcmu_clear(DB8500_PRCM_GPIOCR
,
670 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1
|
671 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0
));
676 * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
678 static inline void prcmu_enable_stm_ape(void)
680 if (cpu_is_u8500()) {
681 prcmu_set(DB8500_PRCM_GPIOCR
,
682 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD
);
687 * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
689 static inline void prcmu_disable_stm_ape(void)
691 if (cpu_is_u8500()) {
692 prcmu_clear(DB8500_PRCM_GPIOCR
,
693 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD
);
699 static inline void prcmu_enable_spi2(void) {}
700 static inline void prcmu_disable_spi2(void) {}
701 static inline void prcmu_enable_stm_mod_uart(void) {}
702 static inline void prcmu_disable_stm_mod_uart(void) {}
703 static inline void prcmu_enable_stm_ape(void) {}
704 static inline void prcmu_disable_stm_ape(void) {}
708 /* PRCMU QoS APE OPP class */
709 #define PRCMU_QOS_APE_OPP 1
710 #define PRCMU_QOS_DDR_OPP 2
711 #define PRCMU_QOS_ARM_OPP 3
712 #define PRCMU_QOS_DEFAULT_VALUE -1
714 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER
716 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
717 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
718 void prcmu_qos_force_opp(int, s32
);
719 int prcmu_qos_requirement(int pm_qos_class
);
720 int prcmu_qos_add_requirement(int pm_qos_class
, char *name
, s32 value
);
721 int prcmu_qos_update_requirement(int pm_qos_class
, char *name
, s32 new_value
);
722 void prcmu_qos_remove_requirement(int pm_qos_class
, char *name
);
723 int prcmu_qos_add_notifier(int prcmu_qos_class
,
724 struct notifier_block
*notifier
);
725 int prcmu_qos_remove_notifier(int prcmu_qos_class
,
726 struct notifier_block
*notifier
);
730 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
735 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n
) {}
737 static inline void prcmu_qos_force_opp(int prcmu_qos_class
, s32 i
) {}
739 static inline int prcmu_qos_requirement(int prcmu_qos_class
)
744 static inline int prcmu_qos_add_requirement(int prcmu_qos_class
,
745 char *name
, s32 value
)
750 static inline int prcmu_qos_update_requirement(int prcmu_qos_class
,
751 char *name
, s32 new_value
)
756 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class
, char *name
)
760 static inline int prcmu_qos_add_notifier(int prcmu_qos_class
,
761 struct notifier_block
*notifier
)
765 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class
,
766 struct notifier_block
*notifier
)
773 #endif /* __MACH_PRCMU_H */