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[deliverable/linux.git] / include / linux / mlx5 / device.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75 } while (0)
76
77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83 } while (0)
84
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
88
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93 })
94
95 #define MLX5_SET64(typ, p, fld, v) do { \
96 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
97 } while (0)
98
99 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
100
101 #define MLX5_GET64_PR(typ, p, fld) ({ \
102 u64 ___t = MLX5_GET64(typ, p, fld); \
103 pr_debug(#fld " = 0x%llx\n", ___t); \
104 ___t; \
105 })
106
107 /* Big endian getters */
108 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
109 __mlx5_64_off(typ, fld)))
110
111 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
112 type_t tmp; \
113 switch (sizeof(tmp)) { \
114 case sizeof(u8): \
115 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
116 break; \
117 case sizeof(u16): \
118 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
119 break; \
120 case sizeof(u32): \
121 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
122 break; \
123 case sizeof(u64): \
124 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
125 break; \
126 } \
127 tmp; \
128 })
129
130 enum mlx5_inline_modes {
131 MLX5_INLINE_MODE_NONE,
132 MLX5_INLINE_MODE_L2,
133 MLX5_INLINE_MODE_IP,
134 MLX5_INLINE_MODE_TCP_UDP,
135 };
136
137 enum {
138 MLX5_MAX_COMMANDS = 32,
139 MLX5_CMD_DATA_BLOCK_SIZE = 512,
140 MLX5_PCI_CMD_XPORT = 7,
141 MLX5_MKEY_BSF_OCTO_SIZE = 4,
142 MLX5_MAX_PSVS = 4,
143 };
144
145 enum {
146 MLX5_EXTENDED_UD_AV = 0x80000000,
147 };
148
149 enum {
150 MLX5_CQ_STATE_ARMED = 9,
151 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
152 MLX5_CQ_STATE_FIRED = 0xa,
153 };
154
155 enum {
156 MLX5_STAT_RATE_OFFSET = 5,
157 };
158
159 enum {
160 MLX5_INLINE_SEG = 0x80000000,
161 };
162
163 enum {
164 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
165 };
166
167 enum {
168 MLX5_MIN_PKEY_TABLE_SIZE = 128,
169 MLX5_MAX_LOG_PKEY_TABLE = 5,
170 };
171
172 enum {
173 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
174 };
175
176 enum {
177 MLX5_PFAULT_SUBTYPE_WQE = 0,
178 MLX5_PFAULT_SUBTYPE_RDMA = 1,
179 };
180
181 enum {
182 MLX5_PERM_LOCAL_READ = 1 << 2,
183 MLX5_PERM_LOCAL_WRITE = 1 << 3,
184 MLX5_PERM_REMOTE_READ = 1 << 4,
185 MLX5_PERM_REMOTE_WRITE = 1 << 5,
186 MLX5_PERM_ATOMIC = 1 << 6,
187 MLX5_PERM_UMR_EN = 1 << 7,
188 };
189
190 enum {
191 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
192 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
193 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
194 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
195 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
196 };
197
198 enum {
199 MLX5_EN_RD = (u64)1,
200 MLX5_EN_WR = (u64)2
201 };
202
203 enum {
204 MLX5_BF_REGS_PER_PAGE = 4,
205 MLX5_MAX_UAR_PAGES = 1 << 8,
206 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
207 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
208 };
209
210 enum {
211 MLX5_MKEY_MASK_LEN = 1ull << 0,
212 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
213 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
214 MLX5_MKEY_MASK_PD = 1ull << 7,
215 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
216 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
217 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
218 MLX5_MKEY_MASK_KEY = 1ull << 13,
219 MLX5_MKEY_MASK_QPN = 1ull << 14,
220 MLX5_MKEY_MASK_LR = 1ull << 17,
221 MLX5_MKEY_MASK_LW = 1ull << 18,
222 MLX5_MKEY_MASK_RR = 1ull << 19,
223 MLX5_MKEY_MASK_RW = 1ull << 20,
224 MLX5_MKEY_MASK_A = 1ull << 21,
225 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
226 MLX5_MKEY_MASK_FREE = 1ull << 29,
227 };
228
229 enum {
230 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
231
232 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
233 MLX5_UMR_CHECK_FREE = (2 << 5),
234
235 MLX5_UMR_INLINE = (1 << 7),
236 };
237
238 #define MLX5_UMR_MTT_ALIGNMENT 0x40
239 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
240 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
241
242 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
243
244 enum {
245 MLX5_EVENT_QUEUE_TYPE_QP = 0,
246 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
247 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
248 };
249
250 enum mlx5_event {
251 MLX5_EVENT_TYPE_COMP = 0x0,
252
253 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
254 MLX5_EVENT_TYPE_COMM_EST = 0x02,
255 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
256 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
257 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
258
259 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
260 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
261 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
262 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
263 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
264 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
265
266 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
267 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
268 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
269 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
270
271 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
272 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
273
274 MLX5_EVENT_TYPE_CMD = 0x0a,
275 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
276
277 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
278 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
279 };
280
281 enum {
282 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
283 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
284 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
285 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
286 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
287 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
288 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
289 };
290
291 enum {
292 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
293 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
294 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
295 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
296 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
297 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
298 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
299 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
300 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
301 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
302 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
303 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
304 };
305
306 enum {
307 MLX5_ROCE_VERSION_1 = 0,
308 MLX5_ROCE_VERSION_2 = 2,
309 };
310
311 enum {
312 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
313 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
314 };
315
316 enum {
317 MLX5_ROCE_L3_TYPE_IPV4 = 0,
318 MLX5_ROCE_L3_TYPE_IPV6 = 1,
319 };
320
321 enum {
322 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
323 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
324 };
325
326 enum {
327 MLX5_OPCODE_NOP = 0x00,
328 MLX5_OPCODE_SEND_INVAL = 0x01,
329 MLX5_OPCODE_RDMA_WRITE = 0x08,
330 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
331 MLX5_OPCODE_SEND = 0x0a,
332 MLX5_OPCODE_SEND_IMM = 0x0b,
333 MLX5_OPCODE_LSO = 0x0e,
334 MLX5_OPCODE_RDMA_READ = 0x10,
335 MLX5_OPCODE_ATOMIC_CS = 0x11,
336 MLX5_OPCODE_ATOMIC_FA = 0x12,
337 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
338 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
339 MLX5_OPCODE_BIND_MW = 0x18,
340 MLX5_OPCODE_CONFIG_CMD = 0x1f,
341
342 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
343 MLX5_RECV_OPCODE_SEND = 0x01,
344 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
345 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
346
347 MLX5_CQE_OPCODE_ERROR = 0x1e,
348 MLX5_CQE_OPCODE_RESIZE = 0x16,
349
350 MLX5_OPCODE_SET_PSV = 0x20,
351 MLX5_OPCODE_GET_PSV = 0x21,
352 MLX5_OPCODE_CHECK_PSV = 0x22,
353 MLX5_OPCODE_RGET_PSV = 0x26,
354 MLX5_OPCODE_RCHECK_PSV = 0x27,
355
356 MLX5_OPCODE_UMR = 0x25,
357
358 };
359
360 enum {
361 MLX5_SET_PORT_RESET_QKEY = 0,
362 MLX5_SET_PORT_GUID0 = 16,
363 MLX5_SET_PORT_NODE_GUID = 17,
364 MLX5_SET_PORT_SYS_GUID = 18,
365 MLX5_SET_PORT_GID_TABLE = 19,
366 MLX5_SET_PORT_PKEY_TABLE = 20,
367 };
368
369 enum {
370 MLX5_BW_NO_LIMIT = 0,
371 MLX5_100_MBPS_UNIT = 3,
372 MLX5_GBPS_UNIT = 4,
373 };
374
375 enum {
376 MLX5_MAX_PAGE_SHIFT = 31
377 };
378
379 enum {
380 MLX5_ADAPTER_PAGE_SHIFT = 12,
381 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
382 };
383
384 enum {
385 MLX5_CAP_OFF_CMDIF_CSUM = 46,
386 };
387
388 enum {
389 /*
390 * Max wqe size for rdma read is 512 bytes, so this
391 * limits our max_sge_rd as the wqe needs to fit:
392 * - ctrl segment (16 bytes)
393 * - rdma segment (16 bytes)
394 * - scatter elements (16 bytes each)
395 */
396 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
397 };
398
399 enum mlx5_odp_transport_cap_bits {
400 MLX5_ODP_SUPPORT_SEND = 1 << 31,
401 MLX5_ODP_SUPPORT_RECV = 1 << 30,
402 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
403 MLX5_ODP_SUPPORT_READ = 1 << 28,
404 };
405
406 struct mlx5_odp_caps {
407 char reserved[0x10];
408 struct {
409 __be32 rc_odp_caps;
410 __be32 uc_odp_caps;
411 __be32 ud_odp_caps;
412 } per_transport_caps;
413 char reserved2[0xe4];
414 };
415
416 struct mlx5_cmd_layout {
417 u8 type;
418 u8 rsvd0[3];
419 __be32 inlen;
420 __be64 in_ptr;
421 __be32 in[4];
422 __be32 out[4];
423 __be64 out_ptr;
424 __be32 outlen;
425 u8 token;
426 u8 sig;
427 u8 rsvd1;
428 u8 status_own;
429 };
430
431 struct health_buffer {
432 __be32 assert_var[5];
433 __be32 rsvd0[3];
434 __be32 assert_exit_ptr;
435 __be32 assert_callra;
436 __be32 rsvd1[2];
437 __be32 fw_ver;
438 __be32 hw_id;
439 __be32 rsvd2;
440 u8 irisc_index;
441 u8 synd;
442 __be16 ext_synd;
443 };
444
445 struct mlx5_init_seg {
446 __be32 fw_rev;
447 __be32 cmdif_rev_fw_sub;
448 __be32 rsvd0[2];
449 __be32 cmdq_addr_h;
450 __be32 cmdq_addr_l_sz;
451 __be32 cmd_dbell;
452 __be32 rsvd1[120];
453 __be32 initializing;
454 struct health_buffer health;
455 __be32 rsvd2[880];
456 __be32 internal_timer_h;
457 __be32 internal_timer_l;
458 __be32 rsvd3[2];
459 __be32 health_counter;
460 __be32 rsvd4[1019];
461 __be64 ieee1588_clk;
462 __be32 ieee1588_clk_type;
463 __be32 clr_intx;
464 };
465
466 struct mlx5_eqe_comp {
467 __be32 reserved[6];
468 __be32 cqn;
469 };
470
471 struct mlx5_eqe_qp_srq {
472 __be32 reserved1[5];
473 u8 type;
474 u8 reserved2[3];
475 __be32 qp_srq_n;
476 };
477
478 struct mlx5_eqe_cq_err {
479 __be32 cqn;
480 u8 reserved1[7];
481 u8 syndrome;
482 };
483
484 struct mlx5_eqe_port_state {
485 u8 reserved0[8];
486 u8 port;
487 };
488
489 struct mlx5_eqe_gpio {
490 __be32 reserved0[2];
491 __be64 gpio_event;
492 };
493
494 struct mlx5_eqe_congestion {
495 u8 type;
496 u8 rsvd0;
497 u8 congestion_level;
498 };
499
500 struct mlx5_eqe_stall_vl {
501 u8 rsvd0[3];
502 u8 port_vl;
503 };
504
505 struct mlx5_eqe_cmd {
506 __be32 vector;
507 __be32 rsvd[6];
508 };
509
510 struct mlx5_eqe_page_req {
511 u8 rsvd0[2];
512 __be16 func_id;
513 __be32 num_pages;
514 __be32 rsvd1[5];
515 };
516
517 struct mlx5_eqe_page_fault {
518 __be32 bytes_committed;
519 union {
520 struct {
521 u16 reserved1;
522 __be16 wqe_index;
523 u16 reserved2;
524 __be16 packet_length;
525 u8 reserved3[12];
526 } __packed wqe;
527 struct {
528 __be32 r_key;
529 u16 reserved1;
530 __be16 packet_length;
531 __be32 rdma_op_len;
532 __be64 rdma_va;
533 } __packed rdma;
534 } __packed;
535 __be32 flags_qpn;
536 } __packed;
537
538 struct mlx5_eqe_vport_change {
539 u8 rsvd0[2];
540 __be16 vport_num;
541 __be32 rsvd1[6];
542 } __packed;
543
544 union ev_data {
545 __be32 raw[7];
546 struct mlx5_eqe_cmd cmd;
547 struct mlx5_eqe_comp comp;
548 struct mlx5_eqe_qp_srq qp_srq;
549 struct mlx5_eqe_cq_err cq_err;
550 struct mlx5_eqe_port_state port;
551 struct mlx5_eqe_gpio gpio;
552 struct mlx5_eqe_congestion cong;
553 struct mlx5_eqe_stall_vl stall_vl;
554 struct mlx5_eqe_page_req req_pages;
555 struct mlx5_eqe_page_fault page_fault;
556 struct mlx5_eqe_vport_change vport_change;
557 } __packed;
558
559 struct mlx5_eqe {
560 u8 rsvd0;
561 u8 type;
562 u8 rsvd1;
563 u8 sub_type;
564 __be32 rsvd2[7];
565 union ev_data data;
566 __be16 rsvd3;
567 u8 signature;
568 u8 owner;
569 } __packed;
570
571 struct mlx5_cmd_prot_block {
572 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
573 u8 rsvd0[48];
574 __be64 next;
575 __be32 block_num;
576 u8 rsvd1;
577 u8 token;
578 u8 ctrl_sig;
579 u8 sig;
580 };
581
582 enum {
583 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
584 };
585
586 struct mlx5_err_cqe {
587 u8 rsvd0[32];
588 __be32 srqn;
589 u8 rsvd1[18];
590 u8 vendor_err_synd;
591 u8 syndrome;
592 __be32 s_wqe_opcode_qpn;
593 __be16 wqe_counter;
594 u8 signature;
595 u8 op_own;
596 };
597
598 struct mlx5_cqe64 {
599 u8 outer_l3_tunneled;
600 u8 rsvd0;
601 __be16 wqe_id;
602 u8 lro_tcppsh_abort_dupack;
603 u8 lro_min_ttl;
604 __be16 lro_tcp_win;
605 __be32 lro_ack_seq_num;
606 __be32 rss_hash_result;
607 u8 rss_hash_type;
608 u8 ml_path;
609 u8 rsvd20[2];
610 __be16 check_sum;
611 __be16 slid;
612 __be32 flags_rqpn;
613 u8 hds_ip_ext;
614 u8 l4_l3_hdr_type;
615 __be16 vlan_info;
616 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
617 __be32 imm_inval_pkey;
618 u8 rsvd40[4];
619 __be32 byte_cnt;
620 __be32 timestamp_h;
621 __be32 timestamp_l;
622 __be32 sop_drop_qpn;
623 __be16 wqe_counter;
624 u8 signature;
625 u8 op_own;
626 };
627
628 struct mlx5_mini_cqe8 {
629 union {
630 __be32 rx_hash_result;
631 struct {
632 __be16 checksum;
633 __be16 rsvd;
634 };
635 struct {
636 __be16 wqe_counter;
637 u8 s_wqe_opcode;
638 u8 reserved;
639 } s_wqe_info;
640 };
641 __be32 byte_cnt;
642 };
643
644 enum {
645 MLX5_NO_INLINE_DATA,
646 MLX5_INLINE_DATA32_SEG,
647 MLX5_INLINE_DATA64_SEG,
648 MLX5_COMPRESSED,
649 };
650
651 enum {
652 MLX5_CQE_FORMAT_CSUM = 0x1,
653 };
654
655 #define MLX5_MINI_CQE_ARRAY_SIZE 8
656
657 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
658 {
659 return (cqe->op_own >> 2) & 0x3;
660 }
661
662 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
663 {
664 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
665 }
666
667 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
668 {
669 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
670 }
671
672 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
673 {
674 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
675 }
676
677 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
678 {
679 return cqe->outer_l3_tunneled & 0x1;
680 }
681
682 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
683 {
684 return !!(cqe->l4_l3_hdr_type & 0x1);
685 }
686
687 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
688 {
689 u32 hi, lo;
690
691 hi = be32_to_cpu(cqe->timestamp_h);
692 lo = be32_to_cpu(cqe->timestamp_l);
693
694 return (u64)lo | ((u64)hi << 32);
695 }
696
697 struct mpwrq_cqe_bc {
698 __be16 filler_consumed_strides;
699 __be16 byte_cnt;
700 };
701
702 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
703 {
704 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
705
706 return be16_to_cpu(bc->byte_cnt);
707 }
708
709 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
710 {
711 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
712 }
713
714 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
715 {
716 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
717
718 return mpwrq_get_cqe_bc_consumed_strides(bc);
719 }
720
721 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
722 {
723 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
724
725 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
726 }
727
728 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
729 {
730 return be16_to_cpu(cqe->wqe_counter);
731 }
732
733 enum {
734 CQE_L4_HDR_TYPE_NONE = 0x0,
735 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
736 CQE_L4_HDR_TYPE_UDP = 0x2,
737 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
738 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
739 };
740
741 enum {
742 CQE_RSS_HTYPE_IP = 0x3 << 6,
743 CQE_RSS_HTYPE_L4 = 0x3 << 2,
744 };
745
746 enum {
747 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
748 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
749 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
750 };
751
752 enum {
753 CQE_L2_OK = 1 << 0,
754 CQE_L3_OK = 1 << 1,
755 CQE_L4_OK = 1 << 2,
756 };
757
758 struct mlx5_sig_err_cqe {
759 u8 rsvd0[16];
760 __be32 expected_trans_sig;
761 __be32 actual_trans_sig;
762 __be32 expected_reftag;
763 __be32 actual_reftag;
764 __be16 syndrome;
765 u8 rsvd22[2];
766 __be32 mkey;
767 __be64 err_offset;
768 u8 rsvd30[8];
769 __be32 qpn;
770 u8 rsvd38[2];
771 u8 signature;
772 u8 op_own;
773 };
774
775 struct mlx5_wqe_srq_next_seg {
776 u8 rsvd0[2];
777 __be16 next_wqe_index;
778 u8 signature;
779 u8 rsvd1[11];
780 };
781
782 union mlx5_ext_cqe {
783 struct ib_grh grh;
784 u8 inl[64];
785 };
786
787 struct mlx5_cqe128 {
788 union mlx5_ext_cqe inl_grh;
789 struct mlx5_cqe64 cqe64;
790 };
791
792 enum {
793 MLX5_MKEY_STATUS_FREE = 1 << 6,
794 };
795
796 enum {
797 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
798 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
799 MLX5_MKEY_BSF_EN = 1 << 30,
800 MLX5_MKEY_LEN64 = 1 << 31,
801 };
802
803 struct mlx5_mkey_seg {
804 /* This is a two bit field occupying bits 31-30.
805 * bit 31 is always 0,
806 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
807 */
808 u8 status;
809 u8 pcie_control;
810 u8 flags;
811 u8 version;
812 __be32 qpn_mkey7_0;
813 u8 rsvd1[4];
814 __be32 flags_pd;
815 __be64 start_addr;
816 __be64 len;
817 __be32 bsfs_octo_size;
818 u8 rsvd2[16];
819 __be32 xlt_oct_size;
820 u8 rsvd3[3];
821 u8 log2_page_size;
822 u8 rsvd4[4];
823 };
824
825 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
826
827 enum {
828 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
829 };
830
831 enum {
832 VPORT_STATE_DOWN = 0x0,
833 VPORT_STATE_UP = 0x1,
834 };
835
836 enum {
837 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
838 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
839 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
840 };
841
842 enum {
843 MLX5_L3_PROT_TYPE_IPV4 = 0,
844 MLX5_L3_PROT_TYPE_IPV6 = 1,
845 };
846
847 enum {
848 MLX5_L4_PROT_TYPE_TCP = 0,
849 MLX5_L4_PROT_TYPE_UDP = 1,
850 };
851
852 enum {
853 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
854 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
855 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
856 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
857 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
858 };
859
860 enum {
861 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
862 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
863 MLX5_MATCH_INNER_HEADERS = 1 << 2,
864
865 };
866
867 enum {
868 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
869 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
870 };
871
872 enum {
873 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
874 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
875 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
876 };
877
878 enum mlx5_list_type {
879 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
880 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
881 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
882 };
883
884 enum {
885 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
886 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
887 };
888
889 enum mlx5_wol_mode {
890 MLX5_WOL_DISABLE = 0,
891 MLX5_WOL_SECURED_MAGIC = 1 << 1,
892 MLX5_WOL_MAGIC = 1 << 2,
893 MLX5_WOL_ARP = 1 << 3,
894 MLX5_WOL_BROADCAST = 1 << 4,
895 MLX5_WOL_MULTICAST = 1 << 5,
896 MLX5_WOL_UNICAST = 1 << 6,
897 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
898 };
899
900 /* MLX5 DEV CAPs */
901
902 /* TODO: EAT.ME */
903 enum mlx5_cap_mode {
904 HCA_CAP_OPMOD_GET_MAX = 0,
905 HCA_CAP_OPMOD_GET_CUR = 1,
906 };
907
908 enum mlx5_cap_type {
909 MLX5_CAP_GENERAL = 0,
910 MLX5_CAP_ETHERNET_OFFLOADS,
911 MLX5_CAP_ODP,
912 MLX5_CAP_ATOMIC,
913 MLX5_CAP_ROCE,
914 MLX5_CAP_IPOIB_OFFLOADS,
915 MLX5_CAP_EOIB_OFFLOADS,
916 MLX5_CAP_FLOW_TABLE,
917 MLX5_CAP_ESWITCH_FLOW_TABLE,
918 MLX5_CAP_ESWITCH,
919 MLX5_CAP_RESERVED,
920 MLX5_CAP_VECTOR_CALC,
921 MLX5_CAP_QOS,
922 /* NUM OF CAP Types */
923 MLX5_CAP_NUM
924 };
925
926 /* GET Dev Caps macros */
927 #define MLX5_CAP_GEN(mdev, cap) \
928 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
929
930 #define MLX5_CAP_GEN_MAX(mdev, cap) \
931 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
932
933 #define MLX5_CAP_ETH(mdev, cap) \
934 MLX5_GET(per_protocol_networking_offload_caps,\
935 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
936
937 #define MLX5_CAP_ETH_MAX(mdev, cap) \
938 MLX5_GET(per_protocol_networking_offload_caps,\
939 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
940
941 #define MLX5_CAP_ROCE(mdev, cap) \
942 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
943
944 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
945 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
946
947 #define MLX5_CAP_ATOMIC(mdev, cap) \
948 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
949
950 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
951 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
952
953 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
954 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
955
956 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
957 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
958
959 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
960 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
961
962 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
963 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
964
965 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
966 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
967
968 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
969 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
970
971 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
972 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
973
974 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
975 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
976
977 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
978 MLX5_GET(flow_table_eswitch_cap, \
979 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
980
981 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
982 MLX5_GET(flow_table_eswitch_cap, \
983 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
984
985 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
986 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
987
988 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
989 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
990
991 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
992 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
993
994 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
995 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
996
997 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
998 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
999
1000 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1001 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1002
1003 #define MLX5_CAP_ESW(mdev, cap) \
1004 MLX5_GET(e_switch_cap, \
1005 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1006
1007 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1008 MLX5_GET(e_switch_cap, \
1009 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1010
1011 #define MLX5_CAP_ODP(mdev, cap)\
1012 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1013
1014 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1015 MLX5_GET(vector_calc_cap, \
1016 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1017
1018 #define MLX5_CAP_QOS(mdev, cap)\
1019 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1020
1021 enum {
1022 MLX5_CMD_STAT_OK = 0x0,
1023 MLX5_CMD_STAT_INT_ERR = 0x1,
1024 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1025 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1026 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1027 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1028 MLX5_CMD_STAT_RES_BUSY = 0x6,
1029 MLX5_CMD_STAT_LIM_ERR = 0x8,
1030 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1031 MLX5_CMD_STAT_IX_ERR = 0xa,
1032 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1033 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1034 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1035 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1036 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1037 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1038 };
1039
1040 enum {
1041 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1042 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1043 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1044 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1045 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1046 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1047 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1048 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1049 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1050 };
1051
1052 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1053 {
1054 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1055 return 0;
1056 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1057 }
1058
1059 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1060 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1061 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1062 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1063 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1064 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1065
1066 #endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
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