2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/mlx5/device.h>
44 #include <linux/mlx5/doorbell.h>
47 MLX5_BOARD_ID_LEN
= 64,
48 MLX5_MAX_NAME_LEN
= 16,
52 /* one minute for the sake of bringup. Generally, commands must always
53 * complete and we may need to increase this timeout value
55 MLX5_CMD_TIMEOUT_MSEC
= 7200 * 1000,
56 MLX5_CMD_WQ_MAX_NAME
= 32,
62 CMD_STATUS_SUCCESS
= 0,
68 MLX5_SQP_IEEE_1588
= 2,
70 MLX5_SQP_SYNC_UMR
= 4,
78 MLX5_EQ_VEC_PAGES
= 0,
80 MLX5_EQ_VEC_ASYNC
= 2,
81 MLX5_EQ_VEC_COMP_BASE
,
89 MLX5_ATOMIC_MODE_IB_COMP
= 1 << 16,
90 MLX5_ATOMIC_MODE_CX
= 2 << 16,
91 MLX5_ATOMIC_MODE_8B
= 3 << 16,
92 MLX5_ATOMIC_MODE_16B
= 4 << 16,
93 MLX5_ATOMIC_MODE_32B
= 5 << 16,
94 MLX5_ATOMIC_MODE_64B
= 6 << 16,
95 MLX5_ATOMIC_MODE_128B
= 7 << 16,
96 MLX5_ATOMIC_MODE_256B
= 8 << 16,
100 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
101 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
102 MLX5_CMD_OP_INIT_HCA
= 0x102,
103 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
104 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
105 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
106 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
107 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
108 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
110 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
111 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
112 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
113 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
115 MLX5_CMD_OP_CREATE_EQ
= 0x301,
116 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
117 MLX5_CMD_OP_QUERY_EQ
= 0x303,
119 MLX5_CMD_OP_CREATE_CQ
= 0x400,
120 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
121 MLX5_CMD_OP_QUERY_CQ
= 0x402,
122 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
124 MLX5_CMD_OP_CREATE_QP
= 0x500,
125 MLX5_CMD_OP_DESTROY_QP
= 0x501,
126 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
127 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
128 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
129 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
130 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
131 MLX5_CMD_OP_2ERR_QP
= 0x507,
132 MLX5_CMD_OP_RTS2SQD_QP
= 0x508,
133 MLX5_CMD_OP_SQD2RTS_QP
= 0x509,
134 MLX5_CMD_OP_2RST_QP
= 0x50a,
135 MLX5_CMD_OP_QUERY_QP
= 0x50b,
136 MLX5_CMD_OP_CONF_SQP
= 0x50c,
137 MLX5_CMD_OP_MAD_IFC
= 0x50d,
138 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
139 MLX5_CMD_OP_SUSPEND_QP
= 0x50f,
140 MLX5_CMD_OP_UNSUSPEND_QP
= 0x510,
141 MLX5_CMD_OP_SQD2SQD_QP
= 0x511,
142 MLX5_CMD_OP_ALLOC_QP_COUNTER_SET
= 0x512,
143 MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET
= 0x513,
144 MLX5_CMD_OP_QUERY_QP_COUNTER_SET
= 0x514,
146 MLX5_CMD_OP_CREATE_PSV
= 0x600,
147 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
148 MLX5_CMD_OP_QUERY_PSV
= 0x602,
149 MLX5_CMD_OP_QUERY_SIG_RULE_TABLE
= 0x603,
150 MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE
= 0x604,
152 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
153 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
154 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
155 MLX5_CMD_OP_ARM_RQ
= 0x703,
156 MLX5_CMD_OP_RESIZE_SRQ
= 0x704,
158 MLX5_CMD_OP_ALLOC_PD
= 0x800,
159 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
160 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
163 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
164 MLX5_CMD_OP_DETACH_FROM_MCG
= 0x807,
167 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
168 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
170 MLX5_CMD_OP_ACCESS_REG
= 0x805,
171 MLX5_CMD_OP_MAX
= 0x810,
175 MLX5_REG_PCAP
= 0x5001,
176 MLX5_REG_PMTU
= 0x5003,
177 MLX5_REG_PTYS
= 0x5004,
178 MLX5_REG_PAOS
= 0x5006,
179 MLX5_REG_PMAOS
= 0x5012,
180 MLX5_REG_PUDE
= 0x5009,
181 MLX5_REG_PMPE
= 0x5010,
182 MLX5_REG_PELC
= 0x500e,
183 MLX5_REG_PMLP
= 0, /* TBD */
184 MLX5_REG_NODE_DESC
= 0x6001,
185 MLX5_REG_HOST_ENDIANNESS
= 0x7004,
194 struct mlx5_field_desc
{
199 struct mlx5_rsc_debug
{
200 struct mlx5_core_dev
*dev
;
202 enum dbg_rsc_type type
;
204 struct mlx5_field_desc fields
[0];
207 enum mlx5_dev_event
{
208 MLX5_DEV_EVENT_SYS_ERROR
,
209 MLX5_DEV_EVENT_PORT_UP
,
210 MLX5_DEV_EVENT_PORT_DOWN
,
211 MLX5_DEV_EVENT_PORT_INITIALIZED
,
212 MLX5_DEV_EVENT_LID_CHANGE
,
213 MLX5_DEV_EVENT_PKEY_CHANGE
,
214 MLX5_DEV_EVENT_GUID_CHANGE
,
215 MLX5_DEV_EVENT_CLIENT_REREG
,
218 struct mlx5_uuar_info
{
219 struct mlx5_uar
*uars
;
221 int num_low_latency_uuars
;
222 unsigned long *bitmap
;
227 * protect uuar allocation data structs
234 void __iomem
*regreg
;
236 struct mlx5_uar
*uar
;
237 unsigned long offset
;
239 /* protect blue flame buffer selection when needed
243 /* serialize 64 bit writes when done as two 32 bit accesses
249 struct mlx5_cmd_first
{
253 struct mlx5_cmd_msg
{
254 struct list_head list
;
255 struct cache_ent
*cache
;
257 struct mlx5_cmd_first first
;
258 struct mlx5_cmd_mailbox
*next
;
261 struct mlx5_cmd_debug
{
262 struct dentry
*dbg_root
;
263 struct dentry
*dbg_in
;
264 struct dentry
*dbg_out
;
265 struct dentry
*dbg_outlen
;
266 struct dentry
*dbg_status
;
267 struct dentry
*dbg_run
;
276 /* protect block chain allocations
279 struct list_head head
;
282 struct cmd_msg_cache
{
283 struct cache_ent large
;
284 struct cache_ent med
;
288 struct mlx5_cmd_stats
{
293 struct dentry
*count
;
294 /* protect command average calculations */
308 /* protect command queue allocations
310 spinlock_t alloc_lock
;
312 /* protect token allocations
314 spinlock_t token_lock
;
316 unsigned long bitmask
;
317 char wq_name
[MLX5_CMD_WQ_MAX_NAME
];
318 struct workqueue_struct
*wq
;
319 struct semaphore sem
;
320 struct semaphore pages_sem
;
322 struct mlx5_cmd_work_ent
*ent_arr
[MLX5_MAX_COMMANDS
];
323 struct pci_pool
*pool
;
324 struct mlx5_cmd_debug dbg
;
325 struct cmd_msg_cache cache
;
326 int checksum_disabled
;
327 struct mlx5_cmd_stats stats
[MLX5_CMD_OP_MAX
];
330 struct mlx5_port_caps
{
347 u16 stat_rate_support
;
354 int bf_regs_per_page
;
355 struct mlx5_port_caps port
[MLX5_MAX_PORTS
];
356 u8 ext_port_cap
[MLX5_MAX_PORTS
];
359 u8 local_ca_ack_delay
;
365 struct mlx5_cmd_mailbox
{
368 struct mlx5_cmd_mailbox
*next
;
371 struct mlx5_buf_list
{
377 struct mlx5_buf_list direct
;
378 struct mlx5_buf_list
*page_list
;
386 struct mlx5_core_dev
*dev
;
387 __be32 __iomem
*doorbell
;
395 char name
[MLX5_MAX_EQ_NAME
];
396 struct list_head list
;
398 struct mlx5_rsc_debug
*dbg
;
402 struct mlx5_core_mr
{
410 struct mlx5_core_srq
{
414 int max_avail_gather
;
416 void (*event
) (struct mlx5_core_srq
*, enum mlx5_event
);
419 struct completion free
;
422 struct mlx5_eq_table
{
423 void __iomem
*update_ci
;
424 void __iomem
*update_arm_ci
;
425 struct list_head
*comp_eq_head
;
426 struct mlx5_eq pages_eq
;
427 struct mlx5_eq async_eq
;
428 struct mlx5_eq cmd_eq
;
429 struct msix_entry
*msix_arr
;
430 int num_comp_vectors
;
438 struct list_head bf_list
;
439 unsigned free_bf_bmap
;
440 void __iomem
*wc_map
;
445 struct mlx5_core_health
{
446 struct health_buffer __iomem
*health
;
447 __be32 __iomem
*health_counter
;
448 struct timer_list timer
;
449 struct list_head list
;
454 struct mlx5_cq_table
{
455 /* protect radix tree
458 struct radix_tree_root tree
;
461 struct mlx5_qp_table
{
462 /* protect radix tree
465 struct radix_tree_root tree
;
468 struct mlx5_srq_table
{
469 /* protect radix tree
472 struct radix_tree_root tree
;
476 char name
[MLX5_MAX_NAME_LEN
];
477 struct mlx5_eq_table eq_table
;
478 struct mlx5_uuar_info uuari
;
479 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock
);
482 struct workqueue_struct
*pg_wq
;
483 struct rb_root page_root
;
486 struct list_head free_list
;
488 struct mlx5_core_health health
;
490 struct mlx5_srq_table srq_table
;
492 /* start: qp staff */
493 struct mlx5_qp_table qp_table
;
494 struct dentry
*qp_debugfs
;
495 struct dentry
*eq_debugfs
;
496 struct dentry
*cq_debugfs
;
497 struct dentry
*cmdif_debugfs
;
500 /* start: cq staff */
501 struct mlx5_cq_table cq_table
;
504 /* start: alloc staff */
505 struct mutex pgdir_mutex
;
506 struct list_head pgdir_list
;
507 /* end: alloc staff */
508 struct dentry
*dbg_root
;
510 /* protect mkey key part */
511 spinlock_t mkey_lock
;
515 struct mlx5_core_dev
{
516 struct pci_dev
*pdev
;
518 char board_id
[MLX5_BOARD_ID_LEN
];
520 struct mlx5_caps caps
;
521 phys_addr_t iseg_base
;
522 struct mlx5_init_seg __iomem
*iseg
;
523 void (*event
) (struct mlx5_core_dev
*dev
,
524 enum mlx5_dev_event event
,
526 struct mlx5_priv priv
;
527 struct mlx5_profile
*profile
;
534 struct mlx5_db_pgdir
*pgdir
;
535 struct mlx5_ib_user_db_page
*user_page
;
542 MLX5_DB_PER_PAGE
= PAGE_SIZE
/ L1_CACHE_BYTES
,
546 MLX5_COMP_EQ_SIZE
= 1024,
549 struct mlx5_db_pgdir
{
550 struct list_head list
;
551 DECLARE_BITMAP(bitmap
, MLX5_DB_PER_PAGE
);
556 typedef void (*mlx5_cmd_cbk_t
)(int status
, void *context
);
558 struct mlx5_cmd_work_ent
{
559 struct mlx5_cmd_msg
*in
;
560 struct mlx5_cmd_msg
*out
;
563 mlx5_cmd_cbk_t callback
;
566 struct completion done
;
567 struct mlx5_cmd
*cmd
;
568 struct work_struct work
;
569 struct mlx5_cmd_layout
*lay
;
584 static inline void *mlx5_buf_offset(struct mlx5_buf
*buf
, int offset
)
586 if (likely(BITS_PER_LONG
== 64 || buf
->nbufs
== 1))
587 return buf
->direct
.buf
+ offset
;
589 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
590 (offset
& (PAGE_SIZE
- 1));
593 extern struct workqueue_struct
*mlx5_core_wq
;
595 #define STRUCT_FIELD(header, field) \
596 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
597 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
600 size_t struct_offset_bytes
;
601 size_t struct_size_bytes
;
606 static inline struct mlx5_core_dev
*pci2mlx5_core_dev(struct pci_dev
*pdev
)
608 return pci_get_drvdata(pdev
);
611 extern struct dentry
*mlx5_debugfs_root
;
613 static inline u16
fw_rev_maj(struct mlx5_core_dev
*dev
)
615 return ioread32be(&dev
->iseg
->fw_rev
) & 0xffff;
618 static inline u16
fw_rev_min(struct mlx5_core_dev
*dev
)
620 return ioread32be(&dev
->iseg
->fw_rev
) >> 16;
623 static inline u16
fw_rev_sub(struct mlx5_core_dev
*dev
)
625 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) & 0xffff;
628 static inline u16
cmdif_rev(struct mlx5_core_dev
*dev
)
630 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) >> 16;
633 static inline void *mlx5_vzalloc(unsigned long size
)
637 rtn
= kzalloc(size
, GFP_KERNEL
| __GFP_NOWARN
);
643 static inline void mlx5_vfree(const void *addr
)
645 if (addr
&& is_vmalloc_addr(addr
))
651 int mlx5_dev_init(struct mlx5_core_dev
*dev
, struct pci_dev
*pdev
);
652 void mlx5_dev_cleanup(struct mlx5_core_dev
*dev
);
653 int mlx5_cmd_init(struct mlx5_core_dev
*dev
);
654 void mlx5_cmd_cleanup(struct mlx5_core_dev
*dev
);
655 void mlx5_cmd_use_events(struct mlx5_core_dev
*dev
);
656 void mlx5_cmd_use_polling(struct mlx5_core_dev
*dev
);
657 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr
*hdr
);
658 int mlx5_cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
660 int mlx5_cmd_exec_cb(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
661 void *out
, int out_size
, mlx5_cmd_cbk_t callback
,
663 int mlx5_cmd_alloc_uar(struct mlx5_core_dev
*dev
, u32
*uarn
);
664 int mlx5_cmd_free_uar(struct mlx5_core_dev
*dev
, u32 uarn
);
665 int mlx5_alloc_uuars(struct mlx5_core_dev
*dev
, struct mlx5_uuar_info
*uuari
);
666 int mlx5_free_uuars(struct mlx5_core_dev
*dev
, struct mlx5_uuar_info
*uuari
);
667 void mlx5_health_cleanup(void);
668 void __init
mlx5_health_init(void);
669 void mlx5_start_health_poll(struct mlx5_core_dev
*dev
);
670 void mlx5_stop_health_poll(struct mlx5_core_dev
*dev
);
671 int mlx5_buf_alloc(struct mlx5_core_dev
*dev
, int size
, int max_direct
,
672 struct mlx5_buf
*buf
);
673 void mlx5_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_buf
*buf
);
674 struct mlx5_cmd_mailbox
*mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
675 gfp_t flags
, int npages
);
676 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
677 struct mlx5_cmd_mailbox
*head
);
678 int mlx5_core_create_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
679 struct mlx5_create_srq_mbox_in
*in
, int inlen
);
680 int mlx5_core_destroy_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
);
681 int mlx5_core_query_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
682 struct mlx5_query_srq_mbox_out
*out
);
683 int mlx5_core_arm_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
684 u16 lwm
, int is_srq
);
685 int mlx5_core_create_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mr
*mr
,
686 struct mlx5_create_mkey_mbox_in
*in
, int inlen
,
687 mlx5_cmd_cbk_t callback
, void *context
,
688 struct mlx5_create_mkey_mbox_out
*out
);
689 int mlx5_core_destroy_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mr
*mr
);
690 int mlx5_core_query_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mr
*mr
,
691 struct mlx5_query_mkey_mbox_out
*out
, int outlen
);
692 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mr
*mr
,
694 int mlx5_core_alloc_pd(struct mlx5_core_dev
*dev
, u32
*pdn
);
695 int mlx5_core_dealloc_pd(struct mlx5_core_dev
*dev
, u32 pdn
);
696 int mlx5_core_mad_ifc(struct mlx5_core_dev
*dev
, void *inb
, void *outb
,
697 u16 opmod
, int port
);
698 void mlx5_pagealloc_init(struct mlx5_core_dev
*dev
);
699 void mlx5_pagealloc_cleanup(struct mlx5_core_dev
*dev
);
700 int mlx5_pagealloc_start(struct mlx5_core_dev
*dev
);
701 void mlx5_pagealloc_stop(struct mlx5_core_dev
*dev
);
702 void mlx5_core_req_pages_handler(struct mlx5_core_dev
*dev
, u16 func_id
,
704 int mlx5_satisfy_startup_pages(struct mlx5_core_dev
*dev
, int boot
);
705 int mlx5_reclaim_startup_pages(struct mlx5_core_dev
*dev
);
706 void mlx5_register_debugfs(void);
707 void mlx5_unregister_debugfs(void);
708 int mlx5_eq_init(struct mlx5_core_dev
*dev
);
709 void mlx5_eq_cleanup(struct mlx5_core_dev
*dev
);
710 void mlx5_fill_page_array(struct mlx5_buf
*buf
, __be64
*pas
);
711 void mlx5_cq_completion(struct mlx5_core_dev
*dev
, u32 cqn
);
712 void mlx5_qp_event(struct mlx5_core_dev
*dev
, u32 qpn
, int event_type
);
713 void mlx5_srq_event(struct mlx5_core_dev
*dev
, u32 srqn
, int event_type
);
714 struct mlx5_core_srq
*mlx5_core_get_srq(struct mlx5_core_dev
*dev
, u32 srqn
);
715 void mlx5_cmd_comp_handler(struct mlx5_core_dev
*dev
, unsigned long vector
);
716 void mlx5_cq_event(struct mlx5_core_dev
*dev
, u32 cqn
, int event_type
);
717 int mlx5_create_map_eq(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
, u8 vecidx
,
718 int nent
, u64 mask
, const char *name
, struct mlx5_uar
*uar
);
719 int mlx5_destroy_unmap_eq(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
720 int mlx5_start_eqs(struct mlx5_core_dev
*dev
);
721 int mlx5_stop_eqs(struct mlx5_core_dev
*dev
);
722 int mlx5_core_attach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
723 int mlx5_core_detach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
725 int mlx5_qp_debugfs_init(struct mlx5_core_dev
*dev
);
726 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev
*dev
);
727 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
728 int size_in
, void *data_out
, int size_out
,
729 u16 reg_num
, int arg
, int write
);
730 int mlx5_set_port_caps(struct mlx5_core_dev
*dev
, int port_num
, u32 caps
);
732 int mlx5_debug_eq_add(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
733 void mlx5_debug_eq_remove(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
734 int mlx5_core_eq_query(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
,
735 struct mlx5_query_eq_mbox_out
*out
, int outlen
);
736 int mlx5_eq_debugfs_init(struct mlx5_core_dev
*dev
);
737 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev
*dev
);
738 int mlx5_cq_debugfs_init(struct mlx5_core_dev
*dev
);
739 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev
*dev
);
740 int mlx5_db_alloc(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
741 void mlx5_db_free(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
743 const char *mlx5_command_str(int command
);
744 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev
*dev
);
745 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev
*dev
);
747 static inline u32
mlx5_mkey_to_idx(u32 mkey
)
752 static inline u32
mlx5_idx_to_mkey(u32 mkey_idx
)
754 return mkey_idx
<< 8;
757 static inline u8
mlx5_mkey_variant(u32 mkey
)
763 MLX5_PROF_MASK_QP_SIZE
= (u64
)1 << 0,
764 MLX5_PROF_MASK_MR_CACHE
= (u64
)1 << 1,
768 MAX_MR_CACHE_ENTRIES
= 16,
771 struct mlx5_profile
{
777 } mr_cache
[MAX_MR_CACHE_ENTRIES
];
780 #endif /* MLX5_DRIVER_H */