2 * Copyright (c) 2014, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
38 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
39 MLX5_CMD_OP_INIT_HCA
= 0x102,
40 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
41 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
42 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
43 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
44 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
45 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
46 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
47 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
48 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
49 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
50 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
51 MLX5_CMD_OP_CREATE_EQ
= 0x301,
52 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
53 MLX5_CMD_OP_QUERY_EQ
= 0x303,
54 MLX5_CMD_OP_GEN_EQE
= 0x304,
55 MLX5_CMD_OP_CREATE_CQ
= 0x400,
56 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
57 MLX5_CMD_OP_QUERY_CQ
= 0x402,
58 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
59 MLX5_CMD_OP_CREATE_QP
= 0x500,
60 MLX5_CMD_OP_DESTROY_QP
= 0x501,
61 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
62 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
63 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
64 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
65 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
66 MLX5_CMD_OP_2ERR_QP
= 0x507,
67 MLX5_CMD_OP_2RST_QP
= 0x50a,
68 MLX5_CMD_OP_QUERY_QP
= 0x50b,
69 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
70 MLX5_CMD_OP_CREATE_PSV
= 0x600,
71 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
72 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
73 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
74 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
75 MLX5_CMD_OP_ARM_RQ
= 0x703,
76 MLX5_CMD_OP_RESIZE_SRQ
= 0x704,
77 MLX5_CMD_OP_CREATE_DCT
= 0x710,
78 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
79 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
80 MLX5_CMD_OP_QUERY_DCT
= 0x713,
81 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
82 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
83 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
84 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
85 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
86 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
87 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
88 MLX5_CMD_OP_QUERY_RCOE_ADDRESS
= 0x760,
89 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
90 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
91 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
92 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
93 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
94 MLX5_CMD_OP_ALLOC_PD
= 0x800,
95 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
96 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
97 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
98 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
99 MLX5_CMD_OP_ACCESS_REG
= 0x805,
100 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
101 MLX5_CMD_OP_DETACH_FROM_MCG
= 0x807,
102 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
103 MLX5_CMD_OP_MAD_IFC
= 0x50d,
104 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
105 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
106 MLX5_CMD_OP_NOP
= 0x80d,
107 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
108 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
109 MLX5_CMD_OP_SET_BURST_SIZE
= 0x812,
110 MLX5_CMD_OP_QUERY_BURST_SZIE
= 0x813,
111 MLX5_CMD_OP_ACTIVATE_TRACER
= 0x814,
112 MLX5_CMD_OP_DEACTIVATE_TRACER
= 0x815,
113 MLX5_CMD_OP_CREATE_SNIFFER_RULE
= 0x820,
114 MLX5_CMD_OP_DESTROY_SNIFFER_RULE
= 0x821,
115 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x822,
116 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x823,
117 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x824,
118 MLX5_CMD_OP_CREATE_TIR
= 0x900,
119 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
120 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
121 MLX5_CMD_OP_QUERY_TIR
= 0x903,
122 MLX5_CMD_OP_CREATE_TIS
= 0x912,
123 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
124 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
125 MLX5_CMD_OP_QUERY_TIS
= 0x915,
126 MLX5_CMD_OP_CREATE_SQ
= 0x904,
127 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
128 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
129 MLX5_CMD_OP_QUERY_SQ
= 0x907,
130 MLX5_CMD_OP_CREATE_RQ
= 0x908,
131 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
132 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
133 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
134 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
135 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
136 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
137 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
138 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x910,
139 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x911,
140 MLX5_CMD_OP_MAX
= 0x911
143 struct mlx5_ifc_cmd_hca_cap_bits
{
146 u8 log_max_srq_sz
[0x8];
147 u8 log_max_qp_sz
[0x8];
151 u8 log_max_strq_sz
[0x8];
153 u8 log_max_srqs
[0x5];
157 u8 log_max_cq_sz
[0x8];
161 u8 log_max_eq_sz
[0x8];
163 u8 log_max_mkey
[0x6];
167 u8 max_indirection
[0x8];
169 u8 log_max_mrw_sz
[0x7];
171 u8 log_max_bsf_list_size
[0x6];
173 u8 log_max_klm_list_size
[0x6];
176 u8 log_max_ra_req_dc
[0x6];
178 u8 log_max_ra_res_dc
[0x6];
181 u8 log_max_ra_req_qp
[0x6];
183 u8 log_max_ra_res_qp
[0x6];
186 u8 cc_query_allowed
[0x1];
187 u8 cc_modify_allowed
[0x1];
188 u8 reserved_15
[0x1d];
192 u8 pkey_table_size
[0x10];
194 u8 eswitch_owner
[0x1];
196 u8 local_ca_ack_delay
[0x5];
202 u8 reserved_20
[0x18];
204 u8 stat_rate_support
[0x10];
205 u8 reserved_21
[0x10];
207 u8 reserved_22
[0x10];
208 u8 cmdif_checksum
[0x2];
211 u8 wq_signature
[0x1];
212 u8 sctr_data_cqe
[0x1];
225 u8 cq_moderation
[0x1];
226 u8 sniffer_rule_flow
[0x1];
227 u8 sniffer_rule_vport
[0x1];
228 u8 sniffer_rule_phy
[0x1];
252 u8 log_bf_reg_size
[0x5];
253 u8 reserved_34
[0x10];
255 u8 reserved_35
[0x10];
256 u8 max_wqe_sz_sq
[0x10];
258 u8 reserved_36
[0x10];
259 u8 max_wqe_sz_rq
[0x10];
261 u8 reserved_37
[0x10];
262 u8 max_wqe_sz_sq_dc
[0x10];
267 u8 reserved_39
[0x18];
273 u8 log_max_xrcd
[0x5];
275 u8 reserved_42
[0x20];
286 u8 reserved_47
[0x13];
287 u8 log_max_rq_per_tir
[0x5];
289 u8 log_max_tis_per_sq
[0x5];
291 u8 reserved_49
[0xe0];
293 u8 reserved_50
[0x10];
294 u8 log_uar_page_sz
[0x10];
296 u8 reserved_51
[0x100];
298 u8 reserved_52
[0x1f];
301 u8 cqe_zip_timeout
[0x10];
302 u8 cqe_zip_max_num
[0x10];
304 u8 reserved_53
[0x220];
307 struct mlx5_ifc_set_hca_cap_in_bits
{
316 struct mlx5_ifc_cmd_hca_cap_bits hca_capability_struct
;
319 struct mlx5_ifc_query_hca_cap_in_bits
{
329 struct mlx5_ifc_query_hca_cap_out_bits
{
337 u8 capability_struct
[256][0x8];
340 struct mlx5_ifc_set_hca_cap_out_bits
{
349 #endif /* MLX5_IFC_H */