include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 struct device_node;
  30
  31 /* Scan and identify a NAND device */
  32 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  33 /*
  34  * Separate phases of nand_scan(), allowing board driver to intervene
  35  * and override command or ECC setup according to flash type.
  36  */
  37 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  38                            struct nand_flash_dev *table);
  39 extern int nand_scan_tail(struct mtd_info *mtd);
  40
  41 /* Free resources held by the NAND device */
  42 extern void nand_release(struct mtd_info *mtd);
  43
  44 /* Internal helper for board drivers which need to override command function */
  45 extern void nand_wait_ready(struct mtd_info *mtd);
  46
  47 /* locks all blocks present in the device */
  48 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  49
  50 /* unlocks specified locked blocks */
  51 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  52
  53 /* The maximum number of NAND chips in an array */
  54 #define NAND_MAX_CHIPS          8
  55
  56 /*
  57  * Constants for hardware specific CLE/ALE/NCE function
  58  *
  59  * These are bits which can be or'ed to set/clear multiple
  60  * bits in one go.
  61  */
  62 /* Select the chip by setting nCE to low */
  63 #define NAND_NCE                0x01
  64 /* Select the command latch by setting CLE to high */
  65 #define NAND_CLE                0x02
  66 /* Select the address latch by setting ALE to high */
  67 #define NAND_ALE                0x04
  68
  69 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  70 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  71 #define NAND_CTRL_CHANGE        0x80
  72
  73 /*
  74  * Standard NAND flash commands
  75  */
  76 #define NAND_CMD_READ0          0
  77 #define NAND_CMD_READ1          1
  78 #define NAND_CMD_RNDOUT         5
  79 #define NAND_CMD_PAGEPROG       0x10
  80 #define NAND_CMD_READOOB        0x50
  81 #define NAND_CMD_ERASE1         0x60
  82 #define NAND_CMD_STATUS         0x70
  83 #define NAND_CMD_SEQIN          0x80
  84 #define NAND_CMD_RNDIN          0x85
  85 #define NAND_CMD_READID         0x90
  86 #define NAND_CMD_ERASE2         0xd0
  87 #define NAND_CMD_PARAM          0xec
  88 #define NAND_CMD_GET_FEATURES   0xee
  89 #define NAND_CMD_SET_FEATURES   0xef
  90 #define NAND_CMD_RESET          0xff
  91
  92 #define NAND_CMD_LOCK           0x2a
  93 #define NAND_CMD_UNLOCK1        0x23
  94 #define NAND_CMD_UNLOCK2        0x24
  95
  96 /* Extended commands for large page devices */
  97 #define NAND_CMD_READSTART      0x30
  98 #define NAND_CMD_RNDOUTSTART    0xE0
  99 #define NAND_CMD_CACHEDPROG     0x15
 100
 101 #define NAND_CMD_NONE           -1
 102
 103 /* Status bits */
 104 #define NAND_STATUS_FAIL        0x01
 105 #define NAND_STATUS_FAIL_N1     0x02
 106 #define NAND_STATUS_TRUE_READY  0x20
 107 #define NAND_STATUS_READY       0x40
 108 #define NAND_STATUS_WP          0x80
 109
 110 /*
 111  * Constants for ECC_MODES
 112  */
 113 typedef enum {
 114         NAND_ECC_NONE,
 115         NAND_ECC_SOFT,
 116         NAND_ECC_HW,
 117         NAND_ECC_HW_SYNDROME,
 118         NAND_ECC_HW_OOB_FIRST,
 119         NAND_ECC_SOFT_BCH,
 120 } nand_ecc_modes_t;
 121
 122 /*
 123  * Constants for Hardware ECC
 124  */
 125 /* Reset Hardware ECC for read */
 126 #define NAND_ECC_READ           0
 127 /* Reset Hardware ECC for write */
 128 #define NAND_ECC_WRITE          1
 129 /* Enable Hardware ECC before syndrome is read back from flash */
 130 #define NAND_ECC_READSYN        2
 131
 132 /*
 133  * Enable generic NAND 'page erased' check. This check is only done when
 134  * ecc.correct() returns -EBADMSG.
 135  * Set this flag if your implementation does not fix bitflips in erased
 136  * pages and you want to rely on the default implementation.
 137  */
 138 #define NAND_ECC_GENERIC_ERASED_CHECK   BIT(0)
 139
 140 /* Bit mask for flags passed to do_nand_read_ecc */
 141 #define NAND_GET_DEVICE         0x80
 142
 143
 144 /*
 145  * Option constants for bizarre disfunctionality and real
 146  * features.
 147  */
 148 /* Buswidth is 16 bit */
 149 #define NAND_BUSWIDTH_16        0x00000002
 150 /* Chip has cache program function */
 151 #define NAND_CACHEPRG           0x00000008
 152 /*
 153  * Chip requires ready check on read (for auto-incremented sequential read).
 154  * True only for small page devices; large page devices do not support
 155  * autoincrement.
 156  */
 157 #define NAND_NEED_READRDY       0x00000100
 158
 159 /* Chip does not allow subpage writes */
 160 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 161
 162 /* Device is one of 'new' xD cards that expose fake nand command set */
 163 #define NAND_BROKEN_XD          0x00000400
 164
 165 /* Device behaves just like nand, but is readonly */
 166 #define NAND_ROM                0x00000800
 167
 168 /* Device supports subpage reads */
 169 #define NAND_SUBPAGE_READ       0x00001000
 170
 171 /* Options valid for Samsung large page devices */
 172 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 173
 174 /* Macros to identify the above */
 175 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 176 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 177
 178 /* Non chip related options */
 179 /* This option skips the bbt scan during initialization. */
 180 #define NAND_SKIP_BBTSCAN       0x00010000
 181 /*
 182  * This option is defined if the board driver allocates its own buffers
 183  * (e.g. because it needs them DMA-coherent).
 184  */
 185 #define NAND_OWN_BUFFERS        0x00020000
 186 /* Chip may not exist, so silence any errors in scan */
 187 #define NAND_SCAN_SILENT_NODEV  0x00040000
 188 /*
 189  * Autodetect nand buswidth with readid/onfi.
 190  * This suppose the driver will configure the hardware in 8 bits mode
 191  * when calling nand_scan_ident, and update its configuration
 192  * before calling nand_scan_tail.
 193  */
 194 #define NAND_BUSWIDTH_AUTO      0x00080000
 195 /*
 196  * This option could be defined by controller drivers to protect against
 197  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
 198  */
 199 #define NAND_USE_BOUNCE_BUFFER  0x00100000
 200
 201 /* Options set by nand scan */
 202 /* Nand scan has allocated controller struct */
 203 #define NAND_CONTROLLER_ALLOC   0x80000000
 204
 205 /* Cell info constants */
 206 #define NAND_CI_CHIPNR_MSK      0x03
 207 #define NAND_CI_CELLTYPE_MSK    0x0C
 208 #define NAND_CI_CELLTYPE_SHIFT  2
 209
 210 /* Keep gcc happy */
 211 struct nand_chip;
 212
 213 /* ONFI features */
 214 #define ONFI_FEATURE_16_BIT_BUS         (1 << 0)
 215 #define ONFI_FEATURE_EXT_PARAM_PAGE     (1 << 7)
 216
 217 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 218 #define ONFI_TIMING_MODE_0              (1 << 0)
 219 #define ONFI_TIMING_MODE_1              (1 << 1)
 220 #define ONFI_TIMING_MODE_2              (1 << 2)
 221 #define ONFI_TIMING_MODE_3              (1 << 3)
 222 #define ONFI_TIMING_MODE_4              (1 << 4)
 223 #define ONFI_TIMING_MODE_5              (1 << 5)
 224 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 225
 226 /* ONFI feature address */
 227 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 228
 229 /* Vendor-specific feature address (Micron) */
 230 #define ONFI_FEATURE_ADDR_READ_RETRY    0x89
 231
 232 /* ONFI subfeature parameters length */
 233 #define ONFI_SUBFEATURE_PARAM_LEN       4
 234
 235 /* ONFI optional commands SET/GET FEATURES supported? */
 236 #define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
 237
 238 struct nand_onfi_params {
 239         /* rev info and features block */
 240         /* 'O' 'N' 'F' 'I'  */
 241         u8 sig[4];
 242         __le16 revision;
 243         __le16 features;
 244         __le16 opt_cmd;
 245         u8 reserved0[2];
 246         __le16 ext_param_page_length; /* since ONFI 2.1 */
 247         u8 num_of_param_pages;        /* since ONFI 2.1 */
 248         u8 reserved1[17];
 249
 250         /* manufacturer information block */
 251         char manufacturer[12];
 252         char model[20];
 253         u8 jedec_id;
 254         __le16 date_code;
 255         u8 reserved2[13];
 256
 257         /* memory organization block */
 258         __le32 byte_per_page;
 259         __le16 spare_bytes_per_page;
 260         __le32 data_bytes_per_ppage;
 261         __le16 spare_bytes_per_ppage;
 262         __le32 pages_per_block;
 263         __le32 blocks_per_lun;
 264         u8 lun_count;
 265         u8 addr_cycles;
 266         u8 bits_per_cell;
 267         __le16 bb_per_lun;
 268         __le16 block_endurance;
 269         u8 guaranteed_good_blocks;
 270         __le16 guaranteed_block_endurance;
 271         u8 programs_per_page;
 272         u8 ppage_attr;
 273         u8 ecc_bits;
 274         u8 interleaved_bits;
 275         u8 interleaved_ops;
 276         u8 reserved3[13];
 277
 278         /* electrical parameter block */
 279         u8 io_pin_capacitance_max;
 280         __le16 async_timing_mode;
 281         __le16 program_cache_timing_mode;
 282         __le16 t_prog;
 283         __le16 t_bers;
 284         __le16 t_r;
 285         __le16 t_ccs;
 286         __le16 src_sync_timing_mode;
 287         u8 src_ssync_features;
 288         __le16 clk_pin_capacitance_typ;
 289         __le16 io_pin_capacitance_typ;
 290         __le16 input_pin_capacitance_typ;
 291         u8 input_pin_capacitance_max;
 292         u8 driver_strength_support;
 293         __le16 t_int_r;
 294         __le16 t_adl;
 295         u8 reserved4[8];
 296
 297         /* vendor */
 298         __le16 vendor_revision;
 299         u8 vendor[88];
 300
 301         __le16 crc;
 302 } __packed;
 303
 304 #define ONFI_CRC_BASE   0x4F4E
 305
 306 /* Extended ECC information Block Definition (since ONFI 2.1) */
 307 struct onfi_ext_ecc_info {
 308         u8 ecc_bits;
 309         u8 codeword_size;
 310         __le16 bb_per_lun;
 311         __le16 block_endurance;
 312         u8 reserved[2];
 313 } __packed;
 314
 315 #define ONFI_SECTION_TYPE_0     0       /* Unused section. */
 316 #define ONFI_SECTION_TYPE_1     1       /* for additional sections. */
 317 #define ONFI_SECTION_TYPE_2     2       /* for ECC information. */
 318 struct onfi_ext_section {
 319         u8 type;
 320         u8 length;
 321 } __packed;
 322
 323 #define ONFI_EXT_SECTION_MAX 8
 324
 325 /* Extended Parameter Page Definition (since ONFI 2.1) */
 326 struct onfi_ext_param_page {
 327         __le16 crc;
 328         u8 sig[4];             /* 'E' 'P' 'P' 'S' */
 329         u8 reserved0[10];
 330         struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
 331
 332         /*
 333          * The actual size of the Extended Parameter Page is in
 334          * @ext_param_page_length of nand_onfi_params{}.
 335          * The following are the variable length sections.
 336          * So we do not add any fields below. Please see the ONFI spec.
 337          */
 338 } __packed;
 339
 340 struct nand_onfi_vendor_micron {
 341         u8 two_plane_read;
 342         u8 read_cache;
 343         u8 read_unique_id;
 344         u8 dq_imped;
 345         u8 dq_imped_num_settings;
 346         u8 dq_imped_feat_addr;
 347         u8 rb_pulldown_strength;
 348         u8 rb_pulldown_strength_feat_addr;
 349         u8 rb_pulldown_strength_num_settings;
 350         u8 otp_mode;
 351         u8 otp_page_start;
 352         u8 otp_data_prot_addr;
 353         u8 otp_num_pages;
 354         u8 otp_feat_addr;
 355         u8 read_retry_options;
 356         u8 reserved[72];
 357         u8 param_revision;
 358 } __packed;
 359
 360 struct jedec_ecc_info {
 361         u8 ecc_bits;
 362         u8 codeword_size;
 363         __le16 bb_per_lun;
 364         __le16 block_endurance;
 365         u8 reserved[2];
 366 } __packed;
 367
 368 /* JEDEC features */
 369 #define JEDEC_FEATURE_16_BIT_BUS        (1 << 0)
 370
 371 struct nand_jedec_params {
 372         /* rev info and features block */
 373         /* 'J' 'E' 'S' 'D'  */
 374         u8 sig[4];
 375         __le16 revision;
 376         __le16 features;
 377         u8 opt_cmd[3];
 378         __le16 sec_cmd;
 379         u8 num_of_param_pages;
 380         u8 reserved0[18];
 381
 382         /* manufacturer information block */
 383         char manufacturer[12];
 384         char model[20];
 385         u8 jedec_id[6];
 386         u8 reserved1[10];
 387
 388         /* memory organization block */
 389         __le32 byte_per_page;
 390         __le16 spare_bytes_per_page;
 391         u8 reserved2[6];
 392         __le32 pages_per_block;
 393         __le32 blocks_per_lun;
 394         u8 lun_count;
 395         u8 addr_cycles;
 396         u8 bits_per_cell;
 397         u8 programs_per_page;
 398         u8 multi_plane_addr;
 399         u8 multi_plane_op_attr;
 400         u8 reserved3[38];
 401
 402         /* electrical parameter block */
 403         __le16 async_sdr_speed_grade;
 404         __le16 toggle_ddr_speed_grade;
 405         __le16 sync_ddr_speed_grade;
 406         u8 async_sdr_features;
 407         u8 toggle_ddr_features;
 408         u8 sync_ddr_features;
 409         __le16 t_prog;
 410         __le16 t_bers;
 411         __le16 t_r;
 412         __le16 t_r_multi_plane;
 413         __le16 t_ccs;
 414         __le16 io_pin_capacitance_typ;
 415         __le16 input_pin_capacitance_typ;
 416         __le16 clk_pin_capacitance_typ;
 417         u8 driver_strength_support;
 418         __le16 t_adl;
 419         u8 reserved4[36];
 420
 421         /* ECC and endurance block */
 422         u8 guaranteed_good_blocks;
 423         __le16 guaranteed_block_endurance;
 424         struct jedec_ecc_info ecc_info[4];
 425         u8 reserved5[29];
 426
 427         /* reserved */
 428         u8 reserved6[148];
 429
 430         /* vendor */
 431         __le16 vendor_rev_num;
 432         u8 reserved7[88];
 433
 434         /* CRC for Parameter Page */
 435         __le16 crc;
 436 } __packed;
 437
 438 /**
 439  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 440  * @lock:               protection lock
 441  * @active:             the mtd device which holds the controller currently
 442  * @wq:                 wait queue to sleep on if a NAND operation is in
 443  *                      progress used instead of the per chip wait queue
 444  *                      when a hw controller is available.
 445  */
 446 struct nand_hw_control {
 447         spinlock_t lock;
 448         struct nand_chip *active;
 449         wait_queue_head_t wq;
 450 };
 451
 452 /**
 453  * struct nand_ecc_ctrl - Control structure for ECC
 454  * @mode:       ECC mode
 455  * @steps:      number of ECC steps per page
 456  * @size:       data bytes per ECC step
 457  * @bytes:      ECC bytes per step
 458  * @strength:   max number of correctible bits per ECC step
 459  * @total:      total number of ECC bytes per page
 460  * @prepad:     padding information for syndrome based ECC generators
 461  * @postpad:    padding information for syndrome based ECC generators
 462  * @options:    ECC specific options (see NAND_ECC_XXX flags defined above)
 463  * @layout:     ECC layout control struct pointer
 464  * @priv:       pointer to private ECC control data
 465  * @hwctl:      function to control hardware ECC generator. Must only
 466  *              be provided if an hardware ECC is available
 467  * @calculate:  function for ECC calculation or readback from ECC hardware
 468  * @correct:    function for ECC correction, matching to ECC generator (sw/hw).
 469  *              Should return a positive number representing the number of
 470  *              corrected bitflips, -EBADMSG if the number of bitflips exceed
 471  *              ECC strength, or any other error code if the error is not
 472  *              directly related to correction.
 473  *              If -EBADMSG is returned the input buffers should be left
 474  *              untouched.
 475  * @read_page_raw:      function to read a raw page without ECC. This function
 476  *                      should hide the specific layout used by the ECC
 477  *                      controller and always return contiguous in-band and
 478  *                      out-of-band data even if they're not stored
 479  *                      contiguously on the NAND chip (e.g.
 480  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
 481  *                      out-of-band data).
 482  * @write_page_raw:     function to write a raw page without ECC. This function
 483  *                      should hide the specific layout used by the ECC
 484  *                      controller and consider the passed data as contiguous
 485  *                      in-band and out-of-band data. ECC controller is
 486  *                      responsible for doing the appropriate transformations
 487  *                      to adapt to its specific layout (e.g.
 488  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
 489  *                      out-of-band data).
 490  * @read_page:  function to read a page according to the ECC generator
 491  *              requirements; returns maximum number of bitflips corrected in
 492  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 493  * @read_subpage:       function to read parts of the page covered by ECC;
 494  *                      returns same as read_page()
 495  * @write_subpage:      function to write parts of the page covered by ECC.
 496  * @write_page: function to write a page according to the ECC generator
 497  *              requirements.
 498  * @write_oob_raw:      function to write chip OOB data without ECC
 499  * @read_oob_raw:       function to read chip OOB data without ECC
 500  * @read_oob:   function to read chip OOB data
 501  * @write_oob:  function to write chip OOB data
 502  */
 503 struct nand_ecc_ctrl {
 504         nand_ecc_modes_t mode;
 505         int steps;
 506         int size;
 507         int bytes;
 508         int total;
 509         int strength;
 510         int prepad;
 511         int postpad;
 512         unsigned int options;
 513         struct nand_ecclayout   *layout;
 514         void *priv;
 515         void (*hwctl)(struct mtd_info *mtd, int mode);
 516         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 517                         uint8_t *ecc_code);
 518         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 519                         uint8_t *calc_ecc);
 520         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 521                         uint8_t *buf, int oob_required, int page);
 522         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 523                         const uint8_t *buf, int oob_required, int page);
 524         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 525                         uint8_t *buf, int oob_required, int page);
 526         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 527                         uint32_t offs, uint32_t len, uint8_t *buf, int page);
 528         int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 529                         uint32_t offset, uint32_t data_len,
 530                         const uint8_t *data_buf, int oob_required, int page);
 531         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 532                         const uint8_t *buf, int oob_required, int page);
 533         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 534                         int page);
 535         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 536                         int page);
 537         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 538         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 539                         int page);
 540 };
 541
 542 /**
 543  * struct nand_buffers - buffer structure for read/write
 544  * @ecccalc:    buffer pointer for calculated ECC, size is oobsize.
 545  * @ecccode:    buffer pointer for ECC read from flash, size is oobsize.
 546  * @databuf:    buffer pointer for data, size is (page size + oobsize).
 547  *
 548  * Do not change the order of buffers. databuf and oobrbuf must be in
 549  * consecutive order.
 550  */
 551 struct nand_buffers {
 552         uint8_t *ecccalc;
 553         uint8_t *ecccode;
 554         uint8_t *databuf;
 555 };
 556
 557 /**
 558  * struct nand_chip - NAND Private Flash Chip Data
 559  * @mtd:                MTD device registered to the MTD framework
 560  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 561  *                      flash device
 562  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 563  *                      flash device.
 564  * @read_byte:          [REPLACEABLE] read one byte from the chip
 565  * @read_word:          [REPLACEABLE] read one word from the chip
 566  * @write_byte:         [REPLACEABLE] write a single byte to the chip on the
 567  *                      low 8 I/O lines
 568  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 569  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 570  * @select_chip:        [REPLACEABLE] select chip nr
 571  * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
 572  * @block_markbad:      [REPLACEABLE] mark a block bad
 573  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 574  *                      ALE/CLE/nCE. Also used to write command and address
 575  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 576  *                      device ready/busy line. If set to NULL no access to
 577  *                      ready/busy is available and the ready/busy information
 578  *                      is read from the chip status register.
 579  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 580  *                      commands to the chip.
 581  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 582  *                      ready.
 583  * @setup_read_retry:   [FLASHSPECIFIC] flash (vendor) specific function for
 584  *                      setting the read-retry mode. Mostly needed for MLC NAND.
 585  * @ecc:                [BOARDSPECIFIC] ECC control structure
 586  * @buffers:            buffer structure for read/write
 587  * @hwcontrol:          platform-specific hardware control structure
 588  * @erase:              [REPLACEABLE] erase function
 589  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 590  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 591  *                      data from array to read regs (tR).
 592  * @state:              [INTERN] the current state of the NAND device
 593  * @oob_poi:            "poison value buffer," used for laying out OOB data
 594  *                      before writing
 595  * @page_shift:         [INTERN] number of address bits in a page (column
 596  *                      address bits).
 597  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 598  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 599  * @chip_shift:         [INTERN] number of address bits in one chip
 600  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 601  *                      be set to inform nand_scan about special functionality.
 602  *                      See the defines for further explanation.
 603  * @bbt_options:        [INTERN] bad block specific options. All options used
 604  *                      here must come from bbm.h. By default, these options
 605  *                      will be copied to the appropriate nand_bbt_descr's.
 606  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 607  *                      area.
 608  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 609  *                      bad block marker position; i.e., BBM == 11110111b is
 610  *                      not bad when badblockbits == 7
 611  * @bits_per_cell:      [INTERN] number of bits per cell. i.e., 1 means SLC.
 612  * @ecc_strength_ds:    [INTERN] ECC correctability from the datasheet.
 613  *                      Minimum amount of bit errors per @ecc_step_ds guaranteed
 614  *                      to be correctable. If unknown, set to zero.
 615  * @ecc_step_ds:        [INTERN] ECC step required by the @ecc_strength_ds,
 616  *                      also from the datasheet. It is the recommended ECC step
 617  *                      size, if known; if unknown, set to zero.
 618  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
 619  *                            either deduced from the datasheet if the NAND
 620  *                            chip is not ONFI compliant or set to 0 if it is
 621  *                            (an ONFI chip is always configured in mode 0
 622  *                            after a NAND reset)
 623  * @numchips:           [INTERN] number of physical chips
 624  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 625  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 626  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 627  *                      data_buf.
 628  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 629  *                      currently in data_buf.
 630  * @subpagesize:        [INTERN] holds the subpagesize
 631  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 632  *                      non 0 if ONFI supported.
 633  * @jedec_version:      [INTERN] holds the chip JEDEC version (BCD encoded),
 634  *                      non 0 if JEDEC supported.
 635  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 636  *                      supported, 0 otherwise.
 637  * @jedec_params:       [INTERN] holds the JEDEC parameter page when JEDEC is
 638  *                      supported, 0 otherwise.
 639  * @read_retries:       [INTERN] the number of read retry modes supported
 640  * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 641  * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 642  * @bbt:                [INTERN] bad block table pointer
 643  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 644  *                      lookup.
 645  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 646  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 647  *                      bad block scan.
 648  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 649  *                      structure which is shared among multiple independent
 650  *                      devices.
 651  * @priv:               [OPTIONAL] pointer to private chip data
 652  * @errstat:            [OPTIONAL] hardware specific function to perform
 653  *                      additional error status checks (determine if errors are
 654  *                      correctable).
 655  * @write_page:         [REPLACEABLE] High-level page write function
 656  */
 657
 658 struct nand_chip {
 659         struct mtd_info mtd;
 660         void __iomem *IO_ADDR_R;
 661         void __iomem *IO_ADDR_W;
 662
 663         uint8_t (*read_byte)(struct mtd_info *mtd);
 664         u16 (*read_word)(struct mtd_info *mtd);
 665         void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
 666         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 667         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 668         void (*select_chip)(struct mtd_info *mtd, int chip);
 669         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 670         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 671         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 672         int (*dev_ready)(struct mtd_info *mtd);
 673         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 674                         int page_addr);
 675         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 676         int (*erase)(struct mtd_info *mtd, int page);
 677         int (*scan_bbt)(struct mtd_info *mtd);
 678         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 679                         int status, int page);
 680         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 681                         uint32_t offset, int data_len, const uint8_t *buf,
 682                         int oob_required, int page, int cached, int raw);
 683         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 684                         int feature_addr, uint8_t *subfeature_para);
 685         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 686                         int feature_addr, uint8_t *subfeature_para);
 687         int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
 688
 689         int chip_delay;
 690         unsigned int options;
 691         unsigned int bbt_options;
 692
 693         int page_shift;
 694         int phys_erase_shift;
 695         int bbt_erase_shift;
 696         int chip_shift;
 697         int numchips;
 698         uint64_t chipsize;
 699         int pagemask;
 700         int pagebuf;
 701         unsigned int pagebuf_bitflips;
 702         int subpagesize;
 703         uint8_t bits_per_cell;
 704         uint16_t ecc_strength_ds;
 705         uint16_t ecc_step_ds;
 706         int onfi_timing_mode_default;
 707         int badblockpos;
 708         int badblockbits;
 709
 710         int onfi_version;
 711         int jedec_version;
 712         union {
 713                 struct nand_onfi_params onfi_params;
 714                 struct nand_jedec_params jedec_params;
 715         };
 716
 717         int read_retries;
 718
 719         flstate_t state;
 720
 721         uint8_t *oob_poi;
 722         struct nand_hw_control *controller;
 723
 724         struct nand_ecc_ctrl ecc;
 725         struct nand_buffers *buffers;
 726         struct nand_hw_control hwcontrol;
 727
 728         uint8_t *bbt;
 729         struct nand_bbt_descr *bbt_td;
 730         struct nand_bbt_descr *bbt_md;
 731
 732         struct nand_bbt_descr *badblock_pattern;
 733
 734         void *priv;
 735 };
 736
 737 static inline void nand_set_flash_node(struct nand_chip *chip,
 738                                        struct device_node *np)
 739 {
 740         mtd_set_of_node(&chip->mtd, np);
 741 }
 742
 743 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
 744 {
 745         return mtd_get_of_node(&chip->mtd);
 746 }
 747
 748 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
 749 {
 750         return container_of(mtd, struct nand_chip, mtd);
 751 }
 752
 753 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
 754 {
 755         return &chip->mtd;
 756 }
 757
 758 static inline void *nand_get_controller_data(struct nand_chip *chip)
 759 {
 760         return chip->priv;
 761 }
 762
 763 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
 764 {
 765         chip->priv = priv;
 766 }
 767
 768 /*
 769  * NAND Flash Manufacturer ID Codes
 770  */
 771 #define NAND_MFR_TOSHIBA        0x98
 772 #define NAND_MFR_SAMSUNG        0xec
 773 #define NAND_MFR_FUJITSU        0x04
 774 #define NAND_MFR_NATIONAL       0x8f
 775 #define NAND_MFR_RENESAS        0x07
 776 #define NAND_MFR_STMICRO        0x20
 777 #define NAND_MFR_HYNIX          0xad
 778 #define NAND_MFR_MICRON         0x2c
 779 #define NAND_MFR_AMD            0x01
 780 #define NAND_MFR_MACRONIX       0xc2
 781 #define NAND_MFR_EON            0x92
 782 #define NAND_MFR_SANDISK        0x45
 783 #define NAND_MFR_INTEL          0x89
 784 #define NAND_MFR_ATO            0x9b
 785
 786 /* The maximum expected count of bytes in the NAND ID sequence */
 787 #define NAND_MAX_ID_LEN 8
 788
 789 /*
 790  * A helper for defining older NAND chips where the second ID byte fully
 791  * defined the chip, including the geometry (chip size, eraseblock size, page
 792  * size). All these chips have 512 bytes NAND page size.
 793  */
 794 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 795         { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 796           .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 797
 798 /*
 799  * A helper for defining newer chips which report their page size and
 800  * eraseblock size via the extended ID bytes.
 801  *
 802  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
 803  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
 804  * device ID now only represented a particular total chip size (and voltage,
 805  * buswidth), and the page size, eraseblock size, and OOB size could vary while
 806  * using the same device ID.
 807  */
 808 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 809         { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 810           .options = (opts) }
 811
 812 #define NAND_ECC_INFO(_strength, _step) \
 813                         { .strength_ds = (_strength), .step_ds = (_step) }
 814 #define NAND_ECC_STRENGTH(type)         ((type)->ecc.strength_ds)
 815 #define NAND_ECC_STEP(type)             ((type)->ecc.step_ds)
 816
 817 /**
 818  * struct nand_flash_dev - NAND Flash Device ID Structure
 819  * @name: a human-readable name of the NAND chip
 820  * @dev_id: the device ID (the second byte of the full chip ID array)
 821  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
 822  *          memory address as @id[0])
 823  * @dev_id: device ID part of the full chip ID array (refers the same memory
 824  *          address as @id[1])
 825  * @id: full device ID array
 826  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
 827  *            well as the eraseblock size) is determined from the extended NAND
 828  *            chip ID array)
 829  * @chipsize: total chip size in MiB
 830  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
 831  * @options: stores various chip bit options
 832  * @id_len: The valid length of the @id.
 833  * @oobsize: OOB size
 834  * @ecc: ECC correctability and step information from the datasheet.
 835  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
 836  *                   @ecc_strength_ds in nand_chip{}.
 837  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
 838  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
 839  *               For example, the "4bit ECC for each 512Byte" can be set with
 840  *               NAND_ECC_INFO(4, 512).
 841  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
 842  *                            reset. Should be deduced from timings described
 843  *                            in the datasheet.
 844  *
 845  */
 846 struct nand_flash_dev {
 847         char *name;
 848         union {
 849                 struct {
 850                         uint8_t mfr_id;
 851                         uint8_t dev_id;
 852                 };
 853                 uint8_t id[NAND_MAX_ID_LEN];
 854         };
 855         unsigned int pagesize;
 856         unsigned int chipsize;
 857         unsigned int erasesize;
 858         unsigned int options;
 859         uint16_t id_len;
 860         uint16_t oobsize;
 861         struct {
 862                 uint16_t strength_ds;
 863                 uint16_t step_ds;
 864         } ecc;
 865         int onfi_timing_mode_default;
 866 };
 867
 868 /**
 869  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 870  * @name:       Manufacturer name
 871  * @id:         manufacturer ID code of device.
 872 */
 873 struct nand_manufacturers {
 874         int id;
 875         char *name;
 876 };
 877
 878 extern struct nand_flash_dev nand_flash_ids[];
 879 extern struct nand_manufacturers nand_manuf_ids[];
 880
 881 extern int nand_default_bbt(struct mtd_info *mtd);
 882 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 883 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
 884 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 885 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 886                            int allowbbt);
 887 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 888                         size_t *retlen, uint8_t *buf);
 889
 890 /**
 891  * struct platform_nand_chip - chip level device structure
 892  * @nr_chips:           max. number of chips to scan for
 893  * @chip_offset:        chip number offset
 894  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 895  * @partitions:         mtd partition list
 896  * @chip_delay:         R/B delay value in us
 897  * @options:            Option flags, e.g. 16bit buswidth
 898  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 899  * @ecclayout:          ECC layout info structure
 900  * @part_probe_types:   NULL-terminated array of probe types
 901  */
 902 struct platform_nand_chip {
 903         int nr_chips;
 904         int chip_offset;
 905         int nr_partitions;
 906         struct mtd_partition *partitions;
 907         struct nand_ecclayout *ecclayout;
 908         int chip_delay;
 909         unsigned int options;
 910         unsigned int bbt_options;
 911         const char **part_probe_types;
 912 };
 913
 914 /* Keep gcc happy */
 915 struct platform_device;
 916
 917 /**
 918  * struct platform_nand_ctrl - controller level device structure
 919  * @probe:              platform specific function to probe/setup hardware
 920  * @remove:             platform specific function to remove/teardown hardware
 921  * @hwcontrol:          platform specific hardware control structure
 922  * @dev_ready:          platform specific function to read ready/busy pin
 923  * @select_chip:        platform specific chip select function
 924  * @cmd_ctrl:           platform specific function for controlling
 925  *                      ALE/CLE/nCE. Also used to write command and address
 926  * @write_buf:          platform specific function for write buffer
 927  * @read_buf:           platform specific function for read buffer
 928  * @read_byte:          platform specific function to read one byte from chip
 929  * @priv:               private data to transport driver specific settings
 930  *
 931  * All fields are optional and depend on the hardware driver requirements
 932  */
 933 struct platform_nand_ctrl {
 934         int (*probe)(struct platform_device *pdev);
 935         void (*remove)(struct platform_device *pdev);
 936         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 937         int (*dev_ready)(struct mtd_info *mtd);
 938         void (*select_chip)(struct mtd_info *mtd, int chip);
 939         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 940         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 941         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 942         unsigned char (*read_byte)(struct mtd_info *mtd);
 943         void *priv;
 944 };
 945
 946 /**
 947  * struct platform_nand_data - container structure for platform-specific data
 948  * @chip:               chip level chip structure
 949  * @ctrl:               controller level device structure
 950  */
 951 struct platform_nand_data {
 952         struct platform_nand_chip chip;
 953         struct platform_nand_ctrl ctrl;
 954 };
 955
 956 /* return the supported features. */
 957 static inline int onfi_feature(struct nand_chip *chip)
 958 {
 959         return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
 960 }
 961
 962 /* return the supported asynchronous timing mode. */
 963 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 964 {
 965         if (!chip->onfi_version)
 966                 return ONFI_TIMING_MODE_UNKNOWN;
 967         return le16_to_cpu(chip->onfi_params.async_timing_mode);
 968 }
 969
 970 /* return the supported synchronous timing mode. */
 971 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 972 {
 973         if (!chip->onfi_version)
 974                 return ONFI_TIMING_MODE_UNKNOWN;
 975         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 976 }
 977
 978 /*
 979  * Check if it is a SLC nand.
 980  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
 981  * We do not distinguish the MLC and TLC now.
 982  */
 983 static inline bool nand_is_slc(struct nand_chip *chip)
 984 {
 985         return chip->bits_per_cell == 1;
 986 }
 987
 988 /**
 989  * Check if the opcode's address should be sent only on the lower 8 bits
 990  * @command: opcode to check
 991  */
 992 static inline int nand_opcode_8bits(unsigned int command)
 993 {
 994         switch (command) {
 995         case NAND_CMD_READID:
 996         case NAND_CMD_PARAM:
 997         case NAND_CMD_GET_FEATURES:
 998         case NAND_CMD_SET_FEATURES:
 999                 return 1;
1000         default:
1001                 break;
1002         }
1003         return 0;
1004 }
1005
1006 /* return the supported JEDEC features. */
1007 static inline int jedec_feature(struct nand_chip *chip)
1008 {
1009         return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1010                 : 0;
1011 }
1012
1013 /*
1014  * struct nand_sdr_timings - SDR NAND chip timings
1015  *
1016  * This struct defines the timing requirements of a SDR NAND chip.
1017  * These informations can be found in every NAND datasheets and the timings
1018  * meaning are described in the ONFI specifications:
1019  * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
1020  * Parameters)
1021  *
1022  * All these timings are expressed in picoseconds.
1023  */
1024
1025 struct nand_sdr_timings {
1026         u32 tALH_min;
1027         u32 tADL_min;
1028         u32 tALS_min;
1029         u32 tAR_min;
1030         u32 tCEA_max;
1031         u32 tCEH_min;
1032         u32 tCH_min;
1033         u32 tCHZ_max;
1034         u32 tCLH_min;
1035         u32 tCLR_min;
1036         u32 tCLS_min;
1037         u32 tCOH_min;
1038         u32 tCS_min;
1039         u32 tDH_min;
1040         u32 tDS_min;
1041         u32 tFEAT_max;
1042         u32 tIR_min;
1043         u32 tITC_max;
1044         u32 tRC_min;
1045         u32 tREA_max;
1046         u32 tREH_min;
1047         u32 tRHOH_min;
1048         u32 tRHW_min;
1049         u32 tRHZ_max;
1050         u32 tRLOH_min;
1051         u32 tRP_min;
1052         u32 tRR_min;
1053         u64 tRST_max;
1054         u32 tWB_max;
1055         u32 tWC_min;
1056         u32 tWH_min;
1057         u32 tWHR_min;
1058         u32 tWP_min;
1059         u32 tWW_min;
1060 };
1061
1062 /* get timing characteristics from ONFI timing mode. */
1063 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1064
1065 int nand_check_erased_ecc_chunk(void *data, int datalen,
1066                                 void *ecc, int ecclen,
1067                                 void *extraoob, int extraooblen,
1068                                 int threshold);
1069 #endif /* __LINUX_MTD_NAND_H */