2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <uapi/linux/nvme.h>
19 #include <linux/pci.h>
20 #include <linux/kref.h>
21 #include <linux/blk-mq.h>
24 __u64 cap
; /* Controller Capabilities */
25 __u32 vs
; /* Version */
26 __u32 intms
; /* Interrupt Mask Set */
27 __u32 intmc
; /* Interrupt Mask Clear */
28 __u32 cc
; /* Controller Configuration */
29 __u32 rsvd1
; /* Reserved */
30 __u32 csts
; /* Controller Status */
31 __u32 nssr
; /* Subsystem Reset */
32 __u32 aqa
; /* Admin Queue Attributes */
33 __u64 asq
; /* Admin SQ Base Address */
34 __u64 acq
; /* Admin CQ Base Address */
35 __u32 cmbloc
; /* Controller Memory Buffer Location */
36 __u32 cmbsz
; /* Controller Memory Buffer Size */
39 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
40 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
41 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
42 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
43 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
44 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
46 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
47 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
48 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
49 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
51 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
52 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
53 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
54 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
55 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
58 NVME_CC_ENABLE
= 1 << 0,
59 NVME_CC_CSS_NVM
= 0 << 4,
60 NVME_CC_MPS_SHIFT
= 7,
61 NVME_CC_ARB_RR
= 0 << 11,
62 NVME_CC_ARB_WRRU
= 1 << 11,
63 NVME_CC_ARB_VS
= 7 << 11,
64 NVME_CC_SHN_NONE
= 0 << 14,
65 NVME_CC_SHN_NORMAL
= 1 << 14,
66 NVME_CC_SHN_ABRUPT
= 2 << 14,
67 NVME_CC_SHN_MASK
= 3 << 14,
68 NVME_CC_IOSQES
= 6 << 16,
69 NVME_CC_IOCQES
= 4 << 20,
70 NVME_CSTS_RDY
= 1 << 0,
71 NVME_CSTS_CFS
= 1 << 1,
72 NVME_CSTS_NSSRO
= 1 << 4,
73 NVME_CSTS_SHST_NORMAL
= 0 << 2,
74 NVME_CSTS_SHST_OCCUR
= 1 << 2,
75 NVME_CSTS_SHST_CMPLT
= 2 << 2,
76 NVME_CSTS_SHST_MASK
= 3 << 2,
79 extern unsigned char nvme_io_timeout
;
80 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
83 * Represents an NVM Express device. Each nvme_dev is a PCI function.
86 struct list_head node
;
87 struct nvme_queue
**queues
;
88 struct request_queue
*admin_q
;
89 struct blk_mq_tag_set tagset
;
90 struct blk_mq_tag_set admin_tagset
;
93 struct dma_pool
*prp_page_pool
;
94 struct dma_pool
*prp_small_pool
;
97 unsigned online_queues
;
102 struct msix_entry
*entry
;
103 struct nvme_bar __iomem
*bar
;
104 struct list_head namespaces
;
106 struct device
*device
;
107 work_func_t reset_workfn
;
108 struct work_struct reset_work
;
109 struct work_struct probe_work
;
110 struct work_struct scan_work
;
114 char firmware_rev
[8];
120 dma_addr_t cmb_dma_addr
;
130 * An NVM Express namespace is equivalent to a SCSI LUN
133 struct list_head list
;
135 struct nvme_dev
*dev
;
136 struct request_queue
*queue
;
137 struct gendisk
*disk
;
144 u64 mode_select_num_blocks
;
145 u32 mode_select_block_len
;
149 * The nvme_iod describes the data in an I/O, including the list of PRP
150 * entries. You can't see it in this data structure because C doesn't let
151 * me express that. Use nvme_alloc_iod to ensure there's enough space
152 * allocated to store the PRP list.
155 unsigned long private; /* For the use of the submitter of the I/O */
156 int npages
; /* In the PRP list. 0 means small pool in use */
157 int offset
; /* Of PRP list */
158 int nents
; /* Used in scatterlist */
159 int length
; /* Of data, in bytes */
160 dma_addr_t first_dma
;
161 struct scatterlist meta_sg
[1]; /* metadata requires single contiguous buffer */
162 struct scatterlist sg
[0];
165 static inline u64
nvme_block_nr(struct nvme_ns
*ns
, sector_t sector
)
167 return (sector
>> (ns
->lba_shift
- 9));
170 int nvme_submit_sync_cmd(struct request_queue
*q
, struct nvme_command
*cmd
,
171 void *buf
, unsigned bufflen
);
172 int __nvme_submit_sync_cmd(struct request_queue
*q
, struct nvme_command
*cmd
,
173 void *buffer
, void __user
*ubuffer
, unsigned bufflen
,
174 u32
*result
, unsigned timeout
);
175 int nvme_identify_ctrl(struct nvme_dev
*dev
, struct nvme_id_ctrl
**id
);
176 int nvme_identify_ns(struct nvme_dev
*dev
, unsigned nsid
,
177 struct nvme_id_ns
**id
);
178 int nvme_get_log_page(struct nvme_dev
*dev
, struct nvme_smart_log
**log
);
179 int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
, unsigned nsid
,
180 dma_addr_t dma_addr
, u32
*result
);
181 int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
, unsigned dword11
,
182 dma_addr_t dma_addr
, u32
*result
);
186 int nvme_sg_io(struct nvme_ns
*ns
, struct sg_io_hdr __user
*u_hdr
);
187 int nvme_sg_io32(struct nvme_ns
*ns
, unsigned long arg
);
188 int nvme_sg_get_version_num(int __user
*ip
);
190 #endif /* _LINUX_NVME_H */