4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <uapi/linux/pci.h>
34 #include <linux/pci_ids.h>
37 * The PCI interface treats multi-function devices as independent
38 * devices. The slot/function address of each device is encoded
39 * in a single byte as follows:
44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
45 * In the interest of not exposing interfaces to user-space unnecessarily,
46 * the following kernel-only defines are being added here.
48 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52 /* pci_slot represents a physical slot */
54 struct pci_bus
*bus
; /* The bus this slot is on */
55 struct list_head list
; /* node in list of slots on this bus */
56 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
57 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
61 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
63 return kobject_name(&slot
->kobj
);
66 /* File state for mmap()s on /proc/bus/pci/X/Y */
72 /* This defines the direction arg to the DMA mapping routines. */
73 #define PCI_DMA_BIDIRECTIONAL 0
74 #define PCI_DMA_TODEVICE 1
75 #define PCI_DMA_FROMDEVICE 2
76 #define PCI_DMA_NONE 3
79 * For PCI devices, the region numbers are assigned this way:
82 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCE_END
= 5,
86 /* #6: expansion ROM resource */
89 /* device specific resources */
92 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
95 /* resources assigned to buses behind the bridge */
96 #define PCI_BRIDGE_RESOURCE_NUM 4
99 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
100 PCI_BRIDGE_RESOURCE_NUM
- 1,
102 /* total resources associated with a PCI device */
105 /* preserve this for compatibility */
106 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
109 typedef int __bitwise pci_power_t
;
111 #define PCI_D0 ((pci_power_t __force) 0)
112 #define PCI_D1 ((pci_power_t __force) 1)
113 #define PCI_D2 ((pci_power_t __force) 2)
114 #define PCI_D3hot ((pci_power_t __force) 3)
115 #define PCI_D3cold ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names
[];
122 static inline const char *pci_power_name(pci_power_t state
)
124 return pci_power_names
[1 + (int) state
];
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_D3COLD_WAIT 100
130 #define PCI_PM_BUS_WAIT 50
132 /** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
136 typedef unsigned int __bitwise pci_channel_state_t
;
138 enum pci_channel_state
{
139 /* I/O channel is in normal state */
140 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
145 /* PCI card is dead */
146 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
149 typedef unsigned int __bitwise pcie_reset_state_t
;
151 enum pcie_reset_state
{
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
155 /* Use #PERST to reset PCIe device */
156 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
158 /* Use PCIe Hot Reset to reset device */
159 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
162 typedef unsigned short __bitwise pci_dev_flags_t
;
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) 1,
168 /* Device configuration is irrevocably lost if disabled into D3 */
169 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) 2,
170 /* Provide indication device is assigned by a Virtual Machine Manager */
171 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) 4,
172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) 8,
176 enum pci_irq_reroute_variant
{
177 INTEL_IRQ_REROUTE_VARIANT
= 1,
178 MAX_IRQ_REROUTE_VARIANTS
= 3
181 typedef unsigned short __bitwise pci_bus_flags_t
;
183 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
184 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
187 /* These values come from the PCI Express Spec */
188 enum pcie_link_width
{
189 PCIE_LNK_WIDTH_RESRV
= 0x00,
197 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
200 /* Based on the PCI Hotplug Spec, but some values are made up by us */
202 PCI_SPEED_33MHz
= 0x00,
203 PCI_SPEED_66MHz
= 0x01,
204 PCI_SPEED_66MHz_PCIX
= 0x02,
205 PCI_SPEED_100MHz_PCIX
= 0x03,
206 PCI_SPEED_133MHz_PCIX
= 0x04,
207 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
208 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
209 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
210 PCI_SPEED_66MHz_PCIX_266
= 0x09,
211 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
212 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
218 PCI_SPEED_66MHz_PCIX_533
= 0x11,
219 PCI_SPEED_100MHz_PCIX_533
= 0x12,
220 PCI_SPEED_133MHz_PCIX_533
= 0x13,
221 PCIE_SPEED_2_5GT
= 0x14,
222 PCIE_SPEED_5_0GT
= 0x15,
223 PCIE_SPEED_8_0GT
= 0x16,
224 PCI_SPEED_UNKNOWN
= 0xff,
227 struct pci_cap_saved_data
{
234 struct pci_cap_saved_state
{
235 struct hlist_node next
;
236 struct pci_cap_saved_data cap
;
239 struct pcie_link_state
;
245 * The pci_dev structure is used to describe PCI devices.
248 struct list_head bus_list
; /* node in per-bus list */
249 struct pci_bus
*bus
; /* bus this device is on */
250 struct pci_bus
*subordinate
; /* bus this device bridges to */
252 void *sysdata
; /* hook for sys-specific extension */
253 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
254 struct pci_slot
*slot
; /* Physical slot this device is in */
256 unsigned int devfn
; /* encoded device & function index */
257 unsigned short vendor
;
258 unsigned short device
;
259 unsigned short subsystem_vendor
;
260 unsigned short subsystem_device
;
261 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
262 u8 revision
; /* PCI revision, low byte of class word */
263 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
264 u8 pcie_cap
; /* PCIe capability offset */
265 u8 msi_cap
; /* MSI capability offset */
266 u8 msix_cap
; /* MSI-X capability offset */
267 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
268 u8 rom_base_reg
; /* which config register controls the ROM */
269 u8 pin
; /* which interrupt pin this device uses */
270 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
272 struct pci_driver
*driver
; /* which driver has allocated this device */
273 u64 dma_mask
; /* Mask of the bits of bus address this
274 device implements. Normally this is
275 0xffffffff. You only need to change
276 this if your device has broken DMA
277 or supports 64-bit transfers. */
279 struct device_dma_parameters dma_parms
;
281 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
282 this is D0-D3, D0 being fully functional,
284 u8 pm_cap
; /* PM capability offset */
285 unsigned int pme_support
:5; /* Bitmask of states from which PME#
287 unsigned int pme_interrupt
:1;
288 unsigned int pme_poll
:1; /* Poll device's PME status bit */
289 unsigned int d1_support
:1; /* Low power state D1 is supported */
290 unsigned int d2_support
:1; /* Low power state D2 is supported */
291 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
292 unsigned int no_d3cold
:1; /* D3cold is forbidden */
293 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
294 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
295 decoding during bar sizing */
296 unsigned int wakeup_prepared
:1;
297 unsigned int runtime_d3cold
:1; /* whether go through runtime
298 D3cold, not set for devices
299 powered on/off by the
300 corresponding bridge */
301 unsigned int d3_delay
; /* D3->D0 transition time in ms */
302 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
304 #ifdef CONFIG_PCIEASPM
305 struct pcie_link_state
*link_state
; /* ASPM link state */
308 pci_channel_state_t error_state
; /* current connectivity state */
309 struct device dev
; /* Generic device interface */
311 int cfg_size
; /* Size of configuration space */
314 * Instead of touching interrupt line and base address registers
315 * directly, use the values stored here. They might be different!
318 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
320 bool match_driver
; /* Skip attaching driver */
321 /* These fields are used by common fixups */
322 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
323 unsigned int multifunction
:1;/* Part of multi-function device */
324 /* keep track of device state */
325 unsigned int is_added
:1;
326 unsigned int is_busmaster
:1; /* device is busmaster */
327 unsigned int no_msi
:1; /* device may not use msi */
328 unsigned int block_cfg_access
:1; /* config space access is blocked */
329 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
330 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
331 unsigned int msi_enabled
:1;
332 unsigned int msix_enabled
:1;
333 unsigned int ari_enabled
:1; /* ARI forwarding */
334 unsigned int is_managed
:1;
335 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
336 unsigned int state_saved
:1;
337 unsigned int is_physfn
:1;
338 unsigned int is_virtfn
:1;
339 unsigned int reset_fn
:1;
340 unsigned int is_hotplug_bridge
:1;
341 unsigned int __aer_firmware_first_valid
:1;
342 unsigned int __aer_firmware_first
:1;
343 unsigned int broken_intx_masking
:1;
344 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
345 pci_dev_flags_t dev_flags
;
346 atomic_t enable_cnt
; /* pci_enable_device has been called */
348 u32 saved_config_space
[16]; /* config space saved at suspend time */
349 struct hlist_head saved_cap_space
;
350 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
351 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
352 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
353 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
354 #ifdef CONFIG_PCI_MSI
355 struct list_head msi_list
;
356 const struct attribute_group
**msi_irq_groups
;
359 #ifdef CONFIG_PCI_ATS
361 struct pci_sriov
*sriov
; /* SR-IOV capability related */
362 struct pci_dev
*physfn
; /* the PF this VF is associated with */
364 struct pci_ats
*ats
; /* Address Translation Service */
366 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
367 size_t romlen
; /* Length of ROM if it's not from the BAR */
368 char *driver_override
; /* Driver name to force a match */
371 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
373 #ifdef CONFIG_PCI_IOV
380 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
382 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
383 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
385 static inline int pci_channel_offline(struct pci_dev
*pdev
)
387 return (pdev
->error_state
!= pci_channel_io_normal
);
390 struct pci_host_bridge_window
{
391 struct list_head list
;
392 struct resource
*res
; /* host bridge aperture (CPU address) */
393 resource_size_t offset
; /* bus address + offset = CPU address */
396 struct pci_host_bridge
{
398 struct pci_bus
*bus
; /* root bus */
399 struct list_head windows
; /* pci_host_bridge_windows */
400 void (*release_fn
)(struct pci_host_bridge
*);
404 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
405 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
406 void (*release_fn
)(struct pci_host_bridge
*),
409 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
412 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
413 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
414 * buses below host bridges or subtractive decode bridges) go in the list.
415 * Use pci_bus_for_each_resource() to iterate through all the resources.
419 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
420 * and there's no way to program the bridge with the details of the window.
421 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
422 * decode bit set, because they are explicit and can be programmed with _SRS.
424 #define PCI_SUBTRACTIVE_DECODE 0x1
426 struct pci_bus_resource
{
427 struct list_head list
;
428 struct resource
*res
;
432 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
435 struct list_head node
; /* node in list of buses */
436 struct pci_bus
*parent
; /* parent bus this bridge is on */
437 struct list_head children
; /* list of child buses */
438 struct list_head devices
; /* list of devices on this bus */
439 struct pci_dev
*self
; /* bridge device as seen by parent */
440 struct list_head slots
; /* list of slots on this bus */
441 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
442 struct list_head resources
; /* address space routed to this bus */
443 struct resource busn_res
; /* bus numbers routed to this bus */
445 struct pci_ops
*ops
; /* configuration access functions */
446 struct msi_chip
*msi
; /* MSI controller */
447 void *sysdata
; /* hook for sys-specific extension */
448 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
450 unsigned char number
; /* bus number */
451 unsigned char primary
; /* number of primary bridge */
452 unsigned char max_bus_speed
; /* enum pci_bus_speed */
453 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
457 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
458 pci_bus_flags_t bus_flags
; /* inherited by child buses */
459 struct device
*bridge
;
461 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
462 struct bin_attribute
*legacy_mem
; /* legacy mem */
463 unsigned int is_added
:1;
466 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
469 * Returns true if the PCI bus is root (behind host-PCI bridge),
472 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
473 * This is incorrect because "virtual" buses added for SR-IOV (via
474 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
476 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
478 return !(pbus
->parent
);
482 * pci_is_bridge - check if the PCI device is a bridge
485 * Return true if the PCI device is bridge whether it has subordinate
488 static inline bool pci_is_bridge(struct pci_dev
*dev
)
490 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
491 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
494 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
496 dev
= pci_physfn(dev
);
497 if (pci_is_root_bus(dev
->bus
))
500 return dev
->bus
->self
;
503 #ifdef CONFIG_PCI_MSI
504 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
506 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
509 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
513 * Error values that may be returned by PCI functions.
515 #define PCIBIOS_SUCCESSFUL 0x00
516 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
517 #define PCIBIOS_BAD_VENDOR_ID 0x83
518 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
519 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
520 #define PCIBIOS_SET_FAILED 0x88
521 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
524 * Translate above to generic errno for passing back through non-PCI code.
526 static inline int pcibios_err_to_errno(int err
)
528 if (err
<= PCIBIOS_SUCCESSFUL
)
529 return err
; /* Assume already errno */
532 case PCIBIOS_FUNC_NOT_SUPPORTED
:
534 case PCIBIOS_BAD_VENDOR_ID
:
536 case PCIBIOS_DEVICE_NOT_FOUND
:
538 case PCIBIOS_BAD_REGISTER_NUMBER
:
540 case PCIBIOS_SET_FAILED
:
542 case PCIBIOS_BUFFER_TOO_SMALL
:
549 /* Low-level architecture-dependent routines */
552 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
553 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
557 * ACPI needs to be able to access PCI config space before we've done a
558 * PCI bus scan and created pci_bus structures.
560 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
561 int reg
, int len
, u32
*val
);
562 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
563 int reg
, int len
, u32 val
);
565 struct pci_bus_region
{
571 spinlock_t lock
; /* protects list, index */
572 struct list_head list
; /* for IDs added at runtime */
577 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
578 * a set of callbacks in struct pci_error_handlers, that device driver
579 * will be notified of PCI bus errors, and will be driven to recovery
580 * when an error occurs.
583 typedef unsigned int __bitwise pci_ers_result_t
;
585 enum pci_ers_result
{
586 /* no result/none/not supported in device driver */
587 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
589 /* Device driver can recover without slot reset */
590 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
592 /* Device driver wants slot to be reset. */
593 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
595 /* Device has completely failed, is unrecoverable */
596 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
598 /* Device driver is fully recovered and operational */
599 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
601 /* No AER capabilities registered for the driver */
602 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
605 /* PCI bus error event callbacks */
606 struct pci_error_handlers
{
607 /* PCI bus error detected on this device */
608 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
609 enum pci_channel_state error
);
611 /* MMIO has been re-enabled, but not DMA */
612 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
614 /* PCI Express link has been reset */
615 pci_ers_result_t (*link_reset
)(struct pci_dev
*dev
);
617 /* PCI slot has been reset */
618 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
620 /* PCI function reset prepare or completed */
621 void (*reset_notify
)(struct pci_dev
*dev
, bool prepare
);
623 /* Device driver may resume normal operations */
624 void (*resume
)(struct pci_dev
*dev
);
630 struct list_head node
;
632 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
633 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
634 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
635 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
636 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
637 int (*resume_early
) (struct pci_dev
*dev
);
638 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
639 void (*shutdown
) (struct pci_dev
*dev
);
640 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
641 const struct pci_error_handlers
*err_handler
;
642 struct device_driver driver
;
643 struct pci_dynids dynids
;
646 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
649 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
650 * @_table: device table name
652 * This macro is deprecated and should not be used in new code.
654 #define DEFINE_PCI_DEVICE_TABLE(_table) \
655 const struct pci_device_id _table[]
658 * PCI_DEVICE - macro used to describe a specific pci device
659 * @vend: the 16 bit PCI Vendor ID
660 * @dev: the 16 bit PCI Device ID
662 * This macro is used to create a struct pci_device_id that matches a
663 * specific device. The subvendor and subdevice fields will be set to
666 #define PCI_DEVICE(vend,dev) \
667 .vendor = (vend), .device = (dev), \
668 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
671 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
672 * @vend: the 16 bit PCI Vendor ID
673 * @dev: the 16 bit PCI Device ID
674 * @subvend: the 16 bit PCI Subvendor ID
675 * @subdev: the 16 bit PCI Subdevice ID
677 * This macro is used to create a struct pci_device_id that matches a
678 * specific device with subsystem information.
680 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
681 .vendor = (vend), .device = (dev), \
682 .subvendor = (subvend), .subdevice = (subdev)
685 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
686 * @dev_class: the class, subclass, prog-if triple for this device
687 * @dev_class_mask: the class mask for this device
689 * This macro is used to create a struct pci_device_id that matches a
690 * specific PCI class. The vendor, device, subvendor, and subdevice
691 * fields will be set to PCI_ANY_ID.
693 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
694 .class = (dev_class), .class_mask = (dev_class_mask), \
695 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
696 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
699 * PCI_VDEVICE - macro used to describe a specific pci device in short form
700 * @vend: the vendor name
701 * @dev: the 16 bit PCI Device ID
703 * This macro is used to create a struct pci_device_id that matches a
704 * specific PCI device. The subvendor, and subdevice fields will be set
705 * to PCI_ANY_ID. The macro allows the next field to follow as the device
709 #define PCI_VDEVICE(vend, dev) \
710 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
711 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
713 /* these external functions are only available when PCI support is enabled */
716 void pcie_bus_configure_settings(struct pci_bus
*bus
);
718 enum pcie_bus_config_types
{
721 PCIE_BUS_PERFORMANCE
,
725 extern enum pcie_bus_config_types pcie_bus_config
;
727 extern struct bus_type pci_bus_type
;
729 /* Do NOT directly access these two variables, unless you are arch-specific PCI
730 * code, or PCI core code. */
731 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
732 /* Some device drivers need know if PCI is initiated */
733 int no_pci_devices(void);
735 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
736 void pcibios_add_bus(struct pci_bus
*bus
);
737 void pcibios_remove_bus(struct pci_bus
*bus
);
738 void pcibios_fixup_bus(struct pci_bus
*);
739 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
740 /* Architecture-specific versions may override this (weak) */
741 char *pcibios_setup(char *str
);
743 /* Used only when drivers/pci/setup.c is used */
744 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
747 void pcibios_update_irq(struct pci_dev
*, int irq
);
749 /* Weak but can be overriden by arch */
750 void pci_fixup_cardbus(struct pci_bus
*);
752 /* Generic PCI functions used internally */
754 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
755 struct resource
*res
);
756 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
757 struct pci_bus_region
*region
);
758 void pcibios_scan_specific_bus(int busn
);
759 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
760 void pci_bus_add_devices(const struct pci_bus
*bus
);
761 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
, int bus
,
762 struct pci_ops
*ops
, void *sysdata
);
763 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
764 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
765 struct pci_ops
*ops
, void *sysdata
,
766 struct list_head
*resources
);
767 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
768 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
769 void pci_bus_release_busn_res(struct pci_bus
*b
);
770 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
771 struct pci_ops
*ops
, void *sysdata
,
772 struct list_head
*resources
);
773 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
775 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
776 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
778 struct hotplug_slot
*hotplug
);
779 void pci_destroy_slot(struct pci_slot
*slot
);
780 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
781 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
782 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
783 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
784 void pci_bus_add_device(struct pci_dev
*dev
);
785 void pci_read_bridge_bases(struct pci_bus
*child
);
786 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
787 struct resource
*res
);
788 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
789 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
790 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
791 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
792 void pci_dev_put(struct pci_dev
*dev
);
793 void pci_remove_bus(struct pci_bus
*b
);
794 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
795 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
796 void pci_stop_root_bus(struct pci_bus
*bus
);
797 void pci_remove_root_bus(struct pci_bus
*bus
);
798 void pci_setup_cardbus(struct pci_bus
*bus
);
799 void pci_sort_breadthfirst(void);
800 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
801 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
802 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
804 /* Generic PCI functions exported to card drivers */
806 enum pci_lost_interrupt_reason
{
807 PCI_LOST_IRQ_NO_INFORMATION
= 0,
808 PCI_LOST_IRQ_DISABLE_MSI
,
809 PCI_LOST_IRQ_DISABLE_MSIX
,
810 PCI_LOST_IRQ_DISABLE_ACPI
,
812 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
813 int pci_find_capability(struct pci_dev
*dev
, int cap
);
814 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
815 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
816 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
817 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
818 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
819 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
821 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
822 struct pci_dev
*from
);
823 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
824 unsigned int ss_vendor
, unsigned int ss_device
,
825 struct pci_dev
*from
);
826 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
827 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
829 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
832 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
834 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
835 int pci_dev_present(const struct pci_device_id
*ids
);
837 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
839 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
840 int where
, u16
*val
);
841 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
842 int where
, u32
*val
);
843 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
845 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
847 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
849 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
851 static inline int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
)
853 return pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
855 static inline int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
)
857 return pci_bus_read_config_word(dev
->bus
, dev
->devfn
, where
, val
);
859 static inline int pci_read_config_dword(const struct pci_dev
*dev
, int where
,
862 return pci_bus_read_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
864 static inline int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
)
866 return pci_bus_write_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
868 static inline int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
)
870 return pci_bus_write_config_word(dev
->bus
, dev
->devfn
, where
, val
);
872 static inline int pci_write_config_dword(const struct pci_dev
*dev
, int where
,
875 return pci_bus_write_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
878 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
879 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
880 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
881 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
882 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
884 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
887 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
890 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
893 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
896 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
899 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
902 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
905 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
908 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
911 /* user-space driven config access */
912 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
913 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
914 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
915 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
916 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
917 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
919 int __must_check
pci_enable_device(struct pci_dev
*dev
);
920 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
921 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
922 int __must_check
pci_reenable_device(struct pci_dev
*);
923 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
924 void pcim_pin_device(struct pci_dev
*pdev
);
926 static inline int pci_is_enabled(struct pci_dev
*pdev
)
928 return (atomic_read(&pdev
->enable_cnt
) > 0);
931 static inline int pci_is_managed(struct pci_dev
*pdev
)
933 return pdev
->is_managed
;
936 void pci_disable_device(struct pci_dev
*dev
);
938 extern unsigned int pcibios_max_latency
;
939 void pci_set_master(struct pci_dev
*dev
);
940 void pci_clear_master(struct pci_dev
*dev
);
942 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
943 int pci_set_cacheline_size(struct pci_dev
*dev
);
944 #define HAVE_PCI_SET_MWI
945 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
946 int pci_try_set_mwi(struct pci_dev
*dev
);
947 void pci_clear_mwi(struct pci_dev
*dev
);
948 void pci_intx(struct pci_dev
*dev
, int enable
);
949 bool pci_intx_mask_supported(struct pci_dev
*dev
);
950 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
951 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
952 void pci_msi_off(struct pci_dev
*dev
);
953 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
);
954 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
);
955 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
956 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
957 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
958 int pcix_get_mmrbc(struct pci_dev
*dev
);
959 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
960 int pcie_get_readrq(struct pci_dev
*dev
);
961 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
962 int pcie_get_mps(struct pci_dev
*dev
);
963 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
964 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
965 enum pcie_link_width
*width
);
966 int __pci_reset_function(struct pci_dev
*dev
);
967 int __pci_reset_function_locked(struct pci_dev
*dev
);
968 int pci_reset_function(struct pci_dev
*dev
);
969 int pci_try_reset_function(struct pci_dev
*dev
);
970 int pci_probe_reset_slot(struct pci_slot
*slot
);
971 int pci_reset_slot(struct pci_slot
*slot
);
972 int pci_try_reset_slot(struct pci_slot
*slot
);
973 int pci_probe_reset_bus(struct pci_bus
*bus
);
974 int pci_reset_bus(struct pci_bus
*bus
);
975 int pci_try_reset_bus(struct pci_bus
*bus
);
976 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
977 void pci_update_resource(struct pci_dev
*dev
, int resno
);
978 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
979 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
980 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
981 bool pci_device_is_present(struct pci_dev
*pdev
);
983 /* ROM control related routines */
984 int pci_enable_rom(struct pci_dev
*pdev
);
985 void pci_disable_rom(struct pci_dev
*pdev
);
986 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
987 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
988 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
989 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
991 /* Power management related routines */
992 int pci_save_state(struct pci_dev
*dev
);
993 void pci_restore_state(struct pci_dev
*dev
);
994 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
995 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
996 struct pci_saved_state
**state
);
997 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
998 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1000 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1001 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1002 u16 cap
, unsigned int size
);
1003 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1004 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1005 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1006 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1007 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1008 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1009 bool runtime
, bool enable
);
1010 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1011 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1012 int pci_back_from_sleep(struct pci_dev
*dev
);
1013 bool pci_dev_run_wake(struct pci_dev
*dev
);
1014 bool pci_check_pme_status(struct pci_dev
*dev
);
1015 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1017 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1020 return __pci_enable_wake(dev
, state
, false, enable
);
1023 /* PCI Virtual Channel */
1024 int pci_save_vc_state(struct pci_dev
*dev
);
1025 void pci_restore_vc_state(struct pci_dev
*dev
);
1026 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1028 /* For use by arch with custom probe code */
1029 void set_pcie_port_type(struct pci_dev
*pdev
);
1030 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1032 /* Functions for PCI Hotplug drivers to use */
1033 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1034 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1035 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1036 void pci_lock_rescan_remove(void);
1037 void pci_unlock_rescan_remove(void);
1039 /* Vital product data routines */
1040 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1041 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1043 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1044 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1045 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1046 void pci_bus_size_bridges(struct pci_bus
*bus
);
1047 int pci_claim_resource(struct pci_dev
*, int);
1048 void pci_assign_unassigned_resources(void);
1049 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1050 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1051 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1052 void pdev_enable_device(struct pci_dev
*);
1053 int pci_enable_resources(struct pci_dev
*, int mask
);
1054 void pci_fixup_irqs(u8 (*)(struct pci_dev
*, u8
*),
1055 int (*)(const struct pci_dev
*, u8
, u8
));
1056 #define HAVE_PCI_REQ_REGIONS 2
1057 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1058 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1059 void pci_release_regions(struct pci_dev
*);
1060 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1061 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1062 void pci_release_region(struct pci_dev
*, int);
1063 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1064 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1065 void pci_release_selected_regions(struct pci_dev
*, int);
1067 /* drivers/pci/bus.c */
1068 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1069 void pci_bus_put(struct pci_bus
*bus
);
1070 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1071 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1072 resource_size_t offset
);
1073 void pci_free_resource_list(struct list_head
*resources
);
1074 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
, unsigned int flags
);
1075 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1076 void pci_bus_remove_resources(struct pci_bus
*bus
);
1078 #define pci_bus_for_each_resource(bus, res, i) \
1080 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1083 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1084 struct resource
*res
, resource_size_t size
,
1085 resource_size_t align
, resource_size_t min
,
1086 unsigned long type_mask
,
1087 resource_size_t (*alignf
)(void *,
1088 const struct resource
*,
1093 static inline dma_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1095 struct pci_bus_region region
;
1097 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1098 return region
.start
;
1101 /* Proper probing supporting hot-pluggable devices */
1102 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1103 const char *mod_name
);
1106 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1108 #define pci_register_driver(driver) \
1109 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1111 void pci_unregister_driver(struct pci_driver
*dev
);
1114 * module_pci_driver() - Helper macro for registering a PCI driver
1115 * @__pci_driver: pci_driver struct
1117 * Helper macro for PCI drivers which do not do anything special in module
1118 * init/exit. This eliminates a lot of boilerplate. Each module may only
1119 * use this macro once, and calling it replaces module_init() and module_exit()
1121 #define module_pci_driver(__pci_driver) \
1122 module_driver(__pci_driver, pci_register_driver, \
1123 pci_unregister_driver)
1125 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1126 int pci_add_dynid(struct pci_driver
*drv
,
1127 unsigned int vendor
, unsigned int device
,
1128 unsigned int subvendor
, unsigned int subdevice
,
1129 unsigned int class, unsigned int class_mask
,
1130 unsigned long driver_data
);
1131 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1132 struct pci_dev
*dev
);
1133 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1136 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1138 int pci_cfg_space_size(struct pci_dev
*dev
);
1139 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1140 void pci_setup_bridge(struct pci_bus
*bus
);
1141 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1142 unsigned long type
);
1144 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1145 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1147 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1148 unsigned int command_bits
, u32 flags
);
1149 /* kmem_cache style wrapper around pci_alloc_consistent() */
1151 #include <linux/pci-dma.h>
1152 #include <linux/dmapool.h>
1154 #define pci_pool dma_pool
1155 #define pci_pool_create(name, pdev, size, align, allocation) \
1156 dma_pool_create(name, &pdev->dev, size, align, allocation)
1157 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1158 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1159 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1161 enum pci_dma_burst_strategy
{
1162 PCI_DMA_BURST_INFINITY
, /* make bursts as large as possible,
1163 strategy_parameter is N/A */
1164 PCI_DMA_BURST_BOUNDARY
, /* disconnect at every strategy_parameter
1166 PCI_DMA_BURST_MULTIPLE
, /* disconnect at some multiple of
1167 strategy_parameter byte boundaries */
1171 u32 vector
; /* kernel uses to write allocated vector */
1172 u16 entry
; /* driver uses to specify entry, OS writes */
1176 #ifdef CONFIG_PCI_MSI
1177 int pci_msi_vec_count(struct pci_dev
*dev
);
1178 void pci_msi_shutdown(struct pci_dev
*dev
);
1179 void pci_disable_msi(struct pci_dev
*dev
);
1180 int pci_msix_vec_count(struct pci_dev
*dev
);
1181 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
);
1182 void pci_msix_shutdown(struct pci_dev
*dev
);
1183 void pci_disable_msix(struct pci_dev
*dev
);
1184 void msi_remove_pci_irq_vectors(struct pci_dev
*dev
);
1185 void pci_restore_msi_state(struct pci_dev
*dev
);
1186 int pci_msi_enabled(void);
1187 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
);
1188 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1190 int rc
= pci_enable_msi_range(dev
, nvec
, nvec
);
1195 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1196 int minvec
, int maxvec
);
1197 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1198 struct msix_entry
*entries
, int nvec
)
1200 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1206 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1207 static inline void pci_msi_shutdown(struct pci_dev
*dev
) { }
1208 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1209 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1210 static inline int pci_enable_msix(struct pci_dev
*dev
,
1211 struct msix_entry
*entries
, int nvec
)
1213 static inline void pci_msix_shutdown(struct pci_dev
*dev
) { }
1214 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1215 static inline void msi_remove_pci_irq_vectors(struct pci_dev
*dev
) { }
1216 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1217 static inline int pci_msi_enabled(void) { return 0; }
1218 static inline int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
,
1221 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1223 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1224 struct msix_entry
*entries
, int minvec
, int maxvec
)
1226 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1227 struct msix_entry
*entries
, int nvec
)
1231 #ifdef CONFIG_PCIEPORTBUS
1232 extern bool pcie_ports_disabled
;
1233 extern bool pcie_ports_auto
;
1235 #define pcie_ports_disabled true
1236 #define pcie_ports_auto false
1239 #ifdef CONFIG_PCIEASPM
1240 bool pcie_aspm_support_enabled(void);
1242 static inline bool pcie_aspm_support_enabled(void) { return false; }
1245 #ifdef CONFIG_PCIEAER
1246 void pci_no_aer(void);
1247 bool pci_aer_available(void);
1249 static inline void pci_no_aer(void) { }
1250 static inline bool pci_aer_available(void) { return false; }
1253 #ifdef CONFIG_PCIE_ECRC
1254 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1255 void pcie_ecrc_get_policy(char *str
);
1257 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1258 static inline void pcie_ecrc_get_policy(char *str
) { }
1261 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1263 #ifdef CONFIG_HT_IRQ
1264 /* The functions a driver should call */
1265 int ht_create_irq(struct pci_dev
*dev
, int idx
);
1266 void ht_destroy_irq(unsigned int irq
);
1267 #endif /* CONFIG_HT_IRQ */
1269 void pci_cfg_access_lock(struct pci_dev
*dev
);
1270 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1271 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1274 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1275 * a PCI domain is defined to be a set of PCI buses which share
1276 * configuration space.
1278 #ifdef CONFIG_PCI_DOMAINS
1279 extern int pci_domains_supported
;
1281 enum { pci_domains_supported
= 0 };
1282 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1283 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1284 #endif /* CONFIG_PCI_DOMAINS */
1286 /* some architectures require additional setup to direct VGA traffic */
1287 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1288 unsigned int command_bits
, u32 flags
);
1289 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1291 #else /* CONFIG_PCI is not enabled */
1294 * If the system does not have PCI, clearly these return errors. Define
1295 * these as simple inline functions to avoid hair in drivers.
1298 #define _PCI_NOP(o, s, t) \
1299 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1301 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1303 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1304 _PCI_NOP(o, word, u16 x) \
1305 _PCI_NOP(o, dword, u32 x)
1306 _PCI_NOP_ALL(read
, *)
1307 _PCI_NOP_ALL(write
,)
1309 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1310 unsigned int device
,
1311 struct pci_dev
*from
)
1314 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1315 unsigned int device
,
1316 unsigned int ss_vendor
,
1317 unsigned int ss_device
,
1318 struct pci_dev
*from
)
1321 static inline struct pci_dev
*pci_get_class(unsigned int class,
1322 struct pci_dev
*from
)
1325 #define pci_dev_present(ids) (0)
1326 #define no_pci_devices() (1)
1327 #define pci_dev_put(dev) do { } while (0)
1329 static inline void pci_set_master(struct pci_dev
*dev
) { }
1330 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1331 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1332 static inline int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1334 static inline int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1336 static inline int pci_set_dma_max_seg_size(struct pci_dev
*dev
,
1339 static inline int pci_set_dma_seg_boundary(struct pci_dev
*dev
,
1342 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1344 static inline int __pci_register_driver(struct pci_driver
*drv
,
1345 struct module
*owner
)
1347 static inline int pci_register_driver(struct pci_driver
*drv
)
1349 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1350 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1352 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1355 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1358 /* Power management related routines */
1359 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1360 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1361 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1363 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1365 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1368 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1372 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1374 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1376 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1378 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1379 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1381 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1383 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1385 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1388 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1392 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1393 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1395 #define dev_is_pci(d) (false)
1396 #define dev_is_pf(d) (false)
1397 #define dev_num_vf(d) (0)
1398 #endif /* CONFIG_PCI */
1400 /* Include architecture-dependent settings and functions */
1402 #include <asm/pci.h>
1404 /* these helpers provide future and backwards compatibility
1405 * for accessing popular PCI BAR info */
1406 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1407 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1408 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1409 #define pci_resource_len(dev,bar) \
1410 ((pci_resource_start((dev), (bar)) == 0 && \
1411 pci_resource_end((dev), (bar)) == \
1412 pci_resource_start((dev), (bar))) ? 0 : \
1414 (pci_resource_end((dev), (bar)) - \
1415 pci_resource_start((dev), (bar)) + 1))
1417 /* Similar to the helpers above, these manipulate per-pci_dev
1418 * driver-specific data. They are really just a wrapper around
1419 * the generic device structure functions of these calls.
1421 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1423 return dev_get_drvdata(&pdev
->dev
);
1426 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1428 dev_set_drvdata(&pdev
->dev
, data
);
1431 /* If you want to know what to call your pci_dev, ask this function.
1432 * Again, it's a wrapper around the generic device.
1434 static inline const char *pci_name(const struct pci_dev
*pdev
)
1436 return dev_name(&pdev
->dev
);
1440 /* Some archs don't want to expose struct resource to userland as-is
1441 * in sysfs and /proc
1443 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1444 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1445 const struct resource
*rsrc
, resource_size_t
*start
,
1446 resource_size_t
*end
)
1448 *start
= rsrc
->start
;
1451 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1455 * The world is not perfect and supplies us with broken PCI devices.
1456 * For at least a part of these bugs we need a work-around, so both
1457 * generic (drivers/pci/quirks.c) and per-architecture code can define
1458 * fixup hooks to be called for particular buggy devices.
1462 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1463 u16 device
; /* You can use PCI_ANY_ID here of course */
1464 u32
class; /* You can use PCI_ANY_ID here too */
1465 unsigned int class_shift
; /* should be 0, 8, 16 */
1466 void (*hook
)(struct pci_dev
*dev
);
1469 enum pci_fixup_pass
{
1470 pci_fixup_early
, /* Before probing BARs */
1471 pci_fixup_header
, /* After reading configuration header */
1472 pci_fixup_final
, /* Final phase of device fixups */
1473 pci_fixup_enable
, /* pci_enable_device() time */
1474 pci_fixup_resume
, /* pci_device_resume() */
1475 pci_fixup_suspend
, /* pci_device_suspend */
1476 pci_fixup_resume_early
, /* pci_device_resume_early() */
1479 /* Anonymous variables would be nice... */
1480 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1481 class_shift, hook) \
1482 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1483 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1484 = { vendor, device, class, class_shift, hook };
1486 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1487 class_shift, hook) \
1488 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1489 hook, vendor, device, class, class_shift, hook)
1490 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1491 class_shift, hook) \
1492 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1493 hook, vendor, device, class, class_shift, hook)
1494 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1495 class_shift, hook) \
1496 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1497 hook, vendor, device, class, class_shift, hook)
1498 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1499 class_shift, hook) \
1500 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1501 hook, vendor, device, class, class_shift, hook)
1502 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1503 class_shift, hook) \
1504 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1505 resume##hook, vendor, device, class, \
1507 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1508 class_shift, hook) \
1509 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1510 resume_early##hook, vendor, device, \
1511 class, class_shift, hook)
1512 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1513 class_shift, hook) \
1514 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1515 suspend##hook, vendor, device, class, \
1518 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1519 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1520 hook, vendor, device, PCI_ANY_ID, 0, hook)
1521 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1522 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1523 hook, vendor, device, PCI_ANY_ID, 0, hook)
1524 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1525 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1526 hook, vendor, device, PCI_ANY_ID, 0, hook)
1527 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1528 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1529 hook, vendor, device, PCI_ANY_ID, 0, hook)
1530 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1531 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1532 resume##hook, vendor, device, \
1533 PCI_ANY_ID, 0, hook)
1534 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1535 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1536 resume_early##hook, vendor, device, \
1537 PCI_ANY_ID, 0, hook)
1538 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1539 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1540 suspend##hook, vendor, device, \
1541 PCI_ANY_ID, 0, hook)
1543 #ifdef CONFIG_PCI_QUIRKS
1544 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1545 struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
);
1546 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1547 void pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1549 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1550 struct pci_dev
*dev
) { }
1551 static inline struct pci_dev
*pci_get_dma_source(struct pci_dev
*dev
)
1553 return pci_dev_get(dev
);
1555 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1560 static inline void pci_dev_specific_enable_acs(struct pci_dev
*dev
) { }
1563 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1564 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1565 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1566 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1567 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1569 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1571 extern int pci_pci_problems
;
1572 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1573 #define PCIPCI_TRITON 2
1574 #define PCIPCI_NATOMA 4
1575 #define PCIPCI_VIAETBF 8
1576 #define PCIPCI_VSFX 16
1577 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1578 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1580 extern unsigned long pci_cardbus_io_size
;
1581 extern unsigned long pci_cardbus_mem_size
;
1582 extern u8 pci_dfl_cache_line_size
;
1583 extern u8 pci_cache_line_size
;
1585 extern unsigned long pci_hotplug_io_size
;
1586 extern unsigned long pci_hotplug_mem_size
;
1588 /* Architecture-specific versions may override these (weak) */
1589 void pcibios_disable_device(struct pci_dev
*dev
);
1590 void pcibios_set_master(struct pci_dev
*dev
);
1591 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1592 enum pcie_reset_state state
);
1593 int pcibios_add_device(struct pci_dev
*dev
);
1594 void pcibios_release_device(struct pci_dev
*dev
);
1595 void pcibios_penalize_isa_irq(int irq
, int active
);
1597 #ifdef CONFIG_HIBERNATE_CALLBACKS
1598 extern struct dev_pm_ops pcibios_pm_ops
;
1601 #ifdef CONFIG_PCI_MMCONFIG
1602 void __init
pci_mmcfg_early_init(void);
1603 void __init
pci_mmcfg_late_init(void);
1605 static inline void pci_mmcfg_early_init(void) { }
1606 static inline void pci_mmcfg_late_init(void) { }
1609 int pci_ext_cfg_avail(void);
1611 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1613 #ifdef CONFIG_PCI_IOV
1614 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1615 void pci_disable_sriov(struct pci_dev
*dev
);
1616 int pci_num_vf(struct pci_dev
*dev
);
1617 int pci_vfs_assigned(struct pci_dev
*dev
);
1618 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1619 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1621 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1623 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
1624 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
1625 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1627 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1629 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1633 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1634 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
1635 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
1639 * pci_pcie_cap - get the saved PCIe capability offset
1642 * PCIe capability offset is calculated at PCI device initialization
1643 * time and saved in the data structure. This function returns saved
1644 * PCIe capability offset. Using this instead of pci_find_capability()
1645 * reduces unnecessary search in the PCI configuration space. If you
1646 * need to calculate PCIe capability offset from raw device for some
1647 * reasons, please use pci_find_capability() instead.
1649 static inline int pci_pcie_cap(struct pci_dev
*dev
)
1651 return dev
->pcie_cap
;
1655 * pci_is_pcie - check if the PCI device is PCI Express capable
1658 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1660 static inline bool pci_is_pcie(struct pci_dev
*dev
)
1662 return pci_pcie_cap(dev
);
1666 * pcie_caps_reg - get the PCIe Capabilities Register
1669 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
1671 return dev
->pcie_flags_reg
;
1675 * pci_pcie_type - get the PCIe device/port type
1678 static inline int pci_pcie_type(const struct pci_dev
*dev
)
1680 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
1683 void pci_request_acs(void);
1684 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
1685 bool pci_acs_path_enabled(struct pci_dev
*start
,
1686 struct pci_dev
*end
, u16 acs_flags
);
1688 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1689 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1691 /* Large Resource Data Type Tag Item Names */
1692 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1693 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1694 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1696 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1697 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1698 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1700 /* Small Resource Data Type Tag Item Names */
1701 #define PCI_VPD_STIN_END 0x78 /* End */
1703 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1705 #define PCI_VPD_SRDT_TIN_MASK 0x78
1706 #define PCI_VPD_SRDT_LEN_MASK 0x07
1708 #define PCI_VPD_LRDT_TAG_SIZE 3
1709 #define PCI_VPD_SRDT_TAG_SIZE 1
1711 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1713 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1714 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1715 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1716 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1719 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1720 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1722 * Returns the extracted Large Resource Data Type length.
1724 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
1726 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
1730 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1731 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1733 * Returns the extracted Small Resource Data Type length.
1735 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
1737 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
1741 * pci_vpd_info_field_size - Extracts the information field length
1742 * @lrdt: Pointer to the beginning of an information field header
1744 * Returns the extracted information field length.
1746 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
1748 return info_field
[2];
1752 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1753 * @buf: Pointer to buffered vpd data
1754 * @off: The offset into the buffer at which to begin the search
1755 * @len: The length of the vpd buffer
1756 * @rdt: The Resource Data Type to search for
1758 * Returns the index where the Resource Data Type was found or
1759 * -ENOENT otherwise.
1761 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
1764 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1765 * @buf: Pointer to buffered vpd data
1766 * @off: The offset into the buffer at which to begin the search
1767 * @len: The length of the buffer area, relative to off, in which to search
1768 * @kw: The keyword to search for
1770 * Returns the index where the information field keyword was found or
1771 * -ENOENT otherwise.
1773 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
1774 unsigned int len
, const char *kw
);
1776 /* PCI <-> OF binding helpers */
1779 void pci_set_of_node(struct pci_dev
*dev
);
1780 void pci_release_of_node(struct pci_dev
*dev
);
1781 void pci_set_bus_of_node(struct pci_bus
*bus
);
1782 void pci_release_bus_of_node(struct pci_bus
*bus
);
1784 /* Arch may override this (weak) */
1785 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
1787 static inline struct device_node
*
1788 pci_device_to_OF_node(const struct pci_dev
*pdev
)
1790 return pdev
? pdev
->dev
.of_node
: NULL
;
1793 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
1795 return bus
? bus
->dev
.of_node
: NULL
;
1798 #else /* CONFIG_OF */
1799 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
1800 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
1801 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
1802 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
1803 #endif /* CONFIG_OF */
1806 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
1808 return pdev
->dev
.archdata
.edev
;
1813 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1814 * @pdev: the PCI device
1816 * if the device is PCIE, return NULL
1817 * if the device isn't connected to a PCIe bridge (that is its parent is a
1818 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1821 struct pci_dev
*pci_find_upstream_pcie_bridge(struct pci_dev
*pdev
);
1823 #endif /* LINUX_PCI_H */