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x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded
[deliverable/linux.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_BUS_WAIT 50
130
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
134 */
135 typedef unsigned int __bitwise pci_channel_state_t;
136
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
140
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
143
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
146 };
147
148 typedef unsigned int __bitwise pcie_reset_state_t;
149
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
153
154 /* Use #PERST to reset PCI-E device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
156
157 /* Use PCI-E Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
159 };
160
161 typedef unsigned short __bitwise pci_dev_flags_t;
162 enum pci_dev_flags {
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
164 * generation too.
165 */
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
169 };
170
171 enum pci_irq_reroute_variant {
172 INTEL_IRQ_REROUTE_VARIANT = 1,
173 MAX_IRQ_REROUTE_VARIANTS = 3
174 };
175
176 typedef unsigned short __bitwise pci_bus_flags_t;
177 enum pci_bus_flags {
178 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
179 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
180 };
181
182 struct pci_cap_saved_state {
183 struct hlist_node next;
184 char cap_nr;
185 u32 data[0];
186 };
187
188 struct pcie_link_state;
189 struct pci_vpd;
190 struct pci_sriov;
191
192 /*
193 * The pci_dev structure is used to describe PCI devices.
194 */
195 struct pci_dev {
196 struct list_head bus_list; /* node in per-bus list */
197 struct pci_bus *bus; /* bus this device is on */
198 struct pci_bus *subordinate; /* bus this device bridges to */
199
200 void *sysdata; /* hook for sys-specific extension */
201 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
202 struct pci_slot *slot; /* Physical slot this device is in */
203
204 unsigned int devfn; /* encoded device & function index */
205 unsigned short vendor;
206 unsigned short device;
207 unsigned short subsystem_vendor;
208 unsigned short subsystem_device;
209 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
210 u8 revision; /* PCI revision, low byte of class word */
211 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
212 u8 pcie_type; /* PCI-E device/port type */
213 u8 rom_base_reg; /* which config register controls the ROM */
214 u8 pin; /* which interrupt pin this device uses */
215
216 struct pci_driver *driver; /* which driver has allocated this device */
217 u64 dma_mask; /* Mask of the bits of bus address this
218 device implements. Normally this is
219 0xffffffff. You only need to change
220 this if your device has broken DMA
221 or supports 64-bit transfers. */
222
223 struct device_dma_parameters dma_parms;
224
225 pci_power_t current_state; /* Current operating state. In ACPI-speak,
226 this is D0-D3, D0 being fully functional,
227 and D3 being off. */
228 int pm_cap; /* PM capability offset in the
229 configuration space */
230 unsigned int pme_support:5; /* Bitmask of states from which PME#
231 can be generated */
232 unsigned int d1_support:1; /* Low power state D1 is supported */
233 unsigned int d2_support:1; /* Low power state D2 is supported */
234 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
235
236 #ifdef CONFIG_PCIEASPM
237 struct pcie_link_state *link_state; /* ASPM link state. */
238 #endif
239
240 pci_channel_state_t error_state; /* current connectivity state */
241 struct device dev; /* Generic device interface */
242
243 int cfg_size; /* Size of configuration space */
244
245 /*
246 * Instead of touching interrupt line and base address registers
247 * directly, use the values stored here. They might be different!
248 */
249 unsigned int irq;
250 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
251
252 /* These fields are used by common fixups */
253 unsigned int transparent:1; /* Transparent PCI bridge */
254 unsigned int multifunction:1;/* Part of multi-function device */
255 /* keep track of device state */
256 unsigned int is_added:1;
257 unsigned int is_busmaster:1; /* device is busmaster */
258 unsigned int no_msi:1; /* device may not use msi */
259 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
260 unsigned int broken_parity_status:1; /* Device generates false positive parity */
261 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
262 unsigned int msi_enabled:1;
263 unsigned int msix_enabled:1;
264 unsigned int ari_enabled:1; /* ARI forwarding */
265 unsigned int is_managed:1;
266 unsigned int is_pcie:1;
267 unsigned int state_saved:1;
268 unsigned int is_physfn:1;
269 unsigned int is_virtfn:1;
270 pci_dev_flags_t dev_flags;
271 atomic_t enable_cnt; /* pci_enable_device has been called */
272
273 u32 saved_config_space[16]; /* config space saved at suspend time */
274 struct hlist_head saved_cap_space;
275 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
276 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
277 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
278 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
279 #ifdef CONFIG_PCI_MSI
280 struct list_head msi_list;
281 #endif
282 struct pci_vpd *vpd;
283 #ifdef CONFIG_PCI_IOV
284 union {
285 struct pci_sriov *sriov; /* SR-IOV capability related */
286 struct pci_dev *physfn; /* the PF this VF is associated with */
287 };
288 #endif
289 };
290
291 extern struct pci_dev *alloc_pci_dev(void);
292
293 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
294 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
295 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
296
297 static inline int pci_channel_offline(struct pci_dev *pdev)
298 {
299 return (pdev->error_state != pci_channel_io_normal);
300 }
301
302 static inline struct pci_cap_saved_state *pci_find_saved_cap(
303 struct pci_dev *pci_dev, char cap)
304 {
305 struct pci_cap_saved_state *tmp;
306 struct hlist_node *pos;
307
308 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
309 if (tmp->cap_nr == cap)
310 return tmp;
311 }
312 return NULL;
313 }
314
315 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
316 struct pci_cap_saved_state *new_cap)
317 {
318 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
319 }
320
321 #ifndef PCI_BUS_NUM_RESOURCES
322 #define PCI_BUS_NUM_RESOURCES 16
323 #endif
324
325 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
326
327 struct pci_bus {
328 struct list_head node; /* node in list of buses */
329 struct pci_bus *parent; /* parent bus this bridge is on */
330 struct list_head children; /* list of child buses */
331 struct list_head devices; /* list of devices on this bus */
332 struct pci_dev *self; /* bridge device as seen by parent */
333 struct list_head slots; /* list of slots on this bus */
334 struct resource *resource[PCI_BUS_NUM_RESOURCES];
335 /* address space routed to this bus */
336
337 struct pci_ops *ops; /* configuration access functions */
338 void *sysdata; /* hook for sys-specific extension */
339 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
340
341 unsigned char number; /* bus number */
342 unsigned char primary; /* number of primary bridge */
343 unsigned char secondary; /* number of secondary bridge */
344 unsigned char subordinate; /* max number of subordinate buses */
345
346 char name[48];
347
348 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
349 pci_bus_flags_t bus_flags; /* Inherited by child busses */
350 struct device *bridge;
351 struct device dev;
352 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
353 struct bin_attribute *legacy_mem; /* legacy mem */
354 unsigned int is_added:1;
355 };
356
357 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
358 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
359
360 /*
361 * Returns true if the pci bus is root (behind host-pci bridge),
362 * false otherwise
363 */
364 static inline bool pci_is_root_bus(struct pci_bus *pbus)
365 {
366 return !(pbus->parent);
367 }
368
369 #ifdef CONFIG_PCI_MSI
370 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
371 {
372 return pci_dev->msi_enabled || pci_dev->msix_enabled;
373 }
374 #else
375 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
376 #endif
377
378 /*
379 * Error values that may be returned by PCI functions.
380 */
381 #define PCIBIOS_SUCCESSFUL 0x00
382 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
383 #define PCIBIOS_BAD_VENDOR_ID 0x83
384 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
385 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
386 #define PCIBIOS_SET_FAILED 0x88
387 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
388
389 /* Low-level architecture-dependent routines */
390
391 struct pci_ops {
392 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
393 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
394 };
395
396 /*
397 * ACPI needs to be able to access PCI config space before we've done a
398 * PCI bus scan and created pci_bus structures.
399 */
400 extern int raw_pci_read(unsigned int domain, unsigned int bus,
401 unsigned int devfn, int reg, int len, u32 *val);
402 extern int raw_pci_write(unsigned int domain, unsigned int bus,
403 unsigned int devfn, int reg, int len, u32 val);
404
405 struct pci_bus_region {
406 resource_size_t start;
407 resource_size_t end;
408 };
409
410 struct pci_dynids {
411 spinlock_t lock; /* protects list, index */
412 struct list_head list; /* for IDs added at runtime */
413 };
414
415 /* ---------------------------------------------------------------- */
416 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
417 * a set of callbacks in struct pci_error_handlers, then that device driver
418 * will be notified of PCI bus errors, and will be driven to recovery
419 * when an error occurs.
420 */
421
422 typedef unsigned int __bitwise pci_ers_result_t;
423
424 enum pci_ers_result {
425 /* no result/none/not supported in device driver */
426 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
427
428 /* Device driver can recover without slot reset */
429 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
430
431 /* Device driver wants slot to be reset. */
432 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
433
434 /* Device has completely failed, is unrecoverable */
435 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
436
437 /* Device driver is fully recovered and operational */
438 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
439 };
440
441 /* PCI bus error event callbacks */
442 struct pci_error_handlers {
443 /* PCI bus error detected on this device */
444 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
445 enum pci_channel_state error);
446
447 /* MMIO has been re-enabled, but not DMA */
448 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
449
450 /* PCI Express link has been reset */
451 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
452
453 /* PCI slot has been reset */
454 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
455
456 /* Device driver may resume normal operations */
457 void (*resume)(struct pci_dev *dev);
458 };
459
460 /* ---------------------------------------------------------------- */
461
462 struct module;
463 struct pci_driver {
464 struct list_head node;
465 char *name;
466 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
467 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
468 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
469 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
470 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
471 int (*resume_early) (struct pci_dev *dev);
472 int (*resume) (struct pci_dev *dev); /* Device woken up */
473 void (*shutdown) (struct pci_dev *dev);
474 struct pci_error_handlers *err_handler;
475 struct device_driver driver;
476 struct pci_dynids dynids;
477 };
478
479 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
480
481 /**
482 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
483 * @_table: device table name
484 *
485 * This macro is used to create a struct pci_device_id array (a device table)
486 * in a generic manner.
487 */
488 #define DEFINE_PCI_DEVICE_TABLE(_table) \
489 const struct pci_device_id _table[] __devinitconst
490
491 /**
492 * PCI_DEVICE - macro used to describe a specific pci device
493 * @vend: the 16 bit PCI Vendor ID
494 * @dev: the 16 bit PCI Device ID
495 *
496 * This macro is used to create a struct pci_device_id that matches a
497 * specific device. The subvendor and subdevice fields will be set to
498 * PCI_ANY_ID.
499 */
500 #define PCI_DEVICE(vend,dev) \
501 .vendor = (vend), .device = (dev), \
502 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
503
504 /**
505 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
506 * @dev_class: the class, subclass, prog-if triple for this device
507 * @dev_class_mask: the class mask for this device
508 *
509 * This macro is used to create a struct pci_device_id that matches a
510 * specific PCI class. The vendor, device, subvendor, and subdevice
511 * fields will be set to PCI_ANY_ID.
512 */
513 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
514 .class = (dev_class), .class_mask = (dev_class_mask), \
515 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
516 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
517
518 /**
519 * PCI_VDEVICE - macro used to describe a specific pci device in short form
520 * @vendor: the vendor name
521 * @device: the 16 bit PCI Device ID
522 *
523 * This macro is used to create a struct pci_device_id that matches a
524 * specific PCI device. The subvendor, and subdevice fields will be set
525 * to PCI_ANY_ID. The macro allows the next field to follow as the device
526 * private data.
527 */
528
529 #define PCI_VDEVICE(vendor, device) \
530 PCI_VENDOR_ID_##vendor, (device), \
531 PCI_ANY_ID, PCI_ANY_ID, 0, 0
532
533 /* these external functions are only available when PCI support is enabled */
534 #ifdef CONFIG_PCI
535
536 extern struct bus_type pci_bus_type;
537
538 /* Do NOT directly access these two variables, unless you are arch specific pci
539 * code, or pci core code. */
540 extern struct list_head pci_root_buses; /* list of all known PCI buses */
541 /* Some device drivers need know if pci is initiated */
542 extern int no_pci_devices(void);
543
544 void pcibios_fixup_bus(struct pci_bus *);
545 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
546 char *pcibios_setup(char *str);
547
548 /* Used only when drivers/pci/setup.c is used */
549 void pcibios_align_resource(void *, struct resource *, resource_size_t,
550 resource_size_t);
551 void pcibios_update_irq(struct pci_dev *, int irq);
552
553 /* Generic PCI functions used internally */
554
555 extern struct pci_bus *pci_find_bus(int domain, int busnr);
556 void pci_bus_add_devices(const struct pci_bus *bus);
557 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
558 struct pci_ops *ops, void *sysdata);
559 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
560 void *sysdata)
561 {
562 struct pci_bus *root_bus;
563 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
564 if (root_bus)
565 pci_bus_add_devices(root_bus);
566 return root_bus;
567 }
568 struct pci_bus *pci_create_bus(struct device *parent, int bus,
569 struct pci_ops *ops, void *sysdata);
570 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
571 int busnr);
572 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
573 const char *name,
574 struct hotplug_slot *hotplug);
575 void pci_destroy_slot(struct pci_slot *slot);
576 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
577 int pci_scan_slot(struct pci_bus *bus, int devfn);
578 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
579 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
580 unsigned int pci_scan_child_bus(struct pci_bus *bus);
581 int __must_check pci_bus_add_device(struct pci_dev *dev);
582 void pci_read_bridge_bases(struct pci_bus *child);
583 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
584 struct resource *res);
585 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
586 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
587 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
588 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
589 extern void pci_dev_put(struct pci_dev *dev);
590 extern void pci_remove_bus(struct pci_bus *b);
591 extern void pci_remove_bus_device(struct pci_dev *dev);
592 extern void pci_stop_bus_device(struct pci_dev *dev);
593 void pci_setup_cardbus(struct pci_bus *bus);
594 extern void pci_sort_breadthfirst(void);
595
596 /* Generic PCI functions exported to card drivers */
597
598 #ifdef CONFIG_PCI_LEGACY
599 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
600 unsigned int device,
601 struct pci_dev *from);
602 #endif /* CONFIG_PCI_LEGACY */
603
604 enum pci_lost_interrupt_reason {
605 PCI_LOST_IRQ_NO_INFORMATION = 0,
606 PCI_LOST_IRQ_DISABLE_MSI,
607 PCI_LOST_IRQ_DISABLE_MSIX,
608 PCI_LOST_IRQ_DISABLE_ACPI,
609 };
610 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
611 int pci_find_capability(struct pci_dev *dev, int cap);
612 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
613 int pci_find_ext_capability(struct pci_dev *dev, int cap);
614 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
615 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
616 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
617
618 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
619 struct pci_dev *from);
620 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
621 unsigned int ss_vendor, unsigned int ss_device,
622 struct pci_dev *from);
623 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
624 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
625 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
626 int pci_dev_present(const struct pci_device_id *ids);
627
628 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
629 int where, u8 *val);
630 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
631 int where, u16 *val);
632 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
633 int where, u32 *val);
634 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
635 int where, u8 val);
636 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
637 int where, u16 val);
638 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
639 int where, u32 val);
640 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
641
642 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
643 {
644 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
645 }
646 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
647 {
648 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
649 }
650 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
651 u32 *val)
652 {
653 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
654 }
655 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
656 {
657 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
658 }
659 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
660 {
661 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
662 }
663 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
664 u32 val)
665 {
666 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
667 }
668
669 int __must_check pci_enable_device(struct pci_dev *dev);
670 int __must_check pci_enable_device_io(struct pci_dev *dev);
671 int __must_check pci_enable_device_mem(struct pci_dev *dev);
672 int __must_check pci_reenable_device(struct pci_dev *);
673 int __must_check pcim_enable_device(struct pci_dev *pdev);
674 void pcim_pin_device(struct pci_dev *pdev);
675
676 static inline int pci_is_enabled(struct pci_dev *pdev)
677 {
678 return (atomic_read(&pdev->enable_cnt) > 0);
679 }
680
681 static inline int pci_is_managed(struct pci_dev *pdev)
682 {
683 return pdev->is_managed;
684 }
685
686 void pci_disable_device(struct pci_dev *dev);
687 void pci_set_master(struct pci_dev *dev);
688 void pci_clear_master(struct pci_dev *dev);
689 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
690 #define HAVE_PCI_SET_MWI
691 int __must_check pci_set_mwi(struct pci_dev *dev);
692 int pci_try_set_mwi(struct pci_dev *dev);
693 void pci_clear_mwi(struct pci_dev *dev);
694 void pci_intx(struct pci_dev *dev, int enable);
695 void pci_msi_off(struct pci_dev *dev);
696 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
697 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
698 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
699 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
700 int pcix_get_max_mmrbc(struct pci_dev *dev);
701 int pcix_get_mmrbc(struct pci_dev *dev);
702 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
703 int pcie_get_readrq(struct pci_dev *dev);
704 int pcie_set_readrq(struct pci_dev *dev, int rq);
705 int __pci_reset_function(struct pci_dev *dev);
706 int pci_reset_function(struct pci_dev *dev);
707 void pci_update_resource(struct pci_dev *dev, int resno);
708 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
709 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
710
711 /* ROM control related routines */
712 int pci_enable_rom(struct pci_dev *pdev);
713 void pci_disable_rom(struct pci_dev *pdev);
714 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
715 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
716 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
717
718 /* Power management related routines */
719 int pci_save_state(struct pci_dev *dev);
720 int pci_restore_state(struct pci_dev *dev);
721 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
722 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
723 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
724 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
725 void pci_pme_active(struct pci_dev *dev, bool enable);
726 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
727 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
728 pci_power_t pci_target_state(struct pci_dev *dev);
729 int pci_prepare_to_sleep(struct pci_dev *dev);
730 int pci_back_from_sleep(struct pci_dev *dev);
731
732 /* Functions for PCI Hotplug drivers to use */
733 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
734 #ifdef CONFIG_HOTPLUG
735 unsigned int pci_rescan_bus(struct pci_bus *bus);
736 #endif
737
738 /* Vital product data routines */
739 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
740 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
741 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
742
743 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
744 void pci_bus_assign_resources(const struct pci_bus *bus);
745 void pci_bus_size_bridges(struct pci_bus *bus);
746 int pci_claim_resource(struct pci_dev *, int);
747 void pci_assign_unassigned_resources(void);
748 void pdev_enable_device(struct pci_dev *);
749 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
750 int pci_enable_resources(struct pci_dev *, int mask);
751 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
752 int (*)(struct pci_dev *, u8, u8));
753 #define HAVE_PCI_REQ_REGIONS 2
754 int __must_check pci_request_regions(struct pci_dev *, const char *);
755 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
756 void pci_release_regions(struct pci_dev *);
757 int __must_check pci_request_region(struct pci_dev *, int, const char *);
758 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
759 void pci_release_region(struct pci_dev *, int);
760 int pci_request_selected_regions(struct pci_dev *, int, const char *);
761 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
762 void pci_release_selected_regions(struct pci_dev *, int);
763
764 /* drivers/pci/bus.c */
765 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
766 struct resource *res, resource_size_t size,
767 resource_size_t align, resource_size_t min,
768 unsigned int type_mask,
769 void (*alignf)(void *, struct resource *,
770 resource_size_t, resource_size_t),
771 void *alignf_data);
772 void pci_enable_bridges(struct pci_bus *bus);
773
774 /* Proper probing supporting hot-pluggable devices */
775 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
776 const char *mod_name);
777
778 /*
779 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
780 */
781 #define pci_register_driver(driver) \
782 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
783
784 void pci_unregister_driver(struct pci_driver *dev);
785 void pci_remove_behind_bridge(struct pci_dev *dev);
786 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
787 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
788 struct pci_dev *dev);
789 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
790 int pass);
791
792 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
793 void *userdata);
794 int pci_cfg_space_size_ext(struct pci_dev *dev);
795 int pci_cfg_space_size(struct pci_dev *dev);
796 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
797
798 /* kmem_cache style wrapper around pci_alloc_consistent() */
799
800 #include <linux/dmapool.h>
801
802 #define pci_pool dma_pool
803 #define pci_pool_create(name, pdev, size, align, allocation) \
804 dma_pool_create(name, &pdev->dev, size, align, allocation)
805 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
806 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
807 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
808
809 enum pci_dma_burst_strategy {
810 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
811 strategy_parameter is N/A */
812 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
813 byte boundaries */
814 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
815 strategy_parameter byte boundaries */
816 };
817
818 struct msix_entry {
819 u32 vector; /* kernel uses to write allocated vector */
820 u16 entry; /* driver uses to specify entry, OS writes */
821 };
822
823
824 #ifndef CONFIG_PCI_MSI
825 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
826 {
827 return -1;
828 }
829
830 static inline void pci_msi_shutdown(struct pci_dev *dev)
831 { }
832 static inline void pci_disable_msi(struct pci_dev *dev)
833 { }
834
835 static inline int pci_msix_table_size(struct pci_dev *dev)
836 {
837 return 0;
838 }
839 static inline int pci_enable_msix(struct pci_dev *dev,
840 struct msix_entry *entries, int nvec)
841 {
842 return -1;
843 }
844
845 static inline void pci_msix_shutdown(struct pci_dev *dev)
846 { }
847 static inline void pci_disable_msix(struct pci_dev *dev)
848 { }
849
850 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
851 { }
852
853 static inline void pci_restore_msi_state(struct pci_dev *dev)
854 { }
855 static inline int pci_msi_enabled(void)
856 {
857 return 0;
858 }
859 #else
860 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
861 extern void pci_msi_shutdown(struct pci_dev *dev);
862 extern void pci_disable_msi(struct pci_dev *dev);
863 extern int pci_msix_table_size(struct pci_dev *dev);
864 extern int pci_enable_msix(struct pci_dev *dev,
865 struct msix_entry *entries, int nvec);
866 extern void pci_msix_shutdown(struct pci_dev *dev);
867 extern void pci_disable_msix(struct pci_dev *dev);
868 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
869 extern void pci_restore_msi_state(struct pci_dev *dev);
870 extern int pci_msi_enabled(void);
871 #endif
872
873 #ifndef CONFIG_PCIEASPM
874 static inline int pcie_aspm_enabled(void)
875 {
876 return 0;
877 }
878 #else
879 extern int pcie_aspm_enabled(void);
880 #endif
881
882 #ifndef CONFIG_PCIE_ECRC
883 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
884 {
885 return;
886 }
887 static inline void pcie_ecrc_get_policy(char *str) {};
888 #else
889 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
890 extern void pcie_ecrc_get_policy(char *str);
891 #endif
892
893 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
894
895 #ifdef CONFIG_HT_IRQ
896 /* The functions a driver should call */
897 int ht_create_irq(struct pci_dev *dev, int idx);
898 void ht_destroy_irq(unsigned int irq);
899 #endif /* CONFIG_HT_IRQ */
900
901 extern void pci_block_user_cfg_access(struct pci_dev *dev);
902 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
903
904 /*
905 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
906 * a PCI domain is defined to be a set of PCI busses which share
907 * configuration space.
908 */
909 #ifdef CONFIG_PCI_DOMAINS
910 extern int pci_domains_supported;
911 #else
912 enum { pci_domains_supported = 0 };
913 static inline int pci_domain_nr(struct pci_bus *bus)
914 {
915 return 0;
916 }
917
918 static inline int pci_proc_domain(struct pci_bus *bus)
919 {
920 return 0;
921 }
922 #endif /* CONFIG_PCI_DOMAINS */
923
924 #else /* CONFIG_PCI is not enabled */
925
926 /*
927 * If the system does not have PCI, clearly these return errors. Define
928 * these as simple inline functions to avoid hair in drivers.
929 */
930
931 #define _PCI_NOP(o, s, t) \
932 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
933 int where, t val) \
934 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
935
936 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
937 _PCI_NOP(o, word, u16 x) \
938 _PCI_NOP(o, dword, u32 x)
939 _PCI_NOP_ALL(read, *)
940 _PCI_NOP_ALL(write,)
941
942 static inline struct pci_dev *pci_find_device(unsigned int vendor,
943 unsigned int device,
944 struct pci_dev *from)
945 {
946 return NULL;
947 }
948
949 static inline struct pci_dev *pci_get_device(unsigned int vendor,
950 unsigned int device,
951 struct pci_dev *from)
952 {
953 return NULL;
954 }
955
956 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
957 unsigned int device,
958 unsigned int ss_vendor,
959 unsigned int ss_device,
960 struct pci_dev *from)
961 {
962 return NULL;
963 }
964
965 static inline struct pci_dev *pci_get_class(unsigned int class,
966 struct pci_dev *from)
967 {
968 return NULL;
969 }
970
971 #define pci_dev_present(ids) (0)
972 #define no_pci_devices() (1)
973 #define pci_dev_put(dev) do { } while (0)
974
975 static inline void pci_set_master(struct pci_dev *dev)
976 { }
977
978 static inline int pci_enable_device(struct pci_dev *dev)
979 {
980 return -EIO;
981 }
982
983 static inline void pci_disable_device(struct pci_dev *dev)
984 { }
985
986 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
987 {
988 return -EIO;
989 }
990
991 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
992 {
993 return -EIO;
994 }
995
996 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
997 unsigned int size)
998 {
999 return -EIO;
1000 }
1001
1002 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1003 unsigned long mask)
1004 {
1005 return -EIO;
1006 }
1007
1008 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1009 {
1010 return -EBUSY;
1011 }
1012
1013 static inline int __pci_register_driver(struct pci_driver *drv,
1014 struct module *owner)
1015 {
1016 return 0;
1017 }
1018
1019 static inline int pci_register_driver(struct pci_driver *drv)
1020 {
1021 return 0;
1022 }
1023
1024 static inline void pci_unregister_driver(struct pci_driver *drv)
1025 { }
1026
1027 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1028 {
1029 return 0;
1030 }
1031
1032 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1033 int cap)
1034 {
1035 return 0;
1036 }
1037
1038 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1039 {
1040 return 0;
1041 }
1042
1043 /* Power management related routines */
1044 static inline int pci_save_state(struct pci_dev *dev)
1045 {
1046 return 0;
1047 }
1048
1049 static inline int pci_restore_state(struct pci_dev *dev)
1050 {
1051 return 0;
1052 }
1053
1054 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1055 {
1056 return 0;
1057 }
1058
1059 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1060 pm_message_t state)
1061 {
1062 return PCI_D0;
1063 }
1064
1065 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1066 int enable)
1067 {
1068 return 0;
1069 }
1070
1071 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1072 {
1073 return -EIO;
1074 }
1075
1076 static inline void pci_release_regions(struct pci_dev *dev)
1077 { }
1078
1079 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1080
1081 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1082 { }
1083
1084 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1085 { }
1086
1087 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1088 { return NULL; }
1089
1090 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1091 unsigned int devfn)
1092 { return NULL; }
1093
1094 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1095 unsigned int devfn)
1096 { return NULL; }
1097
1098 #endif /* CONFIG_PCI */
1099
1100 /* Include architecture-dependent settings and functions */
1101
1102 #include <asm/pci.h>
1103
1104 #ifndef PCIBIOS_MAX_MEM_32
1105 #define PCIBIOS_MAX_MEM_32 (-1)
1106 #endif
1107
1108 /* these helpers provide future and backwards compatibility
1109 * for accessing popular PCI BAR info */
1110 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1111 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1112 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1113 #define pci_resource_len(dev,bar) \
1114 ((pci_resource_start((dev), (bar)) == 0 && \
1115 pci_resource_end((dev), (bar)) == \
1116 pci_resource_start((dev), (bar))) ? 0 : \
1117 \
1118 (pci_resource_end((dev), (bar)) - \
1119 pci_resource_start((dev), (bar)) + 1))
1120
1121 /* Similar to the helpers above, these manipulate per-pci_dev
1122 * driver-specific data. They are really just a wrapper around
1123 * the generic device structure functions of these calls.
1124 */
1125 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1126 {
1127 return dev_get_drvdata(&pdev->dev);
1128 }
1129
1130 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1131 {
1132 dev_set_drvdata(&pdev->dev, data);
1133 }
1134
1135 /* If you want to know what to call your pci_dev, ask this function.
1136 * Again, it's a wrapper around the generic device.
1137 */
1138 static inline const char *pci_name(struct pci_dev *pdev)
1139 {
1140 return dev_name(&pdev->dev);
1141 }
1142
1143
1144 /* Some archs don't want to expose struct resource to userland as-is
1145 * in sysfs and /proc
1146 */
1147 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1148 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1149 const struct resource *rsrc, resource_size_t *start,
1150 resource_size_t *end)
1151 {
1152 *start = rsrc->start;
1153 *end = rsrc->end;
1154 }
1155 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1156
1157
1158 /*
1159 * The world is not perfect and supplies us with broken PCI devices.
1160 * For at least a part of these bugs we need a work-around, so both
1161 * generic (drivers/pci/quirks.c) and per-architecture code can define
1162 * fixup hooks to be called for particular buggy devices.
1163 */
1164
1165 struct pci_fixup {
1166 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1167 void (*hook)(struct pci_dev *dev);
1168 };
1169
1170 enum pci_fixup_pass {
1171 pci_fixup_early, /* Before probing BARs */
1172 pci_fixup_header, /* After reading configuration header */
1173 pci_fixup_final, /* Final phase of device fixups */
1174 pci_fixup_enable, /* pci_enable_device() time */
1175 pci_fixup_resume, /* pci_device_resume() */
1176 pci_fixup_suspend, /* pci_device_suspend */
1177 pci_fixup_resume_early, /* pci_device_resume_early() */
1178 };
1179
1180 /* Anonymous variables would be nice... */
1181 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1182 static const struct pci_fixup __pci_fixup_##name __used \
1183 __attribute__((__section__(#section))) = { vendor, device, hook };
1184 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1185 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1186 vendor##device##hook, vendor, device, hook)
1187 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1188 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1189 vendor##device##hook, vendor, device, hook)
1190 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1191 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1192 vendor##device##hook, vendor, device, hook)
1193 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1194 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1195 vendor##device##hook, vendor, device, hook)
1196 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1197 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1198 resume##vendor##device##hook, vendor, device, hook)
1199 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1200 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1201 resume_early##vendor##device##hook, vendor, device, hook)
1202 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1203 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1204 suspend##vendor##device##hook, vendor, device, hook)
1205
1206
1207 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1208
1209 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1210 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1211 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1212 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1213 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1214 const char *name);
1215 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1216
1217 extern int pci_pci_problems;
1218 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1219 #define PCIPCI_TRITON 2
1220 #define PCIPCI_NATOMA 4
1221 #define PCIPCI_VIAETBF 8
1222 #define PCIPCI_VSFX 16
1223 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1224 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1225
1226 extern unsigned long pci_cardbus_io_size;
1227 extern unsigned long pci_cardbus_mem_size;
1228
1229 int pcibios_add_platform_entries(struct pci_dev *dev);
1230 void pcibios_disable_device(struct pci_dev *dev);
1231 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1232 enum pcie_reset_state state);
1233
1234 #ifdef CONFIG_PCI_MMCONFIG
1235 extern void __init pci_mmcfg_early_init(void);
1236 extern void __init pci_mmcfg_late_init(void);
1237 #else
1238 static inline void pci_mmcfg_early_init(void) { }
1239 static inline void pci_mmcfg_late_init(void) { }
1240 #endif
1241
1242 int pci_ext_cfg_avail(struct pci_dev *dev);
1243
1244 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1245
1246 #ifdef CONFIG_PCI_IOV
1247 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1248 extern void pci_disable_sriov(struct pci_dev *dev);
1249 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1250 #else
1251 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1252 {
1253 return -ENODEV;
1254 }
1255 static inline void pci_disable_sriov(struct pci_dev *dev)
1256 {
1257 }
1258 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1259 {
1260 return IRQ_NONE;
1261 }
1262 #endif
1263
1264 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1265 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1266 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1267 #endif
1268
1269 #endif /* __KERNEL__ */
1270 #endif /* LINUX_PCI_H */
Linux kernel - Deliverables
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