4 /* HW register offset definition */
10 #define HSU_GBL_IEN 0x0
11 #define HSU_GBL_IST 0x4
13 #define HSU_GBL_INT_BIT_PORT0 0x0
14 #define HSU_GBL_INT_BIT_PORT1 0x1
15 #define HSU_GBL_INT_BIT_PORT2 0x2
16 #define HSU_GBL_INT_BIT_IRI 0x3
17 #define HSU_GBL_INT_BIT_HDLC 0x4
18 #define HSU_GBL_INT_BIT_DMA 0x5
20 #define HSU_GBL_ISR 0x8
21 #define HSU_GBL_DMASR 0x400
22 #define HSU_GBL_DMAISR 0x404
24 #define HSU_PORT_REG_OFFSET 0x80
25 #define HSU_PORT0_REG_OFFSET 0x80
26 #define HSU_PORT1_REG_OFFSET 0x100
27 #define HSU_PORT2_REG_OFFSET 0x180
28 #define HSU_PORT_REG_LENGTH 0x80
30 #define HSU_DMA_CHANS_REG_OFFSET 0x500
31 #define HSU_DMA_CHANS_REG_LENGTH 0x40
33 #define HSU_CH_SR 0x0 /* channel status reg */
34 #define HSU_CH_CR 0x4 /* control reg */
35 #define HSU_CH_DCR 0x8 /* descriptor control reg */
36 #define HSU_CH_BSR 0x10 /* max fifo buffer size reg */
37 #define HSU_CH_MOTSR 0x14 /* minimum ocp transfer size */
38 #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
39 #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
40 #define HSU_CH_D1SAR 0x28
41 #define HSU_CH_D1TSR 0x2C
42 #define HSU_CH_D2SAR 0x30
43 #define HSU_CH_D2TSR 0x34
44 #define HSU_CH_D3SAR 0x38
45 #define HSU_CH_D3TSR 0x3C
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