include/linux/serial_sci.h

   1 #ifndef __LINUX_SERIAL_SCI_H
   2 #define __LINUX_SERIAL_SCI_H
   3
   4 #include <linux/serial_core.h>
   5 #include <linux/sh_dma.h>
   6
   7 /*
   8  * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
   9  */
  10
  11 #define SCIx_NOT_SUPPORTED      (-1)
  12
  13 enum {
  14         SCBRR_ALGO_1,           /* ((clk + 16 * bps) / (16 * bps) - 1) */
  15         SCBRR_ALGO_2,           /* ((clk + 16 * bps) / (32 * bps) - 1) */
  16         SCBRR_ALGO_3,           /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
  17         SCBRR_ALGO_4,           /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
  18         SCBRR_ALGO_5,           /* (((clk * 1000 / 32) / bps) - 1) */
  19         SCBRR_ALGO_6,           /* HSCIF variable sample rate algorithm */
  20 };
  21
  22 #define SCSCR_TIE       (1 << 7)
  23 #define SCSCR_RIE       (1 << 6)
  24 #define SCSCR_TE        (1 << 5)
  25 #define SCSCR_RE        (1 << 4)
  26 #define SCSCR_REIE      (1 << 3)        /* not supported by all parts */
  27 #define SCSCR_TOIE      (1 << 2)        /* not supported by all parts */
  28 #define SCSCR_CKE1      (1 << 1)
  29 #define SCSCR_CKE0      (1 << 0)
  30
  31 /* SCxSR SCI */
  32 #define SCI_TDRE  0x80
  33 #define SCI_RDRF  0x40
  34 #define SCI_ORER  0x20
  35 #define SCI_FER   0x10
  36 #define SCI_PER   0x08
  37 #define SCI_TEND  0x04
  38
  39 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
  40
  41 /* SCxSR SCIF, HSCIF */
  42 #define SCIF_ER    0x0080
  43 #define SCIF_TEND  0x0040
  44 #define SCIF_TDFE  0x0020
  45 #define SCIF_BRK   0x0010
  46 #define SCIF_FER   0x0008
  47 #define SCIF_PER   0x0004
  48 #define SCIF_RDF   0x0002
  49 #define SCIF_DR    0x0001
  50
  51 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
  52
  53 /* SCSPTR, optional */
  54 #define SCSPTR_RTSIO    (1 << 7)
  55 #define SCSPTR_CTSIO    (1 << 5)
  56 #define SCSPTR_SPB2IO   (1 << 1)
  57 #define SCSPTR_SPB2DT   (1 << 0)
  58
  59 /* HSSRR HSCIF */
  60 #define HSCIF_SRE       0x8000
  61
  62 /* Offsets into the sci_port->irqs array */
  63 enum {
  64         SCIx_ERI_IRQ,
  65         SCIx_RXI_IRQ,
  66         SCIx_TXI_IRQ,
  67         SCIx_BRI_IRQ,
  68         SCIx_NR_IRQS,
  69
  70         SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
  71 };
  72
  73 /* Offsets into the sci_port->gpios array */
  74 enum {
  75         SCIx_SCK,
  76         SCIx_RXD,
  77         SCIx_TXD,
  78         SCIx_CTS,
  79         SCIx_RTS,
  80
  81         SCIx_NR_FNS,
  82 };
  83
  84 enum {
  85         SCIx_PROBE_REGTYPE,
  86
  87         SCIx_SCI_REGTYPE,
  88         SCIx_IRDA_REGTYPE,
  89         SCIx_SCIFA_REGTYPE,
  90         SCIx_SCIFB_REGTYPE,
  91         SCIx_SH2_SCIF_FIFODATA_REGTYPE,
  92         SCIx_SH3_SCIF_REGTYPE,
  93         SCIx_SH4_SCIF_REGTYPE,
  94         SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
  95         SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  96         SCIx_SH7705_SCIF_REGTYPE,
  97         SCIx_HSCIF_REGTYPE,
  98
  99         SCIx_NR_REGTYPES,
 100 };
 101
 102 #define SCIx_IRQ_MUXED(irq)             \
 103 {                                       \
 104         [SCIx_ERI_IRQ]  = (irq),        \
 105         [SCIx_RXI_IRQ]  = (irq),        \
 106         [SCIx_TXI_IRQ]  = (irq),        \
 107         [SCIx_BRI_IRQ]  = (irq),        \
 108 }
 109
 110 #define SCIx_IRQ_IS_MUXED(port)                 \
 111         ((port)->cfg->irqs[SCIx_ERI_IRQ] ==     \
 112          (port)->cfg->irqs[SCIx_RXI_IRQ]) ||    \
 113         ((port)->cfg->irqs[SCIx_ERI_IRQ] &&     \
 114          !(port)->cfg->irqs[SCIx_RXI_IRQ])
 115 /*
 116  * SCI register subset common for all port types.
 117  * Not all registers will exist on all parts.
 118  */
 119 enum {
 120         SCSMR, SCBRR, SCSCR, SCxSR,
 121         SCFCR, SCFDR, SCxTDR, SCxRDR,
 122         SCLSR, SCTFDR, SCRFDR, SCSPTR,
 123         HSSRR,
 124
 125         SCIx_NR_REGS,
 126 };
 127
 128 struct device;
 129
 130 struct plat_sci_port_ops {
 131         void (*init_pins)(struct uart_port *, unsigned int cflag);
 132 };
 133
 134 /*
 135  * Port-specific capabilities
 136  */
 137 #define SCIx_HAVE_RTSCTS        (1 << 0)
 138
 139 /*
 140  * Platform device specific platform_data struct
 141  */
 142 struct plat_sci_port {
 143         unsigned long   mapbase;                /* resource base */
 144         unsigned int    irqs[SCIx_NR_IRQS];     /* ERI, RXI, TXI, BRI */
 145         unsigned int    gpios[SCIx_NR_FNS];     /* SCK, RXD, TXD, CTS, RTS */
 146         unsigned int    type;                   /* SCI / SCIF / IRDA / HSCIF */
 147         upf_t           flags;                  /* UPF_* flags */
 148         unsigned long   capabilities;           /* Port features/capabilities */
 149
 150         unsigned int    scbrr_algo_id;          /* SCBRR calculation algo */
 151         unsigned int    scscr;                  /* SCSCR initialization */
 152
 153         /*
 154          * Platform overrides if necessary, defaults otherwise.
 155          */
 156         int             overrun_bit;
 157         unsigned int    error_mask;
 158
 159         int             port_reg;
 160         unsigned char   regshift;
 161         unsigned char   regtype;
 162
 163         struct plat_sci_port_ops        *ops;
 164
 165         unsigned int    dma_slave_tx;
 166         unsigned int    dma_slave_rx;
 167 };
 168
 169 #endif /* __LINUX_SERIAL_SCI_H */