4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/types.h>
8 #include <linux/kref.h>
10 #include <linux/err.h>
23 #ifdef CONFIG_SH_CLK_CPG_LEGACY
24 void (*init
)(struct clk
*clk
);
26 int (*enable
)(struct clk
*clk
);
27 void (*disable
)(struct clk
*clk
);
28 unsigned long (*recalc
)(struct clk
*clk
);
29 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
30 int (*set_parent
)(struct clk
*clk
, struct clk
*parent
);
31 long (*round_rate
)(struct clk
*clk
, unsigned long rate
);
35 struct list_head node
;
37 struct clk
**parent_table
; /* list of parents to */
38 unsigned short parent_num
; /* choose between */
39 unsigned char src_shift
; /* source clock field in the */
40 unsigned char src_width
; /* configuration register */
41 struct sh_clk_ops
*ops
;
43 struct list_head children
;
44 struct list_head sibling
; /* node for children */
51 void __iomem
*enable_reg
;
52 unsigned int enable_bit
;
53 void __iomem
*mapped_reg
;
55 unsigned long arch_flags
;
57 struct clk_mapping
*mapping
;
58 struct cpufreq_frequency_table
*freq_table
;
59 unsigned int nr_freqs
;
62 #define CLK_ENABLE_ON_INIT (1 << 0)
64 /* drivers/sh/clk.c */
65 unsigned long followparent_recalc(struct clk
*);
66 void recalculate_root_clocks(void);
67 void propagate_rate(struct clk
*);
68 int clk_reparent(struct clk
*child
, struct clk
*parent
);
69 int clk_register(struct clk
*);
70 void clk_unregister(struct clk
*);
71 void clk_enable_init_clocks(void);
73 struct clk_div_mult_table
{
74 unsigned int *divisors
;
75 unsigned int nr_divisors
;
76 unsigned int *multipliers
;
77 unsigned int nr_multipliers
;
80 struct cpufreq_frequency_table
;
81 void clk_rate_table_build(struct clk
*clk
,
82 struct cpufreq_frequency_table
*freq_table
,
84 struct clk_div_mult_table
*src_table
,
85 unsigned long *bitmap
);
87 long clk_rate_table_round(struct clk
*clk
,
88 struct cpufreq_frequency_table
*freq_table
,
91 int clk_rate_table_find(struct clk
*clk
,
92 struct cpufreq_frequency_table
*freq_table
,
95 long clk_rate_div_range_round(struct clk
*clk
, unsigned int div_min
,
96 unsigned int div_max
, unsigned long rate
);
98 long clk_rate_mult_range_round(struct clk
*clk
, unsigned int mult_min
,
99 unsigned int mult_max
, unsigned long rate
);
101 long clk_round_parent(struct clk
*clk
, unsigned long target
,
102 unsigned long *best_freq
, unsigned long *parent_freq
,
103 unsigned int div_min
, unsigned int div_max
);
105 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
108 .enable_reg = (void __iomem *)_enable_reg, \
109 .enable_bit = _enable_bit, \
113 int sh_clk_mstp32_register(struct clk
*clks
, int nr
);
115 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
118 .enable_reg = (void __iomem *)_reg, \
119 .enable_bit = _shift, \
120 .arch_flags = _div_bitmap, \
124 struct clk_div4_table
{
125 struct clk_div_mult_table
*div_mult_table
;
126 void (*kick
)(struct clk
*clk
);
129 int sh_clk_div4_register(struct clk
*clks
, int nr
,
130 struct clk_div4_table
*table
);
131 int sh_clk_div4_enable_register(struct clk
*clks
, int nr
,
132 struct clk_div4_table
*table
);
133 int sh_clk_div4_reparent_register(struct clk
*clks
, int nr
,
134 struct clk_div4_table
*table
);
136 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
137 _num_parents, _src_shift, _src_width) \
139 .enable_reg = (void __iomem *)_reg, \
141 .parent_table = _parents, \
142 .parent_num = _num_parents, \
143 .src_shift = _src_shift, \
144 .src_width = _src_width, \
147 #define SH_CLK_DIV6(_parent, _reg, _flags) \
150 .enable_reg = (void __iomem *)_reg, \
154 int sh_clk_div6_register(struct clk
*clks
, int nr
);
155 int sh_clk_div6_reparent_register(struct clk
*clks
, int nr
);
157 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
158 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
159 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
161 #endif /* __SH_CLOCK_H */
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