4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/types.h>
8 #include <linux/kref.h>
10 #include <linux/err.h>
22 #ifdef CONFIG_SH_CLK_CPG_LEGACY
23 void (*init
)(struct clk
*clk
);
25 int (*enable
)(struct clk
*clk
);
26 void (*disable
)(struct clk
*clk
);
27 unsigned long (*recalc
)(struct clk
*clk
);
28 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
29 int (*set_parent
)(struct clk
*clk
, struct clk
*parent
);
30 long (*round_rate
)(struct clk
*clk
, unsigned long rate
);
34 struct list_head node
;
36 struct clk
**parent_table
; /* list of parents to */
37 unsigned short parent_num
; /* choose between */
38 unsigned char src_shift
; /* source clock field in the */
39 unsigned char src_width
; /* configuration register */
42 struct list_head children
;
43 struct list_head sibling
; /* node for children */
50 void __iomem
*enable_reg
;
51 unsigned int enable_bit
;
52 void __iomem
*mapped_reg
;
54 unsigned long arch_flags
;
56 struct clk_mapping
*mapping
;
57 struct cpufreq_frequency_table
*freq_table
;
58 unsigned int nr_freqs
;
61 #define CLK_ENABLE_ON_INIT (1 << 0)
63 /* drivers/sh/clk.c */
64 unsigned long followparent_recalc(struct clk
*);
65 void recalculate_root_clocks(void);
66 void propagate_rate(struct clk
*);
67 int clk_reparent(struct clk
*child
, struct clk
*parent
);
68 int clk_register(struct clk
*);
69 void clk_unregister(struct clk
*);
70 void clk_enable_init_clocks(void);
72 struct clk_div_mult_table
{
73 unsigned int *divisors
;
74 unsigned int nr_divisors
;
75 unsigned int *multipliers
;
76 unsigned int nr_multipliers
;
79 struct cpufreq_frequency_table
;
80 void clk_rate_table_build(struct clk
*clk
,
81 struct cpufreq_frequency_table
*freq_table
,
83 struct clk_div_mult_table
*src_table
,
84 unsigned long *bitmap
);
86 long clk_rate_table_round(struct clk
*clk
,
87 struct cpufreq_frequency_table
*freq_table
,
90 int clk_rate_table_find(struct clk
*clk
,
91 struct cpufreq_frequency_table
*freq_table
,
94 long clk_rate_div_range_round(struct clk
*clk
, unsigned int div_min
,
95 unsigned int div_max
, unsigned long rate
);
97 long clk_rate_mult_range_round(struct clk
*clk
, unsigned int mult_min
,
98 unsigned int mult_max
, unsigned long rate
);
100 long clk_round_parent(struct clk
*clk
, unsigned long target
,
101 unsigned long *best_freq
, unsigned long *parent_freq
,
102 unsigned int div_min
, unsigned int div_max
);
104 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
107 .enable_reg = (void __iomem *)_enable_reg, \
108 .enable_bit = _enable_bit, \
112 int sh_clk_mstp32_register(struct clk
*clks
, int nr
);
114 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
117 .enable_reg = (void __iomem *)_reg, \
118 .enable_bit = _shift, \
119 .arch_flags = _div_bitmap, \
123 struct clk_div4_table
{
124 struct clk_div_mult_table
*div_mult_table
;
125 void (*kick
)(struct clk
*clk
);
128 int sh_clk_div4_register(struct clk
*clks
, int nr
,
129 struct clk_div4_table
*table
);
130 int sh_clk_div4_enable_register(struct clk
*clks
, int nr
,
131 struct clk_div4_table
*table
);
132 int sh_clk_div4_reparent_register(struct clk
*clks
, int nr
,
133 struct clk_div4_table
*table
);
135 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
136 _num_parents, _src_shift, _src_width) \
138 .enable_reg = (void __iomem *)_reg, \
140 .parent_table = _parents, \
141 .parent_num = _num_parents, \
142 .src_shift = _src_shift, \
143 .src_width = _src_width, \
146 #define SH_CLK_DIV6(_parent, _reg, _flags) \
149 .enable_reg = (void __iomem *)_reg, \
153 int sh_clk_div6_register(struct clk
*clks
, int nr
);
154 int sh_clk_div6_reparent_register(struct clk
*clks
, int nr
);
156 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
157 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
158 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
160 #endif /* __SH_CLOCK_H */
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