4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/types.h>
8 #include <linux/kref.h>
10 #include <linux/err.h>
22 #ifdef CONFIG_SH_CLK_CPG_LEGACY
23 void (*init
)(struct clk
*clk
);
25 int (*enable
)(struct clk
*clk
);
26 void (*disable
)(struct clk
*clk
);
27 unsigned long (*recalc
)(struct clk
*clk
);
28 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
29 int (*set_parent
)(struct clk
*clk
, struct clk
*parent
);
30 long (*round_rate
)(struct clk
*clk
, unsigned long rate
);
33 #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
34 #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
35 #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
38 struct list_head node
;
40 struct clk
**parent_table
; /* list of parents to */
41 unsigned short parent_num
; /* choose between */
42 unsigned char src_shift
; /* source clock field in the */
43 unsigned char src_width
; /* configuration register */
44 struct sh_clk_ops
*ops
;
46 struct list_head children
;
47 struct list_head sibling
; /* node for children */
54 void __iomem
*enable_reg
;
55 unsigned int enable_bit
;
56 void __iomem
*mapped_reg
;
58 unsigned int div_mask
;
59 unsigned long arch_flags
;
61 struct clk_mapping
*mapping
;
62 struct cpufreq_frequency_table
*freq_table
;
63 unsigned int nr_freqs
;
66 #define CLK_ENABLE_ON_INIT BIT(0)
68 #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
69 #define CLK_ENABLE_REG_16BIT BIT(2)
70 #define CLK_ENABLE_REG_8BIT BIT(3)
72 #define CLK_MASK_DIV_ON_DISABLE BIT(4)
74 #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
75 CLK_ENABLE_REG_16BIT | \
78 /* drivers/sh/clk.c */
79 unsigned long followparent_recalc(struct clk
*);
80 void recalculate_root_clocks(void);
81 void propagate_rate(struct clk
*);
82 int clk_reparent(struct clk
*child
, struct clk
*parent
);
83 int clk_register(struct clk
*);
84 void clk_unregister(struct clk
*);
85 void clk_enable_init_clocks(void);
87 struct clk_div_mult_table
{
88 unsigned int *divisors
;
89 unsigned int nr_divisors
;
90 unsigned int *multipliers
;
91 unsigned int nr_multipliers
;
94 struct cpufreq_frequency_table
;
95 void clk_rate_table_build(struct clk
*clk
,
96 struct cpufreq_frequency_table
*freq_table
,
98 struct clk_div_mult_table
*src_table
,
99 unsigned long *bitmap
);
101 long clk_rate_table_round(struct clk
*clk
,
102 struct cpufreq_frequency_table
*freq_table
,
105 int clk_rate_table_find(struct clk
*clk
,
106 struct cpufreq_frequency_table
*freq_table
,
109 long clk_rate_div_range_round(struct clk
*clk
, unsigned int div_min
,
110 unsigned int div_max
, unsigned long rate
);
112 long clk_rate_mult_range_round(struct clk
*clk
, unsigned int mult_min
,
113 unsigned int mult_max
, unsigned long rate
);
115 long clk_round_parent(struct clk
*clk
, unsigned long target
,
116 unsigned long *best_freq
, unsigned long *parent_freq
,
117 unsigned int div_min
, unsigned int div_max
);
119 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
122 .enable_reg = (void __iomem *)_enable_reg, \
123 .enable_bit = _enable_bit, \
127 #define SH_CLK_MSTP32(_p, _r, _b, _f) \
128 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
130 #define SH_CLK_MSTP16(_p, _r, _b, _f) \
131 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
133 #define SH_CLK_MSTP8(_p, _r, _b, _f) \
134 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
136 int sh_clk_mstp_register(struct clk
*clks
, int nr
);
139 * MSTP registration never really cared about access size, despite the
140 * original enable/disable pairs assuming a 32-bit access. Clocks are
141 * responsible for defining their access sizes either directly or via the
142 * clock definition wrappers.
144 static inline int __deprecated
sh_clk_mstp32_register(struct clk
*clks
, int nr
)
146 return sh_clk_mstp_register(clks
, nr
);
149 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
152 .enable_reg = (void __iomem *)_reg, \
153 .enable_bit = _shift, \
154 .arch_flags = _div_bitmap, \
155 .div_mask = SH_CLK_DIV4_MSK, \
159 struct clk_div_table
{
160 struct clk_div_mult_table
*div_mult_table
;
161 void (*kick
)(struct clk
*clk
);
164 #define clk_div4_table clk_div_table
166 int sh_clk_div4_register(struct clk
*clks
, int nr
,
167 struct clk_div4_table
*table
);
168 int sh_clk_div4_enable_register(struct clk
*clks
, int nr
,
169 struct clk_div4_table
*table
);
170 int sh_clk_div4_reparent_register(struct clk
*clks
, int nr
,
171 struct clk_div4_table
*table
);
173 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
174 _num_parents, _src_shift, _src_width) \
176 .enable_reg = (void __iomem *)_reg, \
177 .enable_bit = 0, /* unused */ \
178 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
179 .div_mask = SH_CLK_DIV6_MSK, \
180 .parent_table = _parents, \
181 .parent_num = _num_parents, \
182 .src_shift = _src_shift, \
183 .src_width = _src_width, \
186 #define SH_CLK_DIV6(_parent, _reg, _flags) \
189 .enable_reg = (void __iomem *)_reg, \
190 .enable_bit = 0, /* unused */ \
191 .div_mask = SH_CLK_DIV6_MSK, \
192 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
195 int sh_clk_div6_register(struct clk
*clks
, int nr
);
196 int sh_clk_div6_reparent_register(struct clk
*clks
, int nr
);
198 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
199 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
200 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
202 /* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
203 #define SH_CLK_FSIDIV(_reg, _parent) \
205 .enable_reg = (void __iomem *)_reg, \
209 int sh_clk_fsidiv_register(struct clk
*clks
, int nr
);
211 #endif /* __SH_CLOCK_H */
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