1 2005-04-18 Mark Kettenis <kettenis@gnu.org>
3 * i386.h: Insert hyphens into selected VIA PadLock extensions.
4 Add xcrypt-ctr. Provide aliases without hyphens.
6 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
8 Moved from ../ChangeLog
10 2005-04-12 Paul Brook <paul@codesourcery.com>
11 * m88k.h: Rename psr macros to avoid conflicts.
13 2005-03-12 Zack Weinberg <zack@codesourcery.com>
14 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
15 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
18 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
19 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
20 Remove redundant instruction types.
21 (struct argument): X_op - new field.
22 (struct cst4_entry): Remove.
23 (no_op_insn): Declare.
25 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
26 * crx.h (enum argtype): Rename types, remove unused types.
28 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
29 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
30 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
31 (enum operand_type): Rearrange operands, edit comments.
32 replace us<N> with ui<N> for unsigned immediate.
33 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
34 displacements (respectively).
35 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
36 (instruction type): Add NO_TYPE_INS.
37 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
38 (operand_entry): New field - 'flags'.
41 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
42 * crx.h (operand_type): Remove redundant types i3, i4,
44 Add new unsigned immediate types us3, us4, us5, us16.
46 2005-04-12 Mark Kettenis <kettenis@gnu.org>
48 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
49 adjust them accordingly.
51 2005-04-01 Jan Beulich <jbeulich@novell.com>
53 * i386.h (i386_optab): Add rdtscp.
55 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
57 * i386.h (i386_optab): Don't allow the `l' suffix for moving
58 between memory and segment register. Allow movq for moving between
59 general-purpose register and segment register.
61 2005-02-09 Jan Beulich <jbeulich@novell.com>
64 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
65 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
68 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
70 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
71 * cgen.h (enum cgen_parse_operand_type): Add
72 CGEN_PARSE_OPERAND_SYMBOLIC.
74 2005-01-21 Fred Fish <fnf@specifixinc.com>
76 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
77 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
78 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
80 2005-01-19 Fred Fish <fnf@specifixinc.com>
82 * mips.h (struct mips_opcode): Add new pinfo2 member.
83 (INSN_ALIAS): New define for opcode table entries that are
84 specific instances of another entry, such as 'move' for an 'or'
86 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
87 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
89 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
91 * mips.h (CPU_RM9000): Define.
92 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
94 2004-11-25 Jan Beulich <jbeulich@novell.com>
96 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
97 to/from test registers are illegal in 64-bit mode. Add missing
98 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
99 (previously one had to explicitly encode a rex64 prefix). Re-enable
100 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
101 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
103 2004-11-23 Jan Beulich <jbeulich@novell.com>
105 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
106 available only with SSE2. Change the MMX additions introduced by SSE
107 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
108 instructions by their now designated identifier (since combining i686
109 and 3DNow! does not really imply 3DNow!A).
111 2004-11-19 Alan Modra <amodra@bigpond.net.au>
113 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
114 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
116 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
117 Vineet Sharma <vineets@noida.hcltech.com>
119 * maxq.h: New file: Disassembly information for the maxq port.
121 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
123 * i386.h (i386_optab): Put back "movzb".
125 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
127 * cris.h (enum cris_insn_version_usage): Tweak formatting and
128 comments. Remove member cris_ver_sim. Add members
129 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
130 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
131 (struct cris_support_reg, struct cris_cond15): New types.
132 (cris_conds15): Declare.
133 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
134 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
135 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
136 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
137 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
140 2004-11-04 Jan Beulich <jbeulich@novell.com>
142 * i386.h (sldx_Suf): Remove.
143 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
144 (q_FP): Define, implying no REX64.
145 (x_FP, sl_FP): Imply FloatMF.
146 (i386_optab): Split reg and mem forms of moving from segment registers
147 so that the memory forms can ignore the 16-/32-bit operand size
148 distinction. Adjust a few others for Intel mode. Remove *FP uses from
149 all non-floating-point instructions. Unite 32- and 64-bit forms of
150 movsx, movzx, and movd. Adjust floating point operations for the above
151 changes to the *FP macros. Add DefaultSize to floating point control
152 insns operating on larger memory ranges. Remove left over comments
153 hinting at certain insns being Intel-syntax ones where the ones
154 actually meant are already gone.
156 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
158 * crx.h: Add COPS_REG_INS - Coprocessor Special register
161 2004-09-30 Paul Brook <paul@codesourcery.com>
163 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
164 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
166 2004-09-11 Theodore A. Roth <troth@openavr.org>
168 * avr.h: Add support for
169 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
171 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
173 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
175 2004-08-24 Dmitry Diky <diwil@spec.ru>
177 * msp430.h (msp430_opc): Add new instructions.
178 (msp430_rcodes): Declare new instructions.
179 (msp430_hcodes): Likewise..
181 2004-08-13 Nick Clifton <nickc@redhat.com>
184 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
187 2004-08-30 Michal Ludvig <mludvig@suse.cz>
189 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
191 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
193 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
195 2004-07-21 Jan Beulich <jbeulich@novell.com>
197 * i386.h: Adjust instruction descriptions to better match the
200 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
202 * arm.h: Remove all old content. Replace with architecture defines
203 from gas/config/tc-arm.c.
205 2004-07-09 Andreas Schwab <schwab@suse.de>
207 * m68k.h: Fix comment.
209 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
213 2004-06-24 Alan Modra <amodra@bigpond.net.au>
215 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
217 2004-05-24 Peter Barada <peter@the-baradas.com>
219 * m68k.h: Add 'size' to m68k_opcode.
221 2004-05-05 Peter Barada <peter@the-baradas.com>
223 * m68k.h: Switch from ColdFire chip name to core variant.
225 2004-04-22 Peter Barada <peter@the-baradas.com>
227 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
228 descriptions for new EMAC cases.
229 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
230 handle Motorola MAC syntax.
231 Allow disassembly of ColdFire V4e object files.
233 2004-03-16 Alan Modra <amodra@bigpond.net.au>
235 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
237 2004-03-12 Jakub Jelinek <jakub@redhat.com>
239 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
241 2004-03-12 Michal Ludvig <mludvig@suse.cz>
243 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
245 2004-03-12 Michal Ludvig <mludvig@suse.cz>
247 * i386.h (i386_optab): Added xstore/xcrypt insns.
249 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
251 * h8300.h (32bit ldc/stc): Add relaxing support.
253 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
255 * h8300.h (BITOP): Pass MEMRELAX flag.
257 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
259 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
262 For older changes see ChangeLog-9103
268 version-control: never