include/opcode/ChangeLog

   1 2005-04-01  Jan Beulich  <jbeulich@novell.com>
   2
   3         * i386.h (i386_optab): Add rdtscp.
   4
   5 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386.h (i386_optab): Don't allow the `l' suffix for moving
   8         moving between memory and segment register. Allow movq for
   9         moving between general-purpose register and segment register.
  10
  11 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  12
  13         PR gas/707
  14         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  15         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  16         fnstsw.
  17
  18 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  19
  20         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  21         * cgen.h (enum cgen_parse_operand_type): Add
  22         CGEN_PARSE_OPERAND_SYMBOLIC.
  23
  24 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  25
  26         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  27         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  28         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  29
  30 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  31
  32         * mips.h (struct mips_opcode): Add new pinfo2 member.
  33         (INSN_ALIAS): New define for opcode table entries that are
  34         specific instances of another entry, such as 'move' for an 'or'
  35         with a zero operand.
  36         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  37         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  38
  39 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  40
  41         * mips.h (CPU_RM9000): Define.
  42         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  43
  44 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  45
  46         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  47         to/from test registers are illegal in 64-bit mode. Add missing
  48         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  49         (previously one had to explicitly encode a rex64 prefix). Re-enable
  50         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  51         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  52
  53 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  54
  55         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
  56         available only with SSE2. Change the MMX additions introduced by SSE
  57         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
  58         instructions by their now designated identifier (since combining i686
  59         and 3DNow! does not really imply 3DNow!A).
  60
  61 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  62
  63         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
  64         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
  65
  66 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  67             Vineet Sharma      <vineets@noida.hcltech.com>
  68
  69         * maxq.h: New file: Disassembly information for the maxq port.
  70
  71 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         * i386.h (i386_optab): Put back "movzb".
  74
  75 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  76
  77         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  78         comments.  Remove member cris_ver_sim.  Add members
  79         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  80         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  81         (struct cris_support_reg, struct cris_cond15): New types.
  82         (cris_conds15): Declare.
  83         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  84         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  85         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  86         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  87         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  88         SIZE_FIELD_UNSIGNED.
  89
  90 2004-11-04 Jan Beulich  <jbeulich@novell.com>
  91
  92         * i386.h (sldx_Suf): Remove.
  93         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  94         (q_FP): Define, implying no REX64.
  95         (x_FP, sl_FP): Imply FloatMF.
  96         (i386_optab): Split reg and mem forms of moving from segment registers
  97         so that the memory forms can ignore the 16-/32-bit operand size
  98         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  99         all non-floating-point instructions. Unite 32- and 64-bit forms of
 100         movsx, movzx, and movd. Adjust floating point operations for the above
 101         changes to the *FP macros. Add DefaultSize to floating point control
 102         insns operating on larger memory ranges. Remove left over comments
 103         hinting at certain insns being Intel-syntax ones where the ones
 104         actually meant are already gone.
 105
 106 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 107
 108         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 109         instruction type.
 110
 111 2004-09-30  Paul Brook  <paul@codesourcery.com>
 112
 113         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 114         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 115
 116 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 117
 118         * avr.h: Add support for
 119         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 120
 121 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 122
 123         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 124
 125 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 126
 127         * msp430.h (msp430_opc): Add new instructions.
 128         (msp430_rcodes): Declare new instructions.
 129         (msp430_hcodes): Likewise..
 130
 131 2004-08-13  Nick Clifton  <nickc@redhat.com>
 132
 133         PR/301
 134         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 135         processors.
 136
 137 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 138
 139         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 140
 141 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 144
 145 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 146
 147         * i386.h: Adjust instruction descriptions to better match the
 148         specification.
 149
 150 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 151
 152         * arm.h: Remove all old content.  Replace with architecture defines
 153         from gas/config/tc-arm.c.
 154
 155 2004-07-09  Andreas Schwab  <schwab@suse.de>
 156
 157         * m68k.h: Fix comment.
 158
 159 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 160
 161         * crx.h: New file.
 162
 163 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 164
 165         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 166
 167 2004-05-24  Peter Barada  <peter@the-baradas.com>
 168
 169         * m68k.h: Add 'size' to m68k_opcode.
 170
 171 2004-05-05  Peter Barada  <peter@the-baradas.com>
 172
 173         * m68k.h: Switch from ColdFire chip name to core variant.
 174
 175 2004-04-22  Peter Barada  <peter@the-baradas.com>
 176
 177         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 178         descriptions for new EMAC cases.
 179         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 180         handle Motorola MAC syntax.
 181         Allow disassembly of ColdFire V4e object files.
 182
 183 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 184
 185         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 186
 187 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 188
 189         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 190
 191 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 192
 193         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 194
 195 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 196
 197         * i386.h (i386_optab): Added xstore/xcrypt insns.
 198
 199 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 200
 201         * h8300.h (32bit ldc/stc): Add relaxing support.
 202
 203 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 204
 205         * h8300.h (BITOP): Pass MEMRELAX flag.
 206
 207 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 208
 209         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 210         except for the H8S.
 211
 212 For older changes see ChangeLog-9103
 213 \f
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