1 2011-07-24 Chao-ying Fu <fu@mips.com>
2 Maciej W. Rozycki <macro@codesourcery.com>
4 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
5 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
6 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
7 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
8 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
9 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
10 (OP_MASK_RS3, OP_SH_RS3): Likewise.
11 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
12 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
13 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
14 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
15 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
16 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
17 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
18 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
19 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
20 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
21 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
22 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
23 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
24 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
25 (INSN_WRITE_GPR_S): New macro.
26 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
27 (INSN2_READ_FPR_D): Likewise.
28 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
29 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
30 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
31 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
32 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
33 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
34 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
35 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
36 (CPU_MICROMIPS): New macro.
37 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
38 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
39 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
40 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
41 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
42 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
43 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
44 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
45 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
46 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
47 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
48 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
49 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
50 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
51 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
52 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
53 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
54 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
55 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
56 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
57 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
58 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
59 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
60 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
61 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
62 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
63 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
64 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
65 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
66 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
67 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
68 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
69 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
70 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
71 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
72 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
73 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
74 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
75 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
76 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
77 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
78 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
79 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
80 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
81 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
82 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
83 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
84 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
85 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
86 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
87 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
88 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
89 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
90 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
91 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
92 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
93 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
94 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
95 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
96 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
97 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
98 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
99 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
100 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
101 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
102 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
103 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
104 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
105 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
106 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
107 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
108 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
109 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
110 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
111 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
112 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
113 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
114 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
115 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
116 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
117 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
118 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
119 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
120 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
121 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
122 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
123 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
124 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
125 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
126 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
127 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
128 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
129 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
130 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
131 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
132 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
133 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
134 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
135 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
136 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
137 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
138 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
139 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
140 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
141 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
142 (micromips_opcodes): New declaration.
143 (bfd_micromips_num_opcodes): Likewise.
145 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
147 * mips.h (INSN_TRAP): Rename to...
148 (INSN_NO_DELAY_SLOT): ... this.
149 (INSN_SYNC): Remove macro.
151 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
153 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
154 a duplicate of AVR_ISA_SPM.
156 2011-07-01 Nick Clifton <nickc@redhat.com>
158 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
160 2011-06-18 Robin Getz <robin.getz@analog.com>
162 * bfin.h (is_macmod_signed): New func
164 2011-06-18 Mike Frysinger <vapier@gentoo.org>
166 * bfin.h (is_macmod_pmove): Add missing space before func args.
167 (is_macmod_hmove): Likewise.
169 2011-06-13 Walter Lee <walt@tilera.com>
171 * tilegx.h: New file.
172 * tilepro.h: New file.
174 2011-05-31 Paul Brook <paul@codesourcery.com>
176 * arm.h (ARM_ARCH_V7R_IDIV): Define.
178 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
180 * s390.h: Replace S390_OPERAND_REG_EVEN with
181 S390_OPERAND_REG_PAIR.
183 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
185 * s390.h: Add S390_OPCODE_REG_EVEN flag.
187 2011-04-18 Julian Brown <julian@codesourcery.com>
189 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
191 2011-04-11 Dan McDonald <dan@wellkeeper.com>
194 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
196 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
198 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
199 New instruction set flags.
200 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
202 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
204 * mips.h (M_PREF_AB): New enum value.
206 2011-02-12 Mike Frysinger <vapier@gentoo.org>
208 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
210 (is_macmod_pmove, is_macmod_hmove): New functions.
212 2011-02-11 Mike Frysinger <vapier@gentoo.org>
214 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
216 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
218 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
219 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
221 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
224 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
227 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
230 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
232 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
234 * mips.h: Update commentary after last commit.
236 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
238 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
239 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
240 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
242 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
244 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
246 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
248 * mips.h: Fix previous commit.
250 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
252 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
253 (INSN_LOONGSON_3A): Clear bit 31.
255 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
258 * arm.h (ARM_AEXT_V6M_ONLY): New define.
259 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
260 (ARM_ARCH_V6M_ONLY): New define.
262 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
264 * mips.h (INSN_LOONGSON_3A): Defined.
265 (CPU_LOONGSON_3A): Defined.
266 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
268 2010-10-09 Matt Rice <ratmice@gmail.com>
270 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
271 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
273 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
275 * arm.h (ARM_EXT_VIRT): New define.
276 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
277 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
280 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
282 * arm.h (ARM_AEXT_ADIV): New define.
283 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
285 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
287 * arm.h (ARM_EXT_OS): New define.
288 (ARM_AEXT_V6SM): Likewise.
289 (ARM_ARCH_V6SM): Likewise.
291 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
293 * arm.h (ARM_EXT_MP): Add.
294 (ARM_ARCH_V7A_MP): Likewise.
296 2010-09-22 Mike Frysinger <vapier@gentoo.org>
298 * bfin.h: Declare pseudoChr structs/defines.
300 2010-09-21 Mike Frysinger <vapier@gentoo.org>
302 * bfin.h: Strip trailing whitespace.
304 2010-07-29 DJ Delorie <dj@redhat.com>
306 * rx.h (RX_Operand_Type): Add TwoReg.
307 (RX_Opcode_ID): Remove ediv and ediv2.
309 2010-07-27 DJ Delorie <dj@redhat.com>
311 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
313 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
314 Ina Pandit <ina.pandit@kpitcummins.com>
316 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
317 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
318 PROCESSOR_V850E2_ALL.
319 Remove PROCESSOR_V850EA support.
320 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
321 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
322 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
323 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
324 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
325 V850_OPERAND_PERCENT.
326 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
328 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
331 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
333 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
334 (MIPS16_INSN_BRANCH): Rename to...
335 (MIPS16_INSN_COND_BRANCH): ... this.
337 2010-07-03 Alan Modra <amodra@gmail.com>
339 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
340 Renumber other PPC_OPCODE defines.
342 2010-07-03 Alan Modra <amodra@gmail.com>
344 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
346 2010-06-29 Alan Modra <amodra@gmail.com>
348 * maxq.h: Delete file.
350 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
352 * ppc.h (PPC_OPCODE_E500): Define.
354 2010-05-26 Catherine Moore <clm@codesourcery.com>
356 * opcode/mips.h (INSN_MIPS16): Remove.
358 2010-04-21 Joseph Myers <joseph@codesourcery.com>
360 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
362 2010-04-15 Nick Clifton <nickc@redhat.com>
364 * alpha.h: Update copyright notice to use GPLv3.
370 * convex.h: Likewise.
384 * m68hc11.h: Likewise.
390 * mn10200.h: Likewise.
391 * mn10300.h: Likewise.
392 * msp430.h: Likewise.
403 * score-datadep.h: Likewise.
404 * score-inst.h: Likewise.
406 * spu-insns.h: Likewise.
410 * tic54x.h: Likewise.
415 2010-03-25 Joseph Myers <joseph@codesourcery.com>
417 * tic6x-control-registers.h, tic6x-insn-formats.h,
418 tic6x-opcode-table.h, tic6x.h: New.
420 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
422 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
424 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
426 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
428 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
430 * ia64.h (ia64_find_opcode): Remove argument name.
431 (ia64_find_next_opcode): Likewise.
432 (ia64_dis_opcode): Likewise.
433 (ia64_free_opcode): Likewise.
434 (ia64_find_dependency): Likewise.
436 2009-11-22 Doug Evans <dje@sebabeach.org>
438 * cgen.h: Include bfd_stdint.h.
439 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
441 2009-11-18 Paul Brook <paul@codesourcery.com>
443 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
445 2009-11-17 Paul Brook <paul@codesourcery.com>
446 Daniel Jacobowitz <dan@codesourcery.com>
448 * arm.h (ARM_EXT_V6_DSP): Define.
449 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
450 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
452 2009-11-04 DJ Delorie <dj@redhat.com>
454 * rx.h (rx_decode_opcode) (mvtipl): Add.
455 (mvtcp, mvfcp, opecp): Remove.
457 2009-11-02 Paul Brook <paul@codesourcery.com>
459 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
460 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
461 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
462 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
463 FPU_ARCH_NEON_VFP_V4): Define.
465 2009-10-23 Doug Evans <dje@sebabeach.org>
467 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
468 * cgen.h: Update. Improve multi-inclusion macro name.
470 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
472 * ppc.h (PPC_OPCODE_476): Define.
474 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
476 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
478 2009-09-29 DJ Delorie <dj@redhat.com>
482 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
484 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
486 2009-09-21 Ben Elliston <bje@au.ibm.com>
488 * ppc.h (PPC_OPCODE_PPCA2): New.
490 2009-09-05 Martin Thuresson <martin@mtme.org>
492 * ia64.h (struct ia64_operand): Renamed member class to op_class.
494 2009-08-29 Martin Thuresson <martin@mtme.org>
496 * tic30.h (template): Rename type template to
497 insn_template. Updated code to use new name.
498 * tic54x.h (template): Rename type template to
501 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
503 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
505 2009-06-11 Anthony Green <green@moxielogic.com>
507 * moxie.h (MOXIE_F3_PCREL): Define.
508 (moxie_form3_opc_info): Grow.
510 2009-06-06 Anthony Green <green@moxielogic.com>
512 * moxie.h (MOXIE_F1_M): Define.
514 2009-04-15 Anthony Green <green@moxielogic.com>
518 2009-04-06 DJ Delorie <dj@redhat.com>
520 * h8300.h: Add relaxation attributes to MOVA opcodes.
522 2009-03-10 Alan Modra <amodra@bigpond.net.au>
524 * ppc.h (ppc_parse_cpu): Declare.
526 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
528 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
529 and _IMM11 for mbitclr and mbitset.
530 * score-datadep.h: Update dependency information.
532 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
534 * ppc.h (PPC_OPCODE_POWER7): New.
536 2009-02-06 Doug Evans <dje@google.com>
538 * i386.h: Add comment regarding sse* insns and prefixes.
540 2009-02-03 Sandip Matte <sandip@rmicorp.com>
542 * mips.h (INSN_XLR): Define.
543 (INSN_CHIP_MASK): Update.
545 (OPCODE_IS_MEMBER): Update.
546 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
548 2009-01-28 Doug Evans <dje@google.com>
550 * opcode/i386.h: Add multiple inclusion protection.
551 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
552 (EDI_REG_NUM): New macros.
553 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
554 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
555 (REX_PREFIX_P): New macro.
557 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
559 * ppc.h (struct powerpc_opcode): New field "deprecated".
560 (PPC_OPCODE_NOPOWER4): Delete.
562 2008-11-28 Joshua Kinard <kumba@gentoo.org>
564 * mips.h: Define CPU_R14000, CPU_R16000.
565 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
567 2008-11-18 Catherine Moore <clm@codesourcery.com>
569 * arm.h (FPU_NEON_FP16): New.
570 (FPU_ARCH_NEON_FP16): New.
572 2008-11-06 Chao-ying Fu <fu@mips.com>
574 * mips.h: Doucument '1' for 5-bit sync type.
576 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
578 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
581 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
583 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
585 2008-07-30 Michael J. Eager <eager@eagercon.com>
587 * ppc.h (PPC_OPCODE_405): Define.
588 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
590 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
592 * ppc.h (ppc_cpu_t): New typedef.
593 (struct powerpc_opcode <flags>): Use it.
594 (struct powerpc_operand <insert, extract>): Likewise.
595 (struct powerpc_macro <flags>): Likewise.
597 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
599 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
600 Update comment before MIPS16 field descriptors to mention MIPS16.
601 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
603 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
604 New bit masks and shift counts for cins and exts.
606 * mips.h: Document new field descriptors +Q.
607 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
609 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
611 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
612 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
614 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
616 * ppc.h: (PPC_OPCODE_E500MC): New.
618 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
620 * i386.h (MAX_OPERANDS): Set to 5.
621 (MAX_MNEM_SIZE): Changed to 20.
623 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
625 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
627 2008-03-09 Paul Brook <paul@codesourcery.com>
629 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
631 2008-03-04 Paul Brook <paul@codesourcery.com>
633 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
634 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
635 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
637 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
638 Nick Clifton <nickc@redhat.com>
641 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
642 with a 32-bit displacement but without the top bit of the 4th byte
645 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
647 * cr16.h (cr16_num_optab): Declared.
649 2008-02-14 Hakan Ardo <hakan@debian.org>
652 * avr.h (AVR_ISA_2xxe): Define.
654 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
656 * mips.h: Update copyright.
657 (INSN_CHIP_MASK): New macro.
658 (INSN_OCTEON): New macro.
659 (CPU_OCTEON): New macro.
660 (OPCODE_IS_MEMBER): Handle Octeon instructions.
662 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
664 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
666 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
668 * avr.h (AVR_ISA_USB162): Add new opcode set.
669 (AVR_ISA_AVR3): Likewise.
671 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
673 * mips.h (INSN_LOONGSON_2E): New.
674 (INSN_LOONGSON_2F): New.
675 (CPU_LOONGSON_2E): New.
676 (CPU_LOONGSON_2F): New.
677 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
679 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
681 * mips.h (INSN_ISA*): Redefine certain values as an
682 enumeration. Update comments.
683 (mips_isa_table): New.
684 (ISA_MIPS*): Redefine to match enumeration.
685 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
688 2007-08-08 Ben Elliston <bje@au.ibm.com>
690 * ppc.h (PPC_OPCODE_PPCPS): New.
692 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
694 * m68k.h: Document j K & E.
696 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
698 * cr16.h: New file for CR16 target.
700 2007-05-02 Alan Modra <amodra@bigpond.net.au>
702 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
704 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
706 * m68k.h (mcfisa_c): New.
707 (mcfusp, mcf_mask): Adjust.
709 2007-04-20 Alan Modra <amodra@bigpond.net.au>
711 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
712 (num_powerpc_operands): Declare.
713 (PPC_OPERAND_SIGNED et al): Redefine as hex.
714 (PPC_OPERAND_PLUS1): Define.
716 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
718 * i386.h (REX_MODE64): Renamed to ...
720 (REX_EXTX): Renamed to ...
722 (REX_EXTY): Renamed to ...
724 (REX_EXTZ): Renamed to ...
727 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
729 * i386.h: Add entries from config/tc-i386.h and move tables
730 to opcodes/i386-opc.h.
732 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
734 * i386.h (FloatDR): Removed.
735 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
737 2007-03-01 Alan Modra <amodra@bigpond.net.au>
739 * spu-insns.h: Add soma double-float insns.
741 2007-02-20 Thiemo Seufer <ths@mips.com>
742 Chao-Ying Fu <fu@mips.com>
744 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
745 (INSN_DSPR2): Add flag for DSP R2 instructions.
746 (M_BALIGN): New macro.
748 2007-02-14 Alan Modra <amodra@bigpond.net.au>
750 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
751 and Seg3ShortFrom with Shortform.
753 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
756 * i386.h (i386_optab): Put the real "test" before the pseudo
759 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
761 * m68k.h (m68010up): OR fido_a.
763 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
765 * m68k.h (fido_a): New.
767 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
769 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
770 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
773 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
775 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
777 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
779 * score-inst.h (enum score_insn_type): Add Insn_internal.
781 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
782 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
783 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
784 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
785 Alan Modra <amodra@bigpond.net.au>
787 * spu-insns.h: New file.
790 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
792 * ppc.h (PPC_OPCODE_CELL): Define.
794 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
796 * i386.h : Modify opcode to support for the change in POPCNT opcode
797 in amdfam10 architecture.
799 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
801 * i386.h: Replace CpuMNI with CpuSSSE3.
803 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
804 Joseph Myers <joseph@codesourcery.com>
805 Ian Lance Taylor <ian@wasabisystems.com>
806 Ben Elliston <bje@wasabisystems.com>
808 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
810 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
812 * score-datadep.h: New file.
813 * score-inst.h: New file.
815 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
817 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
818 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
821 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
822 Michael Meissner <michael.meissner@amd.com>
824 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
826 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
828 * i386.h (i386_optab): Add "nop" with memory reference.
830 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
832 * i386.h (i386_optab): Update comment for 64bit NOP.
834 2006-06-06 Ben Elliston <bje@au.ibm.com>
835 Anton Blanchard <anton@samba.org>
837 * ppc.h (PPC_OPCODE_POWER6): Define.
840 2006-06-05 Thiemo Seufer <ths@mips.com>
842 * mips.h: Improve description of MT flags.
844 2006-05-25 Richard Sandiford <richard@codesourcery.com>
846 * m68k.h (mcf_mask): Define.
848 2006-05-05 Thiemo Seufer <ths@mips.com>
849 David Ung <davidu@mips.com>
851 * mips.h (enum): Add macro M_CACHE_AB.
853 2006-05-04 Thiemo Seufer <ths@mips.com>
854 Nigel Stephens <nigel@mips.com>
855 David Ung <davidu@mips.com>
857 * mips.h: Add INSN_SMARTMIPS define.
859 2006-04-30 Thiemo Seufer <ths@mips.com>
860 David Ung <davidu@mips.com>
862 * mips.h: Defines udi bits and masks. Add description of
863 characters which may appear in the args field of udi
866 2006-04-26 Thiemo Seufer <ths@networkno.de>
868 * mips.h: Improve comments describing the bitfield instruction
871 2006-04-26 Julian Brown <julian@codesourcery.com>
873 * arm.h (FPU_VFP_EXT_V3): Define constant.
874 (FPU_NEON_EXT_V1): Likewise.
875 (FPU_VFP_HARD): Update.
876 (FPU_VFP_V3): Define macro.
877 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
879 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
881 * avr.h (AVR_ISA_PWMx): New.
883 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
885 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
886 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
887 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
888 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
889 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
891 2006-03-10 Paul Brook <paul@codesourcery.com>
893 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
895 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
897 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
898 first. Correct mask of bb "B" opcode.
900 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
902 * i386.h (i386_optab): Support Intel Merom New Instructions.
904 2006-02-24 Paul Brook <paul@codesourcery.com>
906 * arm.h: Add V7 feature bits.
908 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
910 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
912 2006-01-31 Paul Brook <paul@codesourcery.com>
913 Richard Earnshaw <rearnsha@arm.com>
915 * arm.h: Use ARM_CPU_FEATURE.
916 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
917 (arm_feature_set): Change to a structure.
918 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
919 ARM_FEATURE): New macros.
921 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
923 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
924 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
925 (ADD_PC_INCR_OPCODE): Don't define.
927 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
930 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
932 2005-11-14 David Ung <davidu@mips.com>
934 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
935 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
936 save/restore encoding of the args field.
938 2005-10-28 Dave Brolley <brolley@redhat.com>
940 Contribute the following changes:
941 2005-02-16 Dave Brolley <brolley@redhat.com>
943 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
944 cgen_isa_mask_* to cgen_bitset_*.
947 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
949 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
950 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
951 (CGEN_CPU_TABLE): Make isas a ponter.
953 2003-09-29 Dave Brolley <brolley@redhat.com>
955 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
956 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
957 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
959 2002-12-13 Dave Brolley <brolley@redhat.com>
961 * cgen.h (symcat.h): #include it.
962 (cgen-bitset.h): #include it.
963 (CGEN_ATTR_VALUE_TYPE): Now a union.
964 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
965 (CGEN_ATTR_ENTRY): 'value' now unsigned.
966 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
967 * cgen-bitset.h: New file.
969 2005-09-30 Catherine Moore <clm@cm00re.com>
973 2005-10-24 Jan Beulich <jbeulich@novell.com>
975 * ia64.h (enum ia64_opnd): Move memory operand out of set of
978 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
980 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
981 Add FLAG_STRICT to pa10 ftest opcode.
983 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
985 * hppa.h (pa_opcodes): Remove lha entries.
987 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
989 * hppa.h (FLAG_STRICT): Revise comment.
990 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
991 before corresponding pa11 opcodes. Add strict pa10 register-immediate
994 2005-09-30 Catherine Moore <clm@cm00re.com>
998 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1000 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1002 2005-09-06 Chao-ying Fu <fu@mips.com>
1004 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1005 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1007 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1008 (INSN_ASE_MASK): Update to include INSN_MT.
1009 (INSN_MT): New define for MT ASE.
1011 2005-08-25 Chao-ying Fu <fu@mips.com>
1013 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1014 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1015 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1016 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1017 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1018 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1020 (INSN_DSP): New define for DSP ASE.
1022 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1026 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1028 * ppc.h (PPC_OPCODE_E300): Define.
1030 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1032 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1034 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1037 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1040 2005-07-27 Jan Beulich <jbeulich@novell.com>
1042 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1043 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1044 Add movq-s as 64-bit variants of movd-s.
1046 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1048 * hppa.h: Fix punctuation in comment.
1050 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1051 implicit space-register addressing. Set space-register bits on opcodes
1052 using implicit space-register addressing. Add various missing pa20
1053 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1054 space-register addressing. Use "fE" instead of "fe" in various
1057 2005-07-18 Jan Beulich <jbeulich@novell.com>
1059 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1061 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1063 * i386.h (i386_optab): Support Intel VMX Instructions.
1065 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1067 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1069 2005-07-05 Jan Beulich <jbeulich@novell.com>
1071 * i386.h (i386_optab): Add new insns.
1073 2005-07-01 Nick Clifton <nickc@redhat.com>
1075 * sparc.h: Add typedefs to structure declarations.
1077 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1080 * i386.h (i386_optab): Update comments for 64bit addressing on
1081 mov. Allow 64bit addressing for mov and movq.
1083 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1085 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1086 respectively, in various floating-point load and store patterns.
1088 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1090 * hppa.h (FLAG_STRICT): Correct comment.
1091 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1092 PA 2.0 mneumonics when equivalent. Entries with cache control
1093 completers now require PA 1.1. Adjust whitespace.
1095 2005-05-19 Anton Blanchard <anton@samba.org>
1097 * ppc.h (PPC_OPCODE_POWER5): Define.
1099 2005-05-10 Nick Clifton <nickc@redhat.com>
1101 * Update the address and phone number of the FSF organization in
1102 the GPL notices in the following files:
1103 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1104 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1105 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1106 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1107 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1108 tic54x.h, tic80.h, v850.h, vax.h
1110 2005-05-09 Jan Beulich <jbeulich@novell.com>
1112 * i386.h (i386_optab): Add ht and hnt.
1114 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1116 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1117 Add xcrypt-ctr. Provide aliases without hyphens.
1119 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1121 Moved from ../ChangeLog
1123 2005-04-12 Paul Brook <paul@codesourcery.com>
1124 * m88k.h: Rename psr macros to avoid conflicts.
1126 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1127 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1128 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1129 and ARM_ARCH_V6ZKT2.
1131 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1132 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1133 Remove redundant instruction types.
1134 (struct argument): X_op - new field.
1135 (struct cst4_entry): Remove.
1136 (no_op_insn): Declare.
1138 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1139 * crx.h (enum argtype): Rename types, remove unused types.
1141 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1142 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1143 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1144 (enum operand_type): Rearrange operands, edit comments.
1145 replace us<N> with ui<N> for unsigned immediate.
1146 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1147 displacements (respectively).
1148 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1149 (instruction type): Add NO_TYPE_INS.
1150 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1151 (operand_entry): New field - 'flags'.
1152 (operand flags): New.
1154 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1155 * crx.h (operand_type): Remove redundant types i3, i4,
1157 Add new unsigned immediate types us3, us4, us5, us16.
1159 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1161 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1162 adjust them accordingly.
1164 2005-04-01 Jan Beulich <jbeulich@novell.com>
1166 * i386.h (i386_optab): Add rdtscp.
1168 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1170 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1171 between memory and segment register. Allow movq for moving between
1172 general-purpose register and segment register.
1174 2005-02-09 Jan Beulich <jbeulich@novell.com>
1177 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1178 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1181 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1183 * m68k.h (m68008, m68ec030, m68882): Remove.
1185 (cpu_m68k, cpu_cf): New.
1186 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1187 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1189 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1191 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1192 * cgen.h (enum cgen_parse_operand_type): Add
1193 CGEN_PARSE_OPERAND_SYMBOLIC.
1195 2005-01-21 Fred Fish <fnf@specifixinc.com>
1197 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1198 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1199 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1201 2005-01-19 Fred Fish <fnf@specifixinc.com>
1203 * mips.h (struct mips_opcode): Add new pinfo2 member.
1204 (INSN_ALIAS): New define for opcode table entries that are
1205 specific instances of another entry, such as 'move' for an 'or'
1206 with a zero operand.
1207 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1208 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1210 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1212 * mips.h (CPU_RM9000): Define.
1213 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1215 2004-11-25 Jan Beulich <jbeulich@novell.com>
1217 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1218 to/from test registers are illegal in 64-bit mode. Add missing
1219 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1220 (previously one had to explicitly encode a rex64 prefix). Re-enable
1221 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1222 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1224 2004-11-23 Jan Beulich <jbeulich@novell.com>
1226 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1227 available only with SSE2. Change the MMX additions introduced by SSE
1228 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1229 instructions by their now designated identifier (since combining i686
1230 and 3DNow! does not really imply 3DNow!A).
1232 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1234 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1235 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1237 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1238 Vineet Sharma <vineets@noida.hcltech.com>
1240 * maxq.h: New file: Disassembly information for the maxq port.
1242 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1244 * i386.h (i386_optab): Put back "movzb".
1246 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1248 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1249 comments. Remove member cris_ver_sim. Add members
1250 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1251 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1252 (struct cris_support_reg, struct cris_cond15): New types.
1253 (cris_conds15): Declare.
1254 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1255 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1256 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1257 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1258 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1259 SIZE_FIELD_UNSIGNED.
1261 2004-11-04 Jan Beulich <jbeulich@novell.com>
1263 * i386.h (sldx_Suf): Remove.
1264 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1265 (q_FP): Define, implying no REX64.
1266 (x_FP, sl_FP): Imply FloatMF.
1267 (i386_optab): Split reg and mem forms of moving from segment registers
1268 so that the memory forms can ignore the 16-/32-bit operand size
1269 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1270 all non-floating-point instructions. Unite 32- and 64-bit forms of
1271 movsx, movzx, and movd. Adjust floating point operations for the above
1272 changes to the *FP macros. Add DefaultSize to floating point control
1273 insns operating on larger memory ranges. Remove left over comments
1274 hinting at certain insns being Intel-syntax ones where the ones
1275 actually meant are already gone.
1277 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1279 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1282 2004-09-30 Paul Brook <paul@codesourcery.com>
1284 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1285 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1287 2004-09-11 Theodore A. Roth <troth@openavr.org>
1289 * avr.h: Add support for
1290 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1292 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1294 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1296 2004-08-24 Dmitry Diky <diwil@spec.ru>
1298 * msp430.h (msp430_opc): Add new instructions.
1299 (msp430_rcodes): Declare new instructions.
1300 (msp430_hcodes): Likewise..
1302 2004-08-13 Nick Clifton <nickc@redhat.com>
1305 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1308 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1310 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1312 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1314 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1316 2004-07-21 Jan Beulich <jbeulich@novell.com>
1318 * i386.h: Adjust instruction descriptions to better match the
1321 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1323 * arm.h: Remove all old content. Replace with architecture defines
1324 from gas/config/tc-arm.c.
1326 2004-07-09 Andreas Schwab <schwab@suse.de>
1328 * m68k.h: Fix comment.
1330 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1334 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1336 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1338 2004-05-24 Peter Barada <peter@the-baradas.com>
1340 * m68k.h: Add 'size' to m68k_opcode.
1342 2004-05-05 Peter Barada <peter@the-baradas.com>
1344 * m68k.h: Switch from ColdFire chip name to core variant.
1346 2004-04-22 Peter Barada <peter@the-baradas.com>
1348 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1349 descriptions for new EMAC cases.
1350 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1351 handle Motorola MAC syntax.
1352 Allow disassembly of ColdFire V4e object files.
1354 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1356 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1358 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1360 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1362 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1364 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1366 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1368 * i386.h (i386_optab): Added xstore/xcrypt insns.
1370 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1372 * h8300.h (32bit ldc/stc): Add relaxing support.
1374 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1376 * h8300.h (BITOP): Pass MEMRELAX flag.
1378 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1380 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1383 For older changes see ChangeLog-9103
1389 version-control: never