include/opcode/ChangeLog

   1 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
   2
   3         * m68k.h (fido_a): New.
   4
   5 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
   6
   7         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
   8         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
   9         values.
  10
  11 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  14
  15 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  16
  17         * score-inst.h (enum score_insn_type): Add Insn_internal.
  18
  19 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  20             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  21             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  22             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  23             Alan Modra  <amodra@bigpond.net.au>
  24
  25         * spu-insns.h: New file.
  26         * spu.h: New file.
  27
  28 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  29
  30         * ppc.h (PPC_OPCODE_CELL): Define.
  31
  32 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  33
  34         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  35         in amdfam10 architecture.
  36
  37 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386.h: Replace CpuMNI with CpuSSSE3.
  40
  41 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  42             Joseph Myers  <joseph@codesourcery.com>
  43             Ian Lance Taylor  <ian@wasabisystems.com>
  44             Ben Elliston  <bje@wasabisystems.com>
  45
  46         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  47
  48 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  49
  50         * score-datadep.h: New file.
  51         * score-inst.h: New file.
  52
  53 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  56         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  57         movdq2q and movq2dq.
  58
  59 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  60            Michael Meissner             <michael.meissner@amd.com>
  61
  62         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  63
  64 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386.h (i386_optab): Add "nop" with memory reference.
  67
  68 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  69
  70         * i386.h (i386_optab): Update comment for 64bit NOP.
  71
  72 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  73             Anton Blanchard  <anton@samba.org>
  74
  75         * ppc.h (PPC_OPCODE_POWER6): Define.
  76         Adjust whitespace.
  77
  78 2006-06-05  Thiemo Seufer  <ths@mips.com>
  79
  80         * mips.h: Improve description of MT flags.
  81
  82 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  83
  84         * m68k.h (mcf_mask): Define.
  85
  86 2006-05-05  Thiemo Seufer  <ths@mips.com>
  87             David Ung  <davidu@mips.com>
  88
  89         * mips.h (enum): Add macro M_CACHE_AB.
  90
  91 2006-05-04  Thiemo Seufer  <ths@mips.com>
  92             Nigel Stephens  <nigel@mips.com>
  93             David Ung  <davidu@mips.com>
  94
  95         * mips.h: Add INSN_SMARTMIPS define.
  96
  97 2006-04-30  Thiemo Seufer  <ths@mips.com>
  98             David Ung  <davidu@mips.com>
  99
 100         * mips.h: Defines udi bits and masks.  Add description of
 101         characters which may appear in the args field of udi
 102         instructions.
 103
 104 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 105
 106         * mips.h: Improve comments describing the bitfield instruction
 107         fields.
 108
 109 2006-04-26  Julian Brown  <julian@codesourcery.com>
 110
 111         * arm.h (FPU_VFP_EXT_V3): Define constant.
 112         (FPU_NEON_EXT_V1): Likewise.
 113         (FPU_VFP_HARD): Update.
 114         (FPU_VFP_V3): Define macro.
 115         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 116
 117 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 118
 119         * avr.h (AVR_ISA_PWMx): New.
 120
 121 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 122
 123         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 124         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 125         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 126         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 127         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 128
 129 2006-03-10  Paul Brook  <paul@codesourcery.com>
 130
 131         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 132
 133 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 134
 135         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 136         first.  Correct mask of bb "B" opcode.
 137
 138 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 139
 140         * i386.h (i386_optab): Support Intel Merom New Instructions.
 141
 142 2006-02-24  Paul Brook  <paul@codesourcery.com>
 143
 144         * arm.h: Add V7 feature bits.
 145
 146 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 149
 150 2006-01-31  Paul Brook  <paul@codesourcery.com>
 151         Richard Earnshaw <rearnsha@arm.com>
 152
 153         * arm.h: Use ARM_CPU_FEATURE.
 154         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 155         (arm_feature_set): Change to a structure.
 156         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 157         ARM_FEATURE): New macros.
 158
 159 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 160
 161         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 162         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 163         (ADD_PC_INCR_OPCODE): Don't define.
 164
 165 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         PR gas/1874
 168         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 169
 170 2005-11-14  David Ung  <davidu@mips.com>
 171
 172         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 173         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 174         save/restore encoding of the args field.
 175
 176 2005-10-28  Dave Brolley  <brolley@redhat.com>
 177
 178         Contribute the following changes:
 179         2005-02-16  Dave Brolley  <brolley@redhat.com>
 180
 181         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 182         cgen_isa_mask_* to cgen_bitset_*.
 183         * cgen.h: Likewise.
 184
 185         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 186
 187         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 188         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 189         (CGEN_CPU_TABLE): Make isas a ponter.
 190
 191         2003-09-29  Dave Brolley  <brolley@redhat.com>
 192
 193         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 194         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 195         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 196
 197         2002-12-13  Dave Brolley  <brolley@redhat.com>
 198
 199         * cgen.h (symcat.h): #include it.
 200         (cgen-bitset.h): #include it.
 201         (CGEN_ATTR_VALUE_TYPE): Now a union.
 202         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 203         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 204         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 205         * cgen-bitset.h: New file.
 206
 207 2005-09-30  Catherine Moore  <clm@cm00re.com>
 208
 209         * bfin.h: New file.
 210
 211 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 212
 213         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 214         indirect operands.
 215
 216 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 217
 218         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 219         Add FLAG_STRICT to pa10 ftest opcode.
 220
 221 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 222
 223         * hppa.h (pa_opcodes): Remove lha entries.
 224
 225 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 226
 227         * hppa.h (FLAG_STRICT): Revise comment.
 228         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 229         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 230         entries for "fdc".
 231
 232 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 233
 234         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 235
 236 2005-09-06  Chao-ying Fu  <fu@mips.com>
 237
 238         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 239         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 240         define.
 241         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 242         (INSN_ASE_MASK): Update to include INSN_MT.
 243         (INSN_MT): New define for MT ASE.
 244
 245 2005-08-25  Chao-ying Fu  <fu@mips.com>
 246
 247         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 248         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 249         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 250         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 251         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 252         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 253         instructions.
 254         (INSN_DSP): New define for DSP ASE.
 255
 256 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 257
 258         * a29k.h: Delete.
 259
 260 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 261
 262         * ppc.h (PPC_OPCODE_E300): Define.
 263
 264 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 265
 266         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 267
 268 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 269
 270         PR gas/336
 271         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 272         and pitlb.
 273
 274 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 275
 276         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 277         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 278         Add movq-s as 64-bit variants of movd-s.
 279
 280 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 281
 282         * hppa.h: Fix punctuation in comment.
 283
 284         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 285         implicit space-register addressing.  Set space-register bits on opcodes
 286         using implicit space-register addressing.  Add various missing pa20
 287         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 288         space-register addressing.  Use "fE" instead of "fe" in various
 289         fstw opcodes.
 290
 291 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 292
 293         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 294
 295 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 296
 297         * i386.h (i386_optab): Support Intel VMX Instructions.
 298
 299 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 300
 301         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 302
 303 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 304
 305         * i386.h (i386_optab): Add new insns.
 306
 307 2005-07-01  Nick Clifton  <nickc@redhat.com>
 308
 309         * sparc.h: Add typedefs to structure declarations.
 310
 311 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         PR 1013
 314         * i386.h (i386_optab): Update comments for 64bit addressing on
 315         mov. Allow 64bit addressing for mov and movq.
 316
 317 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 318
 319         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 320         respectively, in various floating-point load and store patterns.
 321
 322 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 323
 324         * hppa.h (FLAG_STRICT): Correct comment.
 325         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 326         PA 2.0 mneumonics when equivalent.  Entries with cache control
 327         completers now require PA 1.1.  Adjust whitespace.
 328
 329 2005-05-19  Anton Blanchard  <anton@samba.org>
 330
 331         * ppc.h (PPC_OPCODE_POWER5): Define.
 332
 333 2005-05-10  Nick Clifton  <nickc@redhat.com>
 334
 335         * Update the address and phone number of the FSF organization in
 336         the GPL notices in the following files:
 337         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 338         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 339         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 340         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 341         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 342         tic54x.h, tic80.h, v850.h, vax.h
 343
 344 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 345
 346         * i386.h (i386_optab): Add ht and hnt.
 347
 348 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 349
 350         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 351         Add xcrypt-ctr.  Provide aliases without hyphens.
 352
 353 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         Moved from ../ChangeLog
 356
 357         2005-04-12  Paul Brook  <paul@codesourcery.com>
 358         * m88k.h: Rename psr macros to avoid conflicts.
 359
 360         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 361         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 362         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 363         and ARM_ARCH_V6ZKT2.
 364
 365         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 366         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 367         Remove redundant instruction types.
 368         (struct argument): X_op - new field.
 369         (struct cst4_entry): Remove.
 370         (no_op_insn): Declare.
 371
 372         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 373         * crx.h (enum argtype): Rename types, remove unused types.
 374
 375         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 376         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 377         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 378         (enum operand_type): Rearrange operands, edit comments.
 379         replace us<N> with ui<N> for unsigned immediate.
 380         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 381         displacements (respectively).
 382         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 383         (instruction type): Add NO_TYPE_INS.
 384         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 385         (operand_entry): New field - 'flags'.
 386         (operand flags): New.
 387
 388         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 389         * crx.h (operand_type): Remove redundant types i3, i4,
 390         i5, i8, i12.
 391         Add new unsigned immediate types us3, us4, us5, us16.
 392
 393 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 394
 395         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 396         adjust them accordingly.
 397
 398 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 399
 400         * i386.h (i386_optab): Add rdtscp.
 401
 402 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 405         between memory and segment register. Allow movq for moving between
 406         general-purpose register and segment register.
 407
 408 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 409
 410         PR gas/707
 411         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 412         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 413         fnstsw.
 414
 415 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 416
 417         * m68k.h (m68008, m68ec030, m68882): Remove.
 418         (m68k_mask): New.
 419         (cpu_m68k, cpu_cf): New.
 420         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 421         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 422
 423 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 424
 425         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 426         * cgen.h (enum cgen_parse_operand_type): Add
 427         CGEN_PARSE_OPERAND_SYMBOLIC.
 428
 429 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 430
 431         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 432         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 433         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 434
 435 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 436
 437         * mips.h (struct mips_opcode): Add new pinfo2 member.
 438         (INSN_ALIAS): New define for opcode table entries that are
 439         specific instances of another entry, such as 'move' for an 'or'
 440         with a zero operand.
 441         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 442         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 443
 444 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 445
 446         * mips.h (CPU_RM9000): Define.
 447         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 448
 449 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 450
 451         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 452         to/from test registers are illegal in 64-bit mode. Add missing
 453         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 454         (previously one had to explicitly encode a rex64 prefix). Re-enable
 455         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 456         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 457
 458 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 459
 460         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 461         available only with SSE2. Change the MMX additions introduced by SSE
 462         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 463         instructions by their now designated identifier (since combining i686
 464         and 3DNow! does not really imply 3DNow!A).
 465
 466 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 467
 468         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 469         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 470
 471 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 472             Vineet Sharma      <vineets@noida.hcltech.com>
 473
 474         * maxq.h: New file: Disassembly information for the maxq port.
 475
 476 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 477
 478         * i386.h (i386_optab): Put back "movzb".
 479
 480 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 481
 482         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 483         comments.  Remove member cris_ver_sim.  Add members
 484         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 485         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 486         (struct cris_support_reg, struct cris_cond15): New types.
 487         (cris_conds15): Declare.
 488         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 489         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 490         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 491         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 492         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 493         SIZE_FIELD_UNSIGNED.
 494
 495 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 496
 497         * i386.h (sldx_Suf): Remove.
 498         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 499         (q_FP): Define, implying no REX64.
 500         (x_FP, sl_FP): Imply FloatMF.
 501         (i386_optab): Split reg and mem forms of moving from segment registers
 502         so that the memory forms can ignore the 16-/32-bit operand size
 503         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 504         all non-floating-point instructions. Unite 32- and 64-bit forms of
 505         movsx, movzx, and movd. Adjust floating point operations for the above
 506         changes to the *FP macros. Add DefaultSize to floating point control
 507         insns operating on larger memory ranges. Remove left over comments
 508         hinting at certain insns being Intel-syntax ones where the ones
 509         actually meant are already gone.
 510
 511 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 512
 513         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 514         instruction type.
 515
 516 2004-09-30  Paul Brook  <paul@codesourcery.com>
 517
 518         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 519         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 520
 521 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 522
 523         * avr.h: Add support for
 524         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 525
 526 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 527
 528         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 529
 530 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 531
 532         * msp430.h (msp430_opc): Add new instructions.
 533         (msp430_rcodes): Declare new instructions.
 534         (msp430_hcodes): Likewise..
 535
 536 2004-08-13  Nick Clifton  <nickc@redhat.com>
 537
 538         PR/301
 539         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 540         processors.
 541
 542 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 543
 544         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 545
 546 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 549
 550 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 551
 552         * i386.h: Adjust instruction descriptions to better match the
 553         specification.
 554
 555 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 556
 557         * arm.h: Remove all old content.  Replace with architecture defines
 558         from gas/config/tc-arm.c.
 559
 560 2004-07-09  Andreas Schwab  <schwab@suse.de>
 561
 562         * m68k.h: Fix comment.
 563
 564 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 565
 566         * crx.h: New file.
 567
 568 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 569
 570         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 571
 572 2004-05-24  Peter Barada  <peter@the-baradas.com>
 573
 574         * m68k.h: Add 'size' to m68k_opcode.
 575
 576 2004-05-05  Peter Barada  <peter@the-baradas.com>
 577
 578         * m68k.h: Switch from ColdFire chip name to core variant.
 579
 580 2004-04-22  Peter Barada  <peter@the-baradas.com>
 581
 582         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 583         descriptions for new EMAC cases.
 584         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 585         handle Motorola MAC syntax.
 586         Allow disassembly of ColdFire V4e object files.
 587
 588 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 589
 590         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 591
 592 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 593
 594         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 595
 596 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 597
 598         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 599
 600 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 601
 602         * i386.h (i386_optab): Added xstore/xcrypt insns.
 603
 604 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 605
 606         * h8300.h (32bit ldc/stc): Add relaxing support.
 607
 608 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 609
 610         * h8300.h (BITOP): Pass MEMRELAX flag.
 611
 612 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 613
 614         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 615         except for the H8S.
 616
 617 For older changes see ChangeLog-9103
 618 \f
 619 Local Variables:
 620 mode: change-log
 621 left-margin: 8
 622 fill-column: 74
 623 version-control: never
 624 End: