include/opcode/ChangeLog

   1 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
   2
   3         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
   4         (num_powerpc_operands): Declare.
   5         (PPC_OPERAND_SIGNED et al): Redefine as hex.
   6         (PPC_OPERAND_PLUS1): Define.
   7
   8 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         * i386.h (REX_MODE64): Renamed to ...
  11         (REX_W): This.
  12         (REX_EXTX): Renamed to ...
  13         (REX_R): This.
  14         (REX_EXTY): Renamed to ...
  15         (REX_X): This.
  16         (REX_EXTZ): Renamed to ...
  17         (REX_B): This.
  18
  19 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         * i386.h: Add entries from config/tc-i386.h and move tables
  22         to opcodes/i386-opc.h.
  23
  24 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         * i386.h (FloatDR): Removed.
  27         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  28
  29 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  30
  31         * spu-insns.h: Add soma double-float insns.
  32
  33 2007-02-20  Thiemo Seufer  <ths@mips.com>
  34             Chao-Ying Fu  <fu@mips.com>
  35
  36         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  37         (INSN_DSPR2): Add flag for DSP R2 instructions.
  38         (M_BALIGN): New macro.
  39
  40 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  41
  42         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  43         and Seg3ShortFrom with Shortform.
  44
  45 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         PR gas/4027
  48         * i386.h (i386_optab): Put the real "test" before the pseudo
  49         one.
  50
  51 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  52
  53         * m68k.h (m68010up): OR fido_a.
  54
  55 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  56
  57         * m68k.h (fido_a): New.
  58
  59 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  60
  61         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  62         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  63         values.
  64
  65 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  68
  69 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  70
  71         * score-inst.h (enum score_insn_type): Add Insn_internal.
  72
  73 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  74             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  75             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  76             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  77             Alan Modra  <amodra@bigpond.net.au>
  78
  79         * spu-insns.h: New file.
  80         * spu.h: New file.
  81
  82 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  83
  84         * ppc.h (PPC_OPCODE_CELL): Define.
  85
  86 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  87
  88         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  89         in amdfam10 architecture.
  90
  91 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         * i386.h: Replace CpuMNI with CpuSSSE3.
  94
  95 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  96             Joseph Myers  <joseph@codesourcery.com>
  97             Ian Lance Taylor  <ian@wasabisystems.com>
  98             Ben Elliston  <bje@wasabisystems.com>
  99
 100         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 101
 102 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 103
 104         * score-datadep.h: New file.
 105         * score-inst.h: New file.
 106
 107 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 108
 109         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 110         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 111         movdq2q and movq2dq.
 112
 113 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 114            Michael Meissner             <michael.meissner@amd.com>
 115
 116         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 117
 118 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         * i386.h (i386_optab): Add "nop" with memory reference.
 121
 122 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         * i386.h (i386_optab): Update comment for 64bit NOP.
 125
 126 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 127             Anton Blanchard  <anton@samba.org>
 128
 129         * ppc.h (PPC_OPCODE_POWER6): Define.
 130         Adjust whitespace.
 131
 132 2006-06-05  Thiemo Seufer  <ths@mips.com>
 133
 134         * mips.h: Improve description of MT flags.
 135
 136 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 137
 138         * m68k.h (mcf_mask): Define.
 139
 140 2006-05-05  Thiemo Seufer  <ths@mips.com>
 141             David Ung  <davidu@mips.com>
 142
 143         * mips.h (enum): Add macro M_CACHE_AB.
 144
 145 2006-05-04  Thiemo Seufer  <ths@mips.com>
 146             Nigel Stephens  <nigel@mips.com>
 147             David Ung  <davidu@mips.com>
 148
 149         * mips.h: Add INSN_SMARTMIPS define.
 150
 151 2006-04-30  Thiemo Seufer  <ths@mips.com>
 152             David Ung  <davidu@mips.com>
 153
 154         * mips.h: Defines udi bits and masks.  Add description of
 155         characters which may appear in the args field of udi
 156         instructions.
 157
 158 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 159
 160         * mips.h: Improve comments describing the bitfield instruction
 161         fields.
 162
 163 2006-04-26  Julian Brown  <julian@codesourcery.com>
 164
 165         * arm.h (FPU_VFP_EXT_V3): Define constant.
 166         (FPU_NEON_EXT_V1): Likewise.
 167         (FPU_VFP_HARD): Update.
 168         (FPU_VFP_V3): Define macro.
 169         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 170
 171 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 172
 173         * avr.h (AVR_ISA_PWMx): New.
 174
 175 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 176
 177         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 178         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 179         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 180         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 181         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 182
 183 2006-03-10  Paul Brook  <paul@codesourcery.com>
 184
 185         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 186
 187 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 188
 189         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 190         first.  Correct mask of bb "B" opcode.
 191
 192 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 193
 194         * i386.h (i386_optab): Support Intel Merom New Instructions.
 195
 196 2006-02-24  Paul Brook  <paul@codesourcery.com>
 197
 198         * arm.h: Add V7 feature bits.
 199
 200 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 201
 202         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 203
 204 2006-01-31  Paul Brook  <paul@codesourcery.com>
 205         Richard Earnshaw <rearnsha@arm.com>
 206
 207         * arm.h: Use ARM_CPU_FEATURE.
 208         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 209         (arm_feature_set): Change to a structure.
 210         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 211         ARM_FEATURE): New macros.
 212
 213 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 214
 215         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 216         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 217         (ADD_PC_INCR_OPCODE): Don't define.
 218
 219 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         PR gas/1874
 222         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 223
 224 2005-11-14  David Ung  <davidu@mips.com>
 225
 226         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 227         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 228         save/restore encoding of the args field.
 229
 230 2005-10-28  Dave Brolley  <brolley@redhat.com>
 231
 232         Contribute the following changes:
 233         2005-02-16  Dave Brolley  <brolley@redhat.com>
 234
 235         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 236         cgen_isa_mask_* to cgen_bitset_*.
 237         * cgen.h: Likewise.
 238
 239         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 240
 241         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 242         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 243         (CGEN_CPU_TABLE): Make isas a ponter.
 244
 245         2003-09-29  Dave Brolley  <brolley@redhat.com>
 246
 247         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 248         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 249         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 250
 251         2002-12-13  Dave Brolley  <brolley@redhat.com>
 252
 253         * cgen.h (symcat.h): #include it.
 254         (cgen-bitset.h): #include it.
 255         (CGEN_ATTR_VALUE_TYPE): Now a union.
 256         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 257         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 258         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 259         * cgen-bitset.h: New file.
 260
 261 2005-09-30  Catherine Moore  <clm@cm00re.com>
 262
 263         * bfin.h: New file.
 264
 265 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 266
 267         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 268         indirect operands.
 269
 270 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 271
 272         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 273         Add FLAG_STRICT to pa10 ftest opcode.
 274
 275 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 276
 277         * hppa.h (pa_opcodes): Remove lha entries.
 278
 279 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 280
 281         * hppa.h (FLAG_STRICT): Revise comment.
 282         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 283         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 284         entries for "fdc".
 285
 286 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 287
 288         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 289
 290 2005-09-06  Chao-ying Fu  <fu@mips.com>
 291
 292         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 293         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 294         define.
 295         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 296         (INSN_ASE_MASK): Update to include INSN_MT.
 297         (INSN_MT): New define for MT ASE.
 298
 299 2005-08-25  Chao-ying Fu  <fu@mips.com>
 300
 301         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 302         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 303         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 304         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 305         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 306         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 307         instructions.
 308         (INSN_DSP): New define for DSP ASE.
 309
 310 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 311
 312         * a29k.h: Delete.
 313
 314 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 315
 316         * ppc.h (PPC_OPCODE_E300): Define.
 317
 318 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 319
 320         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 321
 322 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 323
 324         PR gas/336
 325         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 326         and pitlb.
 327
 328 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 329
 330         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 331         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 332         Add movq-s as 64-bit variants of movd-s.
 333
 334 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 335
 336         * hppa.h: Fix punctuation in comment.
 337
 338         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 339         implicit space-register addressing.  Set space-register bits on opcodes
 340         using implicit space-register addressing.  Add various missing pa20
 341         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 342         space-register addressing.  Use "fE" instead of "fe" in various
 343         fstw opcodes.
 344
 345 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 346
 347         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 348
 349 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 350
 351         * i386.h (i386_optab): Support Intel VMX Instructions.
 352
 353 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 354
 355         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 356
 357 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 358
 359         * i386.h (i386_optab): Add new insns.
 360
 361 2005-07-01  Nick Clifton  <nickc@redhat.com>
 362
 363         * sparc.h: Add typedefs to structure declarations.
 364
 365 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         PR 1013
 368         * i386.h (i386_optab): Update comments for 64bit addressing on
 369         mov. Allow 64bit addressing for mov and movq.
 370
 371 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 372
 373         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 374         respectively, in various floating-point load and store patterns.
 375
 376 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 377
 378         * hppa.h (FLAG_STRICT): Correct comment.
 379         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 380         PA 2.0 mneumonics when equivalent.  Entries with cache control
 381         completers now require PA 1.1.  Adjust whitespace.
 382
 383 2005-05-19  Anton Blanchard  <anton@samba.org>
 384
 385         * ppc.h (PPC_OPCODE_POWER5): Define.
 386
 387 2005-05-10  Nick Clifton  <nickc@redhat.com>
 388
 389         * Update the address and phone number of the FSF organization in
 390         the GPL notices in the following files:
 391         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 392         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 393         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 394         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 395         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 396         tic54x.h, tic80.h, v850.h, vax.h
 397
 398 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 399
 400         * i386.h (i386_optab): Add ht and hnt.
 401
 402 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 403
 404         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 405         Add xcrypt-ctr.  Provide aliases without hyphens.
 406
 407 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         Moved from ../ChangeLog
 410
 411         2005-04-12  Paul Brook  <paul@codesourcery.com>
 412         * m88k.h: Rename psr macros to avoid conflicts.
 413
 414         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 415         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 416         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 417         and ARM_ARCH_V6ZKT2.
 418
 419         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 420         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 421         Remove redundant instruction types.
 422         (struct argument): X_op - new field.
 423         (struct cst4_entry): Remove.
 424         (no_op_insn): Declare.
 425
 426         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 427         * crx.h (enum argtype): Rename types, remove unused types.
 428
 429         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 430         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 431         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 432         (enum operand_type): Rearrange operands, edit comments.
 433         replace us<N> with ui<N> for unsigned immediate.
 434         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 435         displacements (respectively).
 436         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 437         (instruction type): Add NO_TYPE_INS.
 438         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 439         (operand_entry): New field - 'flags'.
 440         (operand flags): New.
 441
 442         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 443         * crx.h (operand_type): Remove redundant types i3, i4,
 444         i5, i8, i12.
 445         Add new unsigned immediate types us3, us4, us5, us16.
 446
 447 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 448
 449         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 450         adjust them accordingly.
 451
 452 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 453
 454         * i386.h (i386_optab): Add rdtscp.
 455
 456 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 459         between memory and segment register. Allow movq for moving between
 460         general-purpose register and segment register.
 461
 462 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 463
 464         PR gas/707
 465         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 466         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 467         fnstsw.
 468
 469 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 470
 471         * m68k.h (m68008, m68ec030, m68882): Remove.
 472         (m68k_mask): New.
 473         (cpu_m68k, cpu_cf): New.
 474         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 475         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 476
 477 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 478
 479         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 480         * cgen.h (enum cgen_parse_operand_type): Add
 481         CGEN_PARSE_OPERAND_SYMBOLIC.
 482
 483 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 484
 485         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 486         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 487         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 488
 489 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 490
 491         * mips.h (struct mips_opcode): Add new pinfo2 member.
 492         (INSN_ALIAS): New define for opcode table entries that are
 493         specific instances of another entry, such as 'move' for an 'or'
 494         with a zero operand.
 495         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 496         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 497
 498 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 499
 500         * mips.h (CPU_RM9000): Define.
 501         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 502
 503 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 504
 505         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 506         to/from test registers are illegal in 64-bit mode. Add missing
 507         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 508         (previously one had to explicitly encode a rex64 prefix). Re-enable
 509         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 510         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 511
 512 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 513
 514         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 515         available only with SSE2. Change the MMX additions introduced by SSE
 516         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 517         instructions by their now designated identifier (since combining i686
 518         and 3DNow! does not really imply 3DNow!A).
 519
 520 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 521
 522         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 523         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 524
 525 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 526             Vineet Sharma      <vineets@noida.hcltech.com>
 527
 528         * maxq.h: New file: Disassembly information for the maxq port.
 529
 530 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         * i386.h (i386_optab): Put back "movzb".
 533
 534 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 535
 536         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 537         comments.  Remove member cris_ver_sim.  Add members
 538         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 539         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 540         (struct cris_support_reg, struct cris_cond15): New types.
 541         (cris_conds15): Declare.
 542         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 543         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 544         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 545         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 546         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 547         SIZE_FIELD_UNSIGNED.
 548
 549 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 550
 551         * i386.h (sldx_Suf): Remove.
 552         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 553         (q_FP): Define, implying no REX64.
 554         (x_FP, sl_FP): Imply FloatMF.
 555         (i386_optab): Split reg and mem forms of moving from segment registers
 556         so that the memory forms can ignore the 16-/32-bit operand size
 557         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 558         all non-floating-point instructions. Unite 32- and 64-bit forms of
 559         movsx, movzx, and movd. Adjust floating point operations for the above
 560         changes to the *FP macros. Add DefaultSize to floating point control
 561         insns operating on larger memory ranges. Remove left over comments
 562         hinting at certain insns being Intel-syntax ones where the ones
 563         actually meant are already gone.
 564
 565 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 566
 567         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 568         instruction type.
 569
 570 2004-09-30  Paul Brook  <paul@codesourcery.com>
 571
 572         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 573         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 574
 575 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 576
 577         * avr.h: Add support for
 578         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 579
 580 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 581
 582         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 583
 584 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 585
 586         * msp430.h (msp430_opc): Add new instructions.
 587         (msp430_rcodes): Declare new instructions.
 588         (msp430_hcodes): Likewise..
 589
 590 2004-08-13  Nick Clifton  <nickc@redhat.com>
 591
 592         PR/301
 593         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 594         processors.
 595
 596 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 597
 598         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 599
 600 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 603
 604 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 605
 606         * i386.h: Adjust instruction descriptions to better match the
 607         specification.
 608
 609 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 610
 611         * arm.h: Remove all old content.  Replace with architecture defines
 612         from gas/config/tc-arm.c.
 613
 614 2004-07-09  Andreas Schwab  <schwab@suse.de>
 615
 616         * m68k.h: Fix comment.
 617
 618 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 619
 620         * crx.h: New file.
 621
 622 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 623
 624         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 625
 626 2004-05-24  Peter Barada  <peter@the-baradas.com>
 627
 628         * m68k.h: Add 'size' to m68k_opcode.
 629
 630 2004-05-05  Peter Barada  <peter@the-baradas.com>
 631
 632         * m68k.h: Switch from ColdFire chip name to core variant.
 633
 634 2004-04-22  Peter Barada  <peter@the-baradas.com>
 635
 636         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 637         descriptions for new EMAC cases.
 638         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 639         handle Motorola MAC syntax.
 640         Allow disassembly of ColdFire V4e object files.
 641
 642 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 643
 644         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 645
 646 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 647
 648         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 649
 650 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 651
 652         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 653
 654 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 655
 656         * i386.h (i386_optab): Added xstore/xcrypt insns.
 657
 658 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 659
 660         * h8300.h (32bit ldc/stc): Add relaxing support.
 661
 662 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 663
 664         * h8300.h (BITOP): Pass MEMRELAX flag.
 665
 666 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 667
 668         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 669         except for the H8S.
 670
 671 For older changes see ChangeLog-9103
 672 \f
 673 Local Variables:
 674 mode: change-log
 675 left-margin: 8
 676 fill-column: 74
 677 version-control: never
 678 End: