include/opcode/ChangeLog

   1 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
   2
   3         * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
   4         (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
   5         (aarch64_insn_class): Add lse_atomic.
   6         (F_LSE_SZ): New field added.
   7         (opcode_has_special_coder): Recognize F_LSE_SZ.
   8
   9 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
  10
  11         * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
  12         over to `+J'.
  13
  14 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
  15
  16         * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
  17         (INSN_LOAD_COPROC): New define.
  18         (INSN_COPROC_MOVE_DELAY): Rename to...
  19         (INSN_COPROC_MOVE): New define.
  20
  21 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
  22             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
  23             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
  24             Soundararajan  <Sounderarajan.D@atmel.com>
  25
  26         * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
  27         (AVR_ISA_2xxxa): Define ISA without LPM.
  28         (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
  29         Add doc for contraint used in 16 bit lds/sts.
  30         Adjust ISA group for icall, ijmp, pop and push.
  31         Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
  32
  33 2014-05-19  Nick Clifton  <nickc@redhat.com>
  34
  35         * msp430.h (struct msp430_operand_s): Add vshift field.
  36
  37 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
  38
  39         * mips.h (INSN_ISA_MASK): Updated.
  40         (INSN_ISA32R3): New define.
  41         (INSN_ISA32R5): New define.
  42         (INSN_ISA64R3): New define.
  43         (INSN_ISA64R5): New define.
  44         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
  45         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
  46         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
  47         mips64r5.
  48         (INSN_UPTO32R3): New define.
  49         (INSN_UPTO32R5): New define.
  50         (INSN_UPTO64R3): New define.
  51         (INSN_UPTO64R5): New define.
  52         (ISA_MIPS32R3): New define.
  53         (ISA_MIPS32R5): New define.
  54         (ISA_MIPS64R3): New define.
  55         (ISA_MIPS64R5): New define.
  56         (CPU_MIPS32R3): New define.
  57         (CPU_MIPS32R5): New define.
  58         (CPU_MIPS64R3): New define.
  59         (CPU_MIPS64R5): New define.
  60
  61 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
  62
  63         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
  64
  65 2014-04-22  Christian Svensson  <blue@cmd.nu>
  66
  67         * or32.h: Delete.
  68
  69 2014-03-05  Alan Modra  <amodra@gmail.com>
  70
  71         Update copyright years.
  72
  73 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  74
  75         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
  76         microMIPS.
  77
  78 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  79             Wei-Cheng Wang  <cole945@gmail.com>
  80
  81         * nds32.h: New file for Andes NDS32.
  82
  83 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
  84
  85         * bfin.h: Remove +x file mode.
  86
  87 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  88
  89         * aarch64.h (aarch64_pstatefields): Change element type to
  90         aarch64_sys_reg.
  91
  92 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  93
  94         * arm.h (ARM_AEXT_V7VE): New define.
  95         (ARM_ARCH_V7VE): New define.
  96         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  97
  98 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  99
 100         Revert
 101
 102         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 103
 104         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 105         (aarch64_sys_reg_writeonly_p): Ditto.
 106
 107 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 108
 109         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 110         (aarch64_sys_reg_writeonly_p): Ditto.
 111
 112 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 113
 114         * aarch64.h (aarch64_sys_reg): New typedef.
 115         (aarch64_sys_regs): Change to define with the new type.
 116         (aarch64_sys_reg_deprecated_p): Declare.
 117
 118 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 119
 120         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
 121         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
 122
 123 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 124
 125         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
 126         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
 127         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 128         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 129         For MIPS, update extension character sequences after +.
 130         (ASE_MSA): New define.
 131         (ASE_MSA64): New define.
 132         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 133         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 134         For microMIPS, update extension character sequences after +.
 135
 136 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 137
 138         PR binutils/15834
 139         * i960.h: Fix typos.
 140
 141 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 142
 143         * mips.h: Remove references to "+I" and imm2_expr.
 144
 145 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 146
 147         * mips.h (M_DEXT, M_DINS): Delete.
 148
 149 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 150
 151         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 152         (mips_optional_operand_p): New function.
 153
 154 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 155             Richard Sandiford  <rdsandiford@googlemail.com>
 156
 157         * mips.h: Document new VU0 operand characters.
 158         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 159         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 160         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 161         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 162         (mips_vu0_channel_mask): Declare.
 163
 164 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 165
 166         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 167         (mips_int_operand_min, mips_int_operand_max): New functions.
 168         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 169
 170 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 171
 172         * mips.h (mips_decode_reg_operand): New function.
 173         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 174         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 175         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 176         New macros.
 177         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 178         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 179         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 180         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 181         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 182         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 183         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 184         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 185         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 186         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 187         macros to cover the gaps.
 188         (INSN2_MOD_SP): Replace with...
 189         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 190         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 191         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 192         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 193         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 194         Delete.
 195
 196 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 197
 198         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 199         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 200         (MIPS16_INSN_COND_BRANCH): Delete.
 201
 202 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 203             Kirill Yukhin  <kirill.yukhin@intel.com>
 204             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 205
 206         * i386.h (BND_PREFIX_OPCODE): New.
 207
 208 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 209
 210         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 211         OP_SAVE_RESTORE_LIST.
 212         (decode_mips16_operand): Declare.
 213
 214 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 215
 216         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 217         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 218         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 219         (mips_pcrel_operand): New structures.
 220         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 221         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 222         (decode_mips_operand, decode_micromips_operand): Declare.
 223
 224 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 225
 226         * mips.h: Document MIPS16 "I" opcode.
 227
 228 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 229
 230         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 231         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 232         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 233         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 234         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 235         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 236         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 237         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 238         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 239         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 240         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 241         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 242         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 243         Rename to...
 244         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 245         (M_USD_AB): ...these.
 246
 247 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 248
 249         * mips.h: Remove documentation of "[" and "]".  Update documentation
 250         of "k" and the MDMX formats.
 251
 252 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 253
 254         * mips.h: Update documentation of "+s" and "+S".
 255
 256 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 257
 258         * mips.h: Document "+i".
 259
 260 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 261
 262         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 263         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 264         Delete.
 265         (INSN2_WRITE_GPR_MHI): Rename to...
 266         (INSN2_WRITE_GPR_MH): ...this.
 267
 268 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 269
 270         * mips.h: Remove documentation of "+D" and "+T".
 271
 272 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 273
 274         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 275         Use "source" rather than "destination" for microMIPS "G".
 276
 277 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 278
 279         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 280         values.
 281
 282 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 283
 284         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 285
 286 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 287             Maciej W. Rozycki  <macro@codesourcery.com>
 288             Chao-Ying Fu  <fu@mips.com>
 289
 290         * mips.h (OP_SH_EVAOFFSET): Define.
 291         (OP_MASK_EVAOFFSET): Define.
 292         (INSN_ASE_MASK): Delete.
 293         (ASE_EVA): Define.
 294         (M_CACHEE_AB, M_CACHEE_OB): New.
 295         (M_LBE_OB, M_LBE_AB): New.
 296         (M_LBUE_OB, M_LBUE_AB): New.
 297         (M_LHE_OB, M_LHE_AB): New.
 298         (M_LHUE_OB, M_LHUE_AB): New.
 299         (M_LLE_AB, M_LLE_OB): New.
 300         (M_LWE_OB, M_LWE_AB): New.
 301         (M_LWLE_AB, M_LWLE_OB): New.
 302         (M_LWRE_AB, M_LWRE_OB): New.
 303         (M_PREFE_AB, M_PREFE_OB): New.
 304         (M_SCE_AB, M_SCE_OB): New.
 305         (M_SBE_OB, M_SBE_AB): New.
 306         (M_SHE_OB, M_SHE_AB): New.
 307         (M_SWE_OB, M_SWE_AB): New.
 308         (M_SWLE_AB, M_SWLE_OB): New.
 309         (M_SWRE_AB, M_SWRE_OB): New.
 310         (MICROMIPSOP_SH_EVAOFFSET): Define.
 311         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 312
 313 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 314
 315         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 316
 317 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 318
 319         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 320
 321 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 322
 323         * mips.h (OP_MASK_CODE10): Correct definition.
 324         (OP_SH_CODE10): Likewise.
 325         Add a comment that "+J" is used now for OP_*CODE10.
 326         (INSN_ASE_MASK): Update.
 327         (INSN_VIRT): New macro.
 328         (INSN_VIRT64): New macro
 329
 330 2013-05-02  Nick Clifton  <nickc@redhat.com>
 331
 332         * msp430.h: Add patterns for MSP430X instructions.
 333
 334 2013-04-06  David S. Miller  <davem@davemloft.net>
 335
 336         * sparc.h (F_PREFERRED): Define.
 337         (F_PREF_ALIAS): Define.
 338
 339 2013-04-03  Nick Clifton  <nickc@redhat.com>
 340
 341         * v850.h (V850_INVERSE_PCREL): Define.
 342
 343 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 344
 345         PR binutils/15068
 346         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 347
 348 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 349
 350         PR binutils/15068
 351         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 352         Add 16-bit opcodes.
 353         * tic6xc-opcode-table.h: Add 16-bit insns.
 354         * tic6x.h: Add support for 16-bit insns.
 355
 356 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 357
 358         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 359         and mov.b/w/l Rs,@(d:32,ERd).
 360
 361 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 362
 363         PR gas/15082
 364         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 365         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 366         tic6x_operand_xregpair operand coding type.
 367         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 368         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 369         TIC6X_FLAG_NO_CROSS.
 370
 371 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 372
 373         PR gas/15095
 374         * tic6x.h (enum tic6x_coding_method): Add
 375         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 376         separately the msb and lsb of a register pair.  This is needed to
 377         encode the opcodes in the same way as TI assembler does.
 378         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 379         and rsqrdp opcodes to use the new field coding types.
 380
 381 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 382
 383         * arm.h (CRC_EXT_ARMV8): New constant.
 384         (ARCH_CRC_ARMV8): New macro.
 385
 386 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 387
 388         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 389
 390 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 391             Andrew Jenner <andrew@codesourcery.com>
 392
 393         Based on patches from Altera Corporation.
 394
 395         * nios2.h: New file.
 396
 397 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 398
 399         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 400
 401 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 402
 403         PR gas/15069
 404         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 405
 406 2013-01-24  Nick Clifton  <nickc@redhat.com>
 407
 408         * v850.h: Add e3v5 support.
 409
 410 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 411
 412         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 413
 414 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 415
 416         * ppc.h (PPC_OPCODE_POWER8): New define.
 417         (PPC_OPCODE_HTM): Likewise.
 418
 419 2013-01-10  Will Newton <will.newton@imgtec.com>
 420
 421         * metag.h: New file.
 422
 423 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 424
 425         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 426         (match_opcode): Rename to cr16_match_opcode.
 427
 428 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 429
 430         * mips.h: Add support for r5900 instructions including lq and sq.
 431
 432 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 433
 434         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 435         (make_instruction,match_opcode): Added function prototypes.
 436         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 437
 438 2012-11-23  Alan Modra  <amodra@gmail.com>
 439
 440         * ppc.h (ppc_parse_cpu): Update prototype.
 441
 442 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 443
 444         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 445         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 446
 447 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 448
 449         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 450
 451 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 452
 453         * ia64.h (ia64_opnd): Add new operand types.
 454
 455 2012-08-21  David S. Miller  <davem@davemloft.net>
 456
 457         * sparc.h (F3F4): New macro.
 458
 459 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 460             Laurent Desnogues  <laurent.desnogues@arm.com>
 461             Jim MacArthur  <jim.macarthur@arm.com>
 462             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 463             Nigel Stephens  <nigel.stephens@arm.com>
 464             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 465             Richard Earnshaw  <rearnsha@arm.com>
 466             Sofiane Naci  <sofiane.naci@arm.com>
 467             Tejas Belagod  <tejas.belagod@arm.com>
 468             Yufeng Zhang  <yufeng.zhang@arm.com>
 469
 470         * aarch64.h: New file.
 471
 472 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 473             Maciej W. Rozycki  <macro@codesourcery.com>
 474
 475         * mips.h (mips_opcode): Add the exclusions field.
 476         (OPCODE_IS_MEMBER): Remove macro.
 477         (cpu_is_member): New inline function.
 478         (opcode_is_member): Likewise.
 479
 480 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 481             Catherine Moore  <clm@codesourcery.com>
 482             Maciej W. Rozycki  <macro@codesourcery.com>
 483
 484         * mips.h: Document microMIPS DSP ASE usage.
 485         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 486         microMIPS DSP ASE support.
 487         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 488         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 489         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 490         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 491         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 492         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 493         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 494
 495 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 496
 497         * mips.h: Fix a typo in description.
 498
 499 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 500
 501         * avr.h: (AVR_ISA_XCH): New define.
 502         (AVR_ISA_XMEGA): Use it.
 503         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 504
 505 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 506
 507         * m68hc11.h: Add XGate definitions.
 508         (struct m68hc11_opcode): Add xg_mask field.
 509
 510 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 511             Maciej W. Rozycki  <macro@codesourcery.com>
 512             Rhonda Wittels  <rhonda@codesourcery.com>
 513
 514         * ppc.h (PPC_OPCODE_VLE): New definition.
 515         (PPC_OP_SA): New macro.
 516         (PPC_OP_SE_VLE): New macro.
 517         (PPC_OP): Use a variable shift amount.
 518         (powerpc_operand): Update comments.
 519         (PPC_OPSHIFT_INV): New macro.
 520         (PPC_OPERAND_CR): Replace with...
 521         (PPC_OPERAND_CR_BIT): ...this and
 522         (PPC_OPERAND_CR_REG): ...this.
 523
 524
 525 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 526
 527         * xgate.h: Header file for XGATE assembler.
 528
 529 2012-04-27  David S. Miller  <davem@davemloft.net>
 530
 531         * sparc.h: Document new arg code' )' for crypto RS3
 532         immediates.
 533
 534         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 535         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 536         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 537         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 538         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 539         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 540         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 541         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 542         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 543         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 544         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 545
 546 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 547
 548         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 549
 550 2012-02-27  Alan Modra  <amodra@gmail.com>
 551
 552         * crx.h (cst4_map): Update declaration.
 553
 554 2012-02-25  Walter Lee  <walt@tilera.com>
 555
 556         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 557         TILEGX_OPC_LD_TLS.
 558         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 559         TILEPRO_OPC_LW_TLS_SN.
 560
 561 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 564         (XRELEASE_PREFIX_OPCODE): Likewise.
 565
 566 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 567             Adam Nemet  <anemet@caviumnetworks.com>
 568
 569         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 570         (INSN_OCTEON2): New macro.
 571         (CPU_OCTEON2): New macro.
 572         (OPCODE_IS_MEMBER): Add Octeon2.
 573
 574 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 575
 576         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 577         (INSN_OCTEONP): New macro.
 578         (CPU_OCTEONP): New macro.
 579         (OPCODE_IS_MEMBER): Add Octeon+.
 580         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 581
 582 2011-11-01  DJ Delorie  <dj@redhat.com>
 583
 584         * rl78.h: New file.
 585
 586 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 587
 588         * mips.h: Fix a typo in description.
 589
 590 2011-09-21  David S. Miller  <davem@davemloft.net>
 591
 592         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 593         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 594         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 595         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 596
 597 2011-08-09  Chao-ying Fu  <fu@mips.com>
 598             Maciej W. Rozycki  <macro@codesourcery.com>
 599
 600         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 601         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 602         (INSN_ASE_MASK): Add the MCU bit.
 603         (INSN_MCU): New macro.
 604         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 605         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 606
 607 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 608
 609         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 610         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 611         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 612         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 613         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 614         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 615         (INSN2_READ_GPR_MMN): Likewise.
 616         (INSN2_READ_FPR_D): Change the bit used.
 617         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 618         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 619         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 620         (INSN2_COND_BRANCH): Likewise.
 621         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 622         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 623         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 624         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 625         (INSN2_MOD_GPR_MN): Likewise.
 626
 627 2011-08-05  David S. Miller  <davem@davemloft.net>
 628
 629         * sparc.h: Document new format codes '4', '5', and '('.
 630         (OPF_LOW4, RS3): New macros.
 631
 632 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 633
 634         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 635         order of flags documented.
 636
 637 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 638
 639         * mips.h: Clarify the description of microMIPS instruction
 640         manipulation macros.
 641         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 642
 643 2011-07-24  Chao-ying Fu  <fu@mips.com>
 644             Maciej W. Rozycki  <macro@codesourcery.com>
 645
 646         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 647         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 648         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 649         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 650         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 651         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 652         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 653         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 654         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 655         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 656         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 657         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 658         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 659         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 660         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 661         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 662         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 663         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 664         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 665         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 666         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 667         (INSN_WRITE_GPR_S): New macro.
 668         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 669         (INSN2_READ_FPR_D): Likewise.
 670         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 671         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 672         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 673         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 674         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 675         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 676         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 677         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 678         (CPU_MICROMIPS): New macro.
 679         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 680         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 681         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 682         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 683         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 684         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 685         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 686         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 687         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 688         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 689         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 690         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 691         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 692         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 693         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 694         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 695         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 696         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 697         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 698         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 699         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 700         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 701         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 702         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 703         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 704         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 705         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 706         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 707         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 708         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 709         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 710         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 711         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 712         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 713         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 714         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 715         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 716         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 717         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 718         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 719         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 720         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 721         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 722         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 723         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 724         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 725         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 726         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 727         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 728         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 729         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 730         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 731         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 732         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 733         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 734         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 735         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 736         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 737         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 738         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 739         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 740         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 741         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 742         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 743         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 744         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 745         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 746         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 747         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 748         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 749         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 750         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 751         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 752         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 753         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 754         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 755         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 756         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 757         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 758         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 759         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 760         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 761         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 762         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 763         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 764         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 765         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 766         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 767         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 768         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 769         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 770         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 771         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 772         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 773         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 774         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 775         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 776         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 777         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 778         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 779         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 780         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 781         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 782         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 783         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 784         (micromips_opcodes): New declaration.
 785         (bfd_micromips_num_opcodes): Likewise.
 786
 787 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 788
 789         * mips.h (INSN_TRAP): Rename to...
 790         (INSN_NO_DELAY_SLOT): ... this.
 791         (INSN_SYNC): Remove macro.
 792
 793 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 794
 795         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 796         a duplicate of AVR_ISA_SPM.
 797
 798 2011-07-01  Nick Clifton  <nickc@redhat.com>
 799
 800         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 801
 802 2011-06-18  Robin Getz  <robin.getz@analog.com>
 803
 804         * bfin.h (is_macmod_signed): New func
 805
 806 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 807
 808         * bfin.h (is_macmod_pmove): Add missing space before func args.
 809         (is_macmod_hmove): Likewise.
 810
 811 2011-06-13  Walter Lee  <walt@tilera.com>
 812
 813         * tilegx.h: New file.
 814         * tilepro.h: New file.
 815
 816 2011-05-31  Paul Brook  <paul@codesourcery.com>
 817
 818         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 819
 820 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 821
 822         * s390.h: Replace S390_OPERAND_REG_EVEN with
 823         S390_OPERAND_REG_PAIR.
 824
 825 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 826
 827         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 828
 829 2011-04-18  Julian Brown  <julian@codesourcery.com>
 830
 831         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 832
 833 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 834
 835         PR gas/12296
 836         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 837
 838 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 839
 840         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 841         New instruction set flags.
 842         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 843
 844 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 845
 846         * mips.h (M_PREF_AB): New enum value.
 847
 848 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 849
 850         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 851         M_IU): Define.
 852         (is_macmod_pmove, is_macmod_hmove): New functions.
 853
 854 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 855
 856         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 857
 858 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 859
 860         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 861         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 862
 863 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 864
 865         PR gas/11395
 866         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 867         "bb" entries.
 868
 869 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 870
 871         PR gas/11395
 872         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 873
 874 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 875
 876         * mips.h: Update commentary after last commit.
 877
 878 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 879
 880         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 881         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 882         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 883
 884 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 885
 886         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 887
 888 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 889
 890         * mips.h: Fix previous commit.
 891
 892 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 893
 894         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 895         (INSN_LOONGSON_3A): Clear bit 31.
 896
 897 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 898
 899         PR gas/12198
 900         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 901         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 902         (ARM_ARCH_V6M_ONLY): New define.
 903
 904 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 905
 906         * mips.h (INSN_LOONGSON_3A): Defined.
 907         (CPU_LOONGSON_3A): Defined.
 908         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 909
 910 2010-10-09  Matt Rice  <ratmice@gmail.com>
 911
 912         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 913         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 914
 915 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 916
 917         * arm.h (ARM_EXT_VIRT): New define.
 918         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 919         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 920         Extensions.
 921
 922 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 923
 924         * arm.h (ARM_AEXT_ADIV): New define.
 925         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 926
 927 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 928
 929         * arm.h (ARM_EXT_OS): New define.
 930         (ARM_AEXT_V6SM): Likewise.
 931         (ARM_ARCH_V6SM): Likewise.
 932
 933 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 934
 935         * arm.h (ARM_EXT_MP): Add.
 936         (ARM_ARCH_V7A_MP): Likewise.
 937
 938 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 939
 940         * bfin.h: Declare pseudoChr structs/defines.
 941
 942 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 943
 944         * bfin.h: Strip trailing whitespace.
 945
 946 2010-07-29  DJ Delorie  <dj@redhat.com>
 947
 948         * rx.h (RX_Operand_Type): Add TwoReg.
 949         (RX_Opcode_ID): Remove ediv and ediv2.
 950
 951 2010-07-27  DJ Delorie  <dj@redhat.com>
 952
 953         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 954
 955 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 956             Ina Pandit  <ina.pandit@kpitcummins.com>
 957
 958         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 959         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 960         PROCESSOR_V850E2_ALL.
 961         Remove PROCESSOR_V850EA support.
 962         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 963         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 964         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 965         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 966         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 967         V850_OPERAND_PERCENT.
 968         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 969         V850_NOT_R0.
 970         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 971         and V850E_PUSH_POP
 972
 973 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 974
 975         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 976         (MIPS16_INSN_BRANCH): Rename to...
 977         (MIPS16_INSN_COND_BRANCH): ... this.
 978
 979 2010-07-03  Alan Modra  <amodra@gmail.com>
 980
 981         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 982         Renumber other PPC_OPCODE defines.
 983
 984 2010-07-03  Alan Modra  <amodra@gmail.com>
 985
 986         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 987
 988 2010-06-29  Alan Modra  <amodra@gmail.com>
 989
 990         * maxq.h: Delete file.
 991
 992 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 993
 994         * ppc.h (PPC_OPCODE_E500): Define.
 995
 996 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 997
 998         * opcode/mips.h (INSN_MIPS16): Remove.
 999
1000 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
1001
1002         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1003
1004 2010-04-15  Nick Clifton  <nickc@redhat.com>
1005
1006         * alpha.h: Update copyright notice to use GPLv3.
1007         * arc.h: Likewise.
1008         * arm.h: Likewise.
1009         * avr.h: Likewise.
1010         * bfin.h: Likewise.
1011         * cgen.h: Likewise.
1012         * convex.h: Likewise.
1013         * cr16.h: Likewise.
1014         * cris.h: Likewise.
1015         * crx.h: Likewise.
1016         * d10v.h: Likewise.
1017         * d30v.h: Likewise.
1018         * dlx.h: Likewise.
1019         * h8300.h: Likewise.
1020         * hppa.h: Likewise.
1021         * i370.h: Likewise.
1022         * i386.h: Likewise.
1023         * i860.h: Likewise.
1024         * i960.h: Likewise.
1025         * ia64.h: Likewise.
1026         * m68hc11.h: Likewise.
1027         * m68k.h: Likewise.
1028         * m88k.h: Likewise.
1029         * maxq.h: Likewise.
1030         * mips.h: Likewise.
1031         * mmix.h: Likewise.
1032         * mn10200.h: Likewise.
1033         * mn10300.h: Likewise.
1034         * msp430.h: Likewise.
1035         * np1.h: Likewise.
1036         * ns32k.h: Likewise.
1037         * or32.h: Likewise.
1038         * pdp11.h: Likewise.
1039         * pj.h: Likewise.
1040         * pn.h: Likewise.
1041         * ppc.h: Likewise.
1042         * pyr.h: Likewise.
1043         * rx.h: Likewise.
1044         * s390.h: Likewise.
1045         * score-datadep.h: Likewise.
1046         * score-inst.h: Likewise.
1047         * sparc.h: Likewise.
1048         * spu-insns.h: Likewise.
1049         * spu.h: Likewise.
1050         * tic30.h: Likewise.
1051         * tic4x.h: Likewise.
1052         * tic54x.h: Likewise.
1053         * tic80.h: Likewise.
1054         * v850.h: Likewise.
1055         * vax.h: Likewise.
1056
1057 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1058
1059         * tic6x-control-registers.h, tic6x-insn-formats.h,
1060         tic6x-opcode-table.h, tic6x.h: New.
1061
1062 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1063
1064         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1065
1066 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1067
1068         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1069
1070 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         * ia64.h (ia64_find_opcode): Remove argument name.
1073         (ia64_find_next_opcode): Likewise.
1074         (ia64_dis_opcode): Likewise.
1075         (ia64_free_opcode): Likewise.
1076         (ia64_find_dependency): Likewise.
1077
1078 2009-11-22  Doug Evans  <dje@sebabeach.org>
1079
1080         * cgen.h: Include bfd_stdint.h.
1081         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1082
1083 2009-11-18  Paul Brook  <paul@codesourcery.com>
1084
1085         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1086
1087 2009-11-17  Paul Brook  <paul@codesourcery.com>
1088         Daniel Jacobowitz  <dan@codesourcery.com>
1089
1090         * arm.h (ARM_EXT_V6_DSP): Define.
1091         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1092         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1093
1094 2009-11-04  DJ Delorie  <dj@redhat.com>
1095
1096         * rx.h (rx_decode_opcode) (mvtipl): Add.
1097         (mvtcp, mvfcp, opecp): Remove.
1098
1099 2009-11-02  Paul Brook  <paul@codesourcery.com>
1100
1101         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1102         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1103         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1104         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1105         FPU_ARCH_NEON_VFP_V4): Define.
1106
1107 2009-10-23  Doug Evans  <dje@sebabeach.org>
1108
1109         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1110         * cgen.h: Update.  Improve multi-inclusion macro name.
1111
1112 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1113
1114         * ppc.h (PPC_OPCODE_476): Define.
1115
1116 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1117
1118         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1119
1120 2009-09-29  DJ Delorie  <dj@redhat.com>
1121
1122         * rx.h: New file.
1123
1124 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1125
1126         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1127
1128 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1129
1130         * ppc.h (PPC_OPCODE_PPCA2): New.
1131
1132 2009-09-05  Martin Thuresson  <martin@mtme.org>
1133
1134         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1135
1136 2009-08-29  Martin Thuresson  <martin@mtme.org>
1137
1138         * tic30.h (template): Rename type template to
1139         insn_template. Updated code to use new name.
1140         * tic54x.h (template): Rename type template to
1141         insn_template.
1142
1143 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1144
1145         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1146
1147 2009-06-11  Anthony Green  <green@moxielogic.com>
1148
1149         * moxie.h (MOXIE_F3_PCREL): Define.
1150         (moxie_form3_opc_info): Grow.
1151
1152 2009-06-06  Anthony Green  <green@moxielogic.com>
1153
1154         * moxie.h (MOXIE_F1_M): Define.
1155
1156 2009-04-15  Anthony Green  <green@moxielogic.com>
1157
1158         * moxie.h: Created.
1159
1160 2009-04-06  DJ Delorie  <dj@redhat.com>
1161
1162         * h8300.h: Add relaxation attributes to MOVA opcodes.
1163
1164 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1165
1166         * ppc.h (ppc_parse_cpu): Declare.
1167
1168 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1169
1170         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1171         and _IMM11 for mbitclr and mbitset.
1172         * score-datadep.h: Update dependency information.
1173
1174 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1175
1176         * ppc.h (PPC_OPCODE_POWER7): New.
1177
1178 2009-02-06  Doug Evans  <dje@google.com>
1179
1180         * i386.h: Add comment regarding sse* insns and prefixes.
1181
1182 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1183
1184         * mips.h (INSN_XLR): Define.
1185         (INSN_CHIP_MASK): Update.
1186         (CPU_XLR): Define.
1187         (OPCODE_IS_MEMBER): Update.
1188         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1189
1190 2009-01-28  Doug Evans  <dje@google.com>
1191
1192         * opcode/i386.h: Add multiple inclusion protection.
1193         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1194         (EDI_REG_NUM): New macros.
1195         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1196         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1197         (REX_PREFIX_P): New macro.
1198
1199 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1200
1201         * ppc.h (struct powerpc_opcode): New field "deprecated".
1202         (PPC_OPCODE_NOPOWER4): Delete.
1203
1204 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1205
1206         * mips.h: Define CPU_R14000, CPU_R16000.
1207         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1208
1209 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1210
1211         * arm.h (FPU_NEON_FP16): New.
1212         (FPU_ARCH_NEON_FP16): New.
1213
1214 2008-11-06  Chao-ying Fu  <fu@mips.com>
1215
1216         * mips.h: Doucument '1' for 5-bit sync type.
1217
1218 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1221         IA64_RS_CR.
1222
1223 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1224
1225         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1226
1227 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1228
1229         * ppc.h (PPC_OPCODE_405): Define.
1230         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1231
1232 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1233
1234         * ppc.h (ppc_cpu_t): New typedef.
1235         (struct powerpc_opcode <flags>): Use it.
1236         (struct powerpc_operand <insert, extract>): Likewise.
1237         (struct powerpc_macro <flags>): Likewise.
1238
1239 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1240
1241         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1242         Update comment before MIPS16 field descriptors to mention MIPS16.
1243         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1244         BBIT.
1245         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1246         New bit masks and shift counts for cins and exts.
1247
1248         * mips.h: Document new field descriptors +Q.
1249         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1250
1251 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1252
1253         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1254         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1255
1256 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1257
1258         * ppc.h: (PPC_OPCODE_E500MC): New.
1259
1260 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1261
1262         * i386.h (MAX_OPERANDS): Set to 5.
1263         (MAX_MNEM_SIZE): Changed to 20.
1264
1265 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1266
1267         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1268
1269 2008-03-09  Paul Brook  <paul@codesourcery.com>
1270
1271         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1272
1273 2008-03-04  Paul Brook  <paul@codesourcery.com>
1274
1275         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1276         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1277         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1278
1279 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1280             Nick Clifton  <nickc@redhat.com>
1281
1282         PR 3134
1283         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1284         with a 32-bit displacement but without the top bit of the 4th byte
1285         set.
1286
1287 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1288
1289         * cr16.h (cr16_num_optab): Declared.
1290
1291 2008-02-14  Hakan Ardo  <hakan@debian.org>
1292
1293         PR gas/2626
1294         * avr.h (AVR_ISA_2xxe): Define.
1295
1296 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1297
1298         * mips.h: Update copyright.
1299         (INSN_CHIP_MASK): New macro.
1300         (INSN_OCTEON): New macro.
1301         (CPU_OCTEON): New macro.
1302         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1303
1304 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1305
1306         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1307
1308 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1309
1310         * avr.h (AVR_ISA_USB162): Add new opcode set.
1311         (AVR_ISA_AVR3): Likewise.
1312
1313 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1314
1315         * mips.h (INSN_LOONGSON_2E): New.
1316         (INSN_LOONGSON_2F): New.
1317         (CPU_LOONGSON_2E): New.
1318         (CPU_LOONGSON_2F): New.
1319         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1320
1321 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1322
1323         * mips.h (INSN_ISA*): Redefine certain values as an
1324         enumeration.  Update comments.
1325         (mips_isa_table): New.
1326         (ISA_MIPS*): Redefine to match enumeration.
1327         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1328         values.
1329
1330 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1331
1332         * ppc.h (PPC_OPCODE_PPCPS): New.
1333
1334 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1335
1336         * m68k.h: Document j K & E.
1337
1338 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1339
1340         * cr16.h: New file for CR16 target.
1341
1342 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1343
1344         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1345
1346 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1347
1348         * m68k.h (mcfisa_c): New.
1349         (mcfusp, mcf_mask): Adjust.
1350
1351 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1352
1353         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1354         (num_powerpc_operands): Declare.
1355         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1356         (PPC_OPERAND_PLUS1): Define.
1357
1358 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1359
1360         * i386.h (REX_MODE64): Renamed to ...
1361         (REX_W): This.
1362         (REX_EXTX): Renamed to ...
1363         (REX_R): This.
1364         (REX_EXTY): Renamed to ...
1365         (REX_X): This.
1366         (REX_EXTZ): Renamed to ...
1367         (REX_B): This.
1368
1369 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1370
1371         * i386.h: Add entries from config/tc-i386.h and move tables
1372         to opcodes/i386-opc.h.
1373
1374 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1375
1376         * i386.h (FloatDR): Removed.
1377         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1378
1379 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1380
1381         * spu-insns.h: Add soma double-float insns.
1382
1383 2007-02-20  Thiemo Seufer  <ths@mips.com>
1384             Chao-Ying Fu  <fu@mips.com>
1385
1386         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1387         (INSN_DSPR2): Add flag for DSP R2 instructions.
1388         (M_BALIGN): New macro.
1389
1390 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1391
1392         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1393         and Seg3ShortFrom with Shortform.
1394
1395 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1396
1397         PR gas/4027
1398         * i386.h (i386_optab): Put the real "test" before the pseudo
1399         one.
1400
1401 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1402
1403         * m68k.h (m68010up): OR fido_a.
1404
1405 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1406
1407         * m68k.h (fido_a): New.
1408
1409 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1410
1411         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1412         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1413         values.
1414
1415 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1416
1417         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1418
1419 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1420
1421         * score-inst.h (enum score_insn_type): Add Insn_internal.
1422
1423 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1424             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1425             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1426             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1427             Alan Modra  <amodra@bigpond.net.au>
1428
1429         * spu-insns.h: New file.
1430         * spu.h: New file.
1431
1432 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1433
1434         * ppc.h (PPC_OPCODE_CELL): Define.
1435
1436 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1437
1438         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1439         in amdfam10 architecture.
1440
1441 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1442
1443         * i386.h: Replace CpuMNI with CpuSSSE3.
1444
1445 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1446             Joseph Myers  <joseph@codesourcery.com>
1447             Ian Lance Taylor  <ian@wasabisystems.com>
1448             Ben Elliston  <bje@wasabisystems.com>
1449
1450         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1451
1452 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1453
1454         * score-datadep.h: New file.
1455         * score-inst.h: New file.
1456
1457 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1458
1459         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1460         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1461         movdq2q and movq2dq.
1462
1463 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1464            Michael Meissner             <michael.meissner@amd.com>
1465
1466         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1467
1468 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1469
1470         * i386.h (i386_optab): Add "nop" with memory reference.
1471
1472 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1473
1474         * i386.h (i386_optab): Update comment for 64bit NOP.
1475
1476 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1477             Anton Blanchard  <anton@samba.org>
1478
1479         * ppc.h (PPC_OPCODE_POWER6): Define.
1480         Adjust whitespace.
1481
1482 2006-06-05  Thiemo Seufer  <ths@mips.com>
1483
1484         * mips.h: Improve description of MT flags.
1485
1486 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1487
1488         * m68k.h (mcf_mask): Define.
1489
1490 2006-05-05  Thiemo Seufer  <ths@mips.com>
1491             David Ung  <davidu@mips.com>
1492
1493         * mips.h (enum): Add macro M_CACHE_AB.
1494
1495 2006-05-04  Thiemo Seufer  <ths@mips.com>
1496             Nigel Stephens  <nigel@mips.com>
1497             David Ung  <davidu@mips.com>
1498
1499         * mips.h: Add INSN_SMARTMIPS define.
1500
1501 2006-04-30  Thiemo Seufer  <ths@mips.com>
1502             David Ung  <davidu@mips.com>
1503
1504         * mips.h: Defines udi bits and masks.  Add description of
1505         characters which may appear in the args field of udi
1506         instructions.
1507
1508 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1509
1510         * mips.h: Improve comments describing the bitfield instruction
1511         fields.
1512
1513 2006-04-26  Julian Brown  <julian@codesourcery.com>
1514
1515         * arm.h (FPU_VFP_EXT_V3): Define constant.
1516         (FPU_NEON_EXT_V1): Likewise.
1517         (FPU_VFP_HARD): Update.
1518         (FPU_VFP_V3): Define macro.
1519         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1520
1521 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1522
1523         * avr.h (AVR_ISA_PWMx): New.
1524
1525 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1526
1527         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1528         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1529         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1530         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1531         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1532
1533 2006-03-10  Paul Brook  <paul@codesourcery.com>
1534
1535         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1536
1537 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1538
1539         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1540         first.  Correct mask of bb "B" opcode.
1541
1542 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1543
1544         * i386.h (i386_optab): Support Intel Merom New Instructions.
1545
1546 2006-02-24  Paul Brook  <paul@codesourcery.com>
1547
1548         * arm.h: Add V7 feature bits.
1549
1550 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1551
1552         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1553
1554 2006-01-31  Paul Brook  <paul@codesourcery.com>
1555         Richard Earnshaw <rearnsha@arm.com>
1556
1557         * arm.h: Use ARM_CPU_FEATURE.
1558         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1559         (arm_feature_set): Change to a structure.
1560         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1561         ARM_FEATURE): New macros.
1562
1563 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1564
1565         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1566         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1567         (ADD_PC_INCR_OPCODE): Don't define.
1568
1569 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1570
1571         PR gas/1874
1572         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1573
1574 2005-11-14  David Ung  <davidu@mips.com>
1575
1576         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1577         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1578         save/restore encoding of the args field.
1579
1580 2005-10-28  Dave Brolley  <brolley@redhat.com>
1581
1582         Contribute the following changes:
1583         2005-02-16  Dave Brolley  <brolley@redhat.com>
1584
1585         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1586         cgen_isa_mask_* to cgen_bitset_*.
1587         * cgen.h: Likewise.
1588
1589         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1590
1591         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1592         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1593         (CGEN_CPU_TABLE): Make isas a ponter.
1594
1595         2003-09-29  Dave Brolley  <brolley@redhat.com>
1596
1597         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1598         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1599         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1600
1601         2002-12-13  Dave Brolley  <brolley@redhat.com>
1602
1603         * cgen.h (symcat.h): #include it.
1604         (cgen-bitset.h): #include it.
1605         (CGEN_ATTR_VALUE_TYPE): Now a union.
1606         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1607         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1608         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1609         * cgen-bitset.h: New file.
1610
1611 2005-09-30  Catherine Moore  <clm@cm00re.com>
1612
1613         * bfin.h: New file.
1614
1615 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1616
1617         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1618         indirect operands.
1619
1620 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1621
1622         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1623         Add FLAG_STRICT to pa10 ftest opcode.
1624
1625 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1626
1627         * hppa.h (pa_opcodes): Remove lha entries.
1628
1629 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1630
1631         * hppa.h (FLAG_STRICT): Revise comment.
1632         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1633         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1634         entries for "fdc".
1635
1636 2005-09-30  Catherine Moore  <clm@cm00re.com>
1637
1638         * bfin.h: New file.
1639
1640 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1641
1642         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1643
1644 2005-09-06  Chao-ying Fu  <fu@mips.com>
1645
1646         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1647         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1648         define.
1649         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1650         (INSN_ASE_MASK): Update to include INSN_MT.
1651         (INSN_MT): New define for MT ASE.
1652
1653 2005-08-25  Chao-ying Fu  <fu@mips.com>
1654
1655         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1656         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1657         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1658         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1659         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1660         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1661         instructions.
1662         (INSN_DSP): New define for DSP ASE.
1663
1664 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1665
1666         * a29k.h: Delete.
1667
1668 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1669
1670         * ppc.h (PPC_OPCODE_E300): Define.
1671
1672 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1673
1674         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1675
1676 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1677
1678         PR gas/336
1679         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1680         and pitlb.
1681
1682 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1683
1684         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1685         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1686         Add movq-s as 64-bit variants of movd-s.
1687
1688 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1689
1690         * hppa.h: Fix punctuation in comment.
1691
1692         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1693         implicit space-register addressing.  Set space-register bits on opcodes
1694         using implicit space-register addressing.  Add various missing pa20
1695         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1696         space-register addressing.  Use "fE" instead of "fe" in various
1697         fstw opcodes.
1698
1699 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1700
1701         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1702
1703 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1704
1705         * i386.h (i386_optab): Support Intel VMX Instructions.
1706
1707 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1708
1709         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1710
1711 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1712
1713         * i386.h (i386_optab): Add new insns.
1714
1715 2005-07-01  Nick Clifton  <nickc@redhat.com>
1716
1717         * sparc.h: Add typedefs to structure declarations.
1718
1719 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1720
1721         PR 1013
1722         * i386.h (i386_optab): Update comments for 64bit addressing on
1723         mov. Allow 64bit addressing for mov and movq.
1724
1725 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1726
1727         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1728         respectively, in various floating-point load and store patterns.
1729
1730 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1731
1732         * hppa.h (FLAG_STRICT): Correct comment.
1733         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1734         PA 2.0 mneumonics when equivalent.  Entries with cache control
1735         completers now require PA 1.1.  Adjust whitespace.
1736
1737 2005-05-19  Anton Blanchard  <anton@samba.org>
1738
1739         * ppc.h (PPC_OPCODE_POWER5): Define.
1740
1741 2005-05-10  Nick Clifton  <nickc@redhat.com>
1742
1743         * Update the address and phone number of the FSF organization in
1744         the GPL notices in the following files:
1745         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1746         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1747         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1748         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1749         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1750         tic54x.h, tic80.h, v850.h, vax.h
1751
1752 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1753
1754         * i386.h (i386_optab): Add ht and hnt.
1755
1756 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1757
1758         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1759         Add xcrypt-ctr.  Provide aliases without hyphens.
1760
1761 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1762
1763         Moved from ../ChangeLog
1764
1765         2005-04-12  Paul Brook  <paul@codesourcery.com>
1766         * m88k.h: Rename psr macros to avoid conflicts.
1767
1768         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1769         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1770         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1771         and ARM_ARCH_V6ZKT2.
1772
1773         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1774         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1775         Remove redundant instruction types.
1776         (struct argument): X_op - new field.
1777         (struct cst4_entry): Remove.
1778         (no_op_insn): Declare.
1779
1780         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1781         * crx.h (enum argtype): Rename types, remove unused types.
1782
1783         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1784         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1785         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1786         (enum operand_type): Rearrange operands, edit comments.
1787         replace us<N> with ui<N> for unsigned immediate.
1788         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1789         displacements (respectively).
1790         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1791         (instruction type): Add NO_TYPE_INS.
1792         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1793         (operand_entry): New field - 'flags'.
1794         (operand flags): New.
1795
1796         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1797         * crx.h (operand_type): Remove redundant types i3, i4,
1798         i5, i8, i12.
1799         Add new unsigned immediate types us3, us4, us5, us16.
1800
1801 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1802
1803         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1804         adjust them accordingly.
1805
1806 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1807
1808         * i386.h (i386_optab): Add rdtscp.
1809
1810 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1811
1812         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1813         between memory and segment register. Allow movq for moving between
1814         general-purpose register and segment register.
1815
1816 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1817
1818         PR gas/707
1819         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1820         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1821         fnstsw.
1822
1823 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1824
1825         * m68k.h (m68008, m68ec030, m68882): Remove.
1826         (m68k_mask): New.
1827         (cpu_m68k, cpu_cf): New.
1828         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1829         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1830
1831 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1832
1833         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1834         * cgen.h (enum cgen_parse_operand_type): Add
1835         CGEN_PARSE_OPERAND_SYMBOLIC.
1836
1837 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1838
1839         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1840         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1841         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1842
1843 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1844
1845         * mips.h (struct mips_opcode): Add new pinfo2 member.
1846         (INSN_ALIAS): New define for opcode table entries that are
1847         specific instances of another entry, such as 'move' for an 'or'
1848         with a zero operand.
1849         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1850         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1851
1852 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1853
1854         * mips.h (CPU_RM9000): Define.
1855         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1856
1857 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1858
1859         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1860         to/from test registers are illegal in 64-bit mode. Add missing
1861         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1862         (previously one had to explicitly encode a rex64 prefix). Re-enable
1863         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1864         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1865
1866 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1867
1868         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1869         available only with SSE2. Change the MMX additions introduced by SSE
1870         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1871         instructions by their now designated identifier (since combining i686
1872         and 3DNow! does not really imply 3DNow!A).
1873
1874 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1875
1876         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1877         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1878
1879 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1880             Vineet Sharma      <vineets@noida.hcltech.com>
1881
1882         * maxq.h: New file: Disassembly information for the maxq port.
1883
1884 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1885
1886         * i386.h (i386_optab): Put back "movzb".
1887
1888 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1889
1890         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1891         comments.  Remove member cris_ver_sim.  Add members
1892         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1893         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1894         (struct cris_support_reg, struct cris_cond15): New types.
1895         (cris_conds15): Declare.
1896         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1897         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1898         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1899         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1900         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1901         SIZE_FIELD_UNSIGNED.
1902
1903 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1904
1905         * i386.h (sldx_Suf): Remove.
1906         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1907         (q_FP): Define, implying no REX64.
1908         (x_FP, sl_FP): Imply FloatMF.
1909         (i386_optab): Split reg and mem forms of moving from segment registers
1910         so that the memory forms can ignore the 16-/32-bit operand size
1911         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1912         all non-floating-point instructions. Unite 32- and 64-bit forms of
1913         movsx, movzx, and movd. Adjust floating point operations for the above
1914         changes to the *FP macros. Add DefaultSize to floating point control
1915         insns operating on larger memory ranges. Remove left over comments
1916         hinting at certain insns being Intel-syntax ones where the ones
1917         actually meant are already gone.
1918
1919 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1920
1921         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1922         instruction type.
1923
1924 2004-09-30  Paul Brook  <paul@codesourcery.com>
1925
1926         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1927         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1928
1929 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1930
1931         * avr.h: Add support for
1932         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1933
1934 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1935
1936         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1937
1938 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1939
1940         * msp430.h (msp430_opc): Add new instructions.
1941         (msp430_rcodes): Declare new instructions.
1942         (msp430_hcodes): Likewise..
1943
1944 2004-08-13  Nick Clifton  <nickc@redhat.com>
1945
1946         PR/301
1947         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1948         processors.
1949
1950 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1951
1952         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1953
1954 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1955
1956         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1957
1958 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1959
1960         * i386.h: Adjust instruction descriptions to better match the
1961         specification.
1962
1963 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1964
1965         * arm.h: Remove all old content.  Replace with architecture defines
1966         from gas/config/tc-arm.c.
1967
1968 2004-07-09  Andreas Schwab  <schwab@suse.de>
1969
1970         * m68k.h: Fix comment.
1971
1972 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1973
1974         * crx.h: New file.
1975
1976 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1977
1978         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1979
1980 2004-05-24  Peter Barada  <peter@the-baradas.com>
1981
1982         * m68k.h: Add 'size' to m68k_opcode.
1983
1984 2004-05-05  Peter Barada  <peter@the-baradas.com>
1985
1986         * m68k.h: Switch from ColdFire chip name to core variant.
1987
1988 2004-04-22  Peter Barada  <peter@the-baradas.com>
1989
1990         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1991         descriptions for new EMAC cases.
1992         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1993         handle Motorola MAC syntax.
1994         Allow disassembly of ColdFire V4e object files.
1995
1996 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1997
1998         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1999
2000 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
2001
2002         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2003
2004 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2005
2006         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2007
2008 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2009
2010         * i386.h (i386_optab): Added xstore/xcrypt insns.
2011
2012 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2013
2014         * h8300.h (32bit ldc/stc): Add relaxing support.
2015
2016 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
2017
2018         * h8300.h (BITOP): Pass MEMRELAX flag.
2019
2020 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2021
2022         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2023         except for the H8S.
2024
2025 For older changes see ChangeLog-9103
2026 \f
2027 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2028
2029 Copying and distribution of this file, with or without modification,
2030 are permitted in any medium without royalty provided the copyright
2031 notice and this notice are preserved.
2032
2033 Local Variables:
2034 mode: change-log
2035 left-margin: 8
2036 fill-column: 74
2037 version-control: never
2038 End: