include/opcode/ChangeLog

   1 2011-07-01  Nick Clifton  <nickc@redhat.com>
   2
   3         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
   4
   5 2011-06-18  Robin Getz  <robin.getz@analog.com>
   6
   7         * bfin.h (is_macmod_signed): New func
   8
   9 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
  10
  11         * bfin.h (is_macmod_pmove): Add missing space before func args.
  12         (is_macmod_hmove): Likewise.
  13
  14 2011-06-13  Walter Lee  <walt@tilera.com>
  15
  16         * tilegx.h: New file.
  17         * tilepro.h: New file.
  18
  19 2011-05-31  Paul Brook  <paul@codesourcery.com>
  20
  21         * arm.h (ARM_ARCH_V7R_IDIV): Define.
  22
  23 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  24
  25         * s390.h: Replace S390_OPERAND_REG_EVEN with
  26         S390_OPERAND_REG_PAIR.
  27
  28 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  29
  30         * s390.h: Add S390_OPCODE_REG_EVEN flag.
  31
  32 2011-04-18  Julian Brown  <julian@codesourcery.com>
  33
  34         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
  35
  36 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
  37
  38         PR gas/12296
  39         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
  40
  41 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
  42
  43         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
  44         New instruction set flags.
  45         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
  46
  47 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
  48
  49         * mips.h (M_PREF_AB): New enum value.
  50
  51 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
  52
  53         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
  54         M_IU): Define.
  55         (is_macmod_pmove, is_macmod_hmove): New functions.
  56
  57 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
  58
  59         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
  60
  61 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
  62
  63         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
  64         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
  65
  66 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  67
  68         PR gas/11395
  69         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
  70         "bb" entries.
  71
  72 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  73
  74         PR gas/11395
  75         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
  76
  77 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
  78
  79         * mips.h: Update commentary after last commit.
  80
  81 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
  82
  83         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
  84         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
  85         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
  86
  87 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  88
  89         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
  90
  91 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
  92
  93         * mips.h: Fix previous commit.
  94
  95 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
  96
  97         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
  98         (INSN_LOONGSON_3A): Clear bit 31.
  99
 100 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 101
 102         PR gas/12198
 103         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 104         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 105         (ARM_ARCH_V6M_ONLY): New define.
 106
 107 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 108
 109         * mips.h (INSN_LOONGSON_3A): Defined.
 110         (CPU_LOONGSON_3A): Defined.
 111         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 112
 113 2010-10-09  Matt Rice  <ratmice@gmail.com>
 114
 115         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 116         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 117
 118 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 119
 120         * arm.h (ARM_EXT_VIRT): New define.
 121         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 122         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 123         Extensions.
 124
 125 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 126
 127         * arm.h (ARM_AEXT_ADIV): New define.
 128         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 129
 130 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 131
 132         * arm.h (ARM_EXT_OS): New define.
 133         (ARM_AEXT_V6SM): Likewise.
 134         (ARM_ARCH_V6SM): Likewise.
 135
 136 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 137
 138         * arm.h (ARM_EXT_MP): Add.
 139         (ARM_ARCH_V7A_MP): Likewise.
 140
 141 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 142
 143         * bfin.h: Declare pseudoChr structs/defines.
 144
 145 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 146
 147         * bfin.h: Strip trailing whitespace.
 148
 149 2010-07-29  DJ Delorie  <dj@redhat.com>
 150
 151         * rx.h (RX_Operand_Type): Add TwoReg.
 152         (RX_Opcode_ID): Remove ediv and ediv2.
 153
 154 2010-07-27  DJ Delorie  <dj@redhat.com>
 155
 156         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 157
 158 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 159             Ina Pandit  <ina.pandit@kpitcummins.com>
 160
 161         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 162         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 163         PROCESSOR_V850E2_ALL.
 164         Remove PROCESSOR_V850EA support.
 165         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 166         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 167         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 168         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 169         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 170         V850_OPERAND_PERCENT.
 171         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 172         V850_NOT_R0.
 173         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 174         and V850E_PUSH_POP
 175
 176 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 177
 178         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 179         (MIPS16_INSN_BRANCH): Rename to...
 180         (MIPS16_INSN_COND_BRANCH): ... this.
 181
 182 2010-07-03  Alan Modra  <amodra@gmail.com>
 183
 184         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 185         Renumber other PPC_OPCODE defines.
 186
 187 2010-07-03  Alan Modra  <amodra@gmail.com>
 188
 189         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 190
 191 2010-06-29  Alan Modra  <amodra@gmail.com>
 192
 193         * maxq.h: Delete file.
 194
 195 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 196
 197         * ppc.h (PPC_OPCODE_E500): Define.
 198
 199 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 200
 201         * opcode/mips.h (INSN_MIPS16): Remove.
 202
 203 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 204
 205         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 206
 207 2010-04-15  Nick Clifton  <nickc@redhat.com>
 208
 209         * alpha.h: Update copyright notice to use GPLv3.
 210         * arc.h: Likewise.
 211         * arm.h: Likewise.
 212         * avr.h: Likewise.
 213         * bfin.h: Likewise.
 214         * cgen.h: Likewise.
 215         * convex.h: Likewise.
 216         * cr16.h: Likewise.
 217         * cris.h: Likewise.
 218         * crx.h: Likewise.
 219         * d10v.h: Likewise.
 220         * d30v.h: Likewise.
 221         * dlx.h: Likewise.
 222         * h8300.h: Likewise.
 223         * hppa.h: Likewise.
 224         * i370.h: Likewise.
 225         * i386.h: Likewise.
 226         * i860.h: Likewise.
 227         * i960.h: Likewise.
 228         * ia64.h: Likewise.
 229         * m68hc11.h: Likewise.
 230         * m68k.h: Likewise.
 231         * m88k.h: Likewise.
 232         * maxq.h: Likewise.
 233         * mips.h: Likewise.
 234         * mmix.h: Likewise.
 235         * mn10200.h: Likewise.
 236         * mn10300.h: Likewise.
 237         * msp430.h: Likewise.
 238         * np1.h: Likewise.
 239         * ns32k.h: Likewise.
 240         * or32.h: Likewise.
 241         * pdp11.h: Likewise.
 242         * pj.h: Likewise.
 243         * pn.h: Likewise.
 244         * ppc.h: Likewise.
 245         * pyr.h: Likewise.
 246         * rx.h: Likewise.
 247         * s390.h: Likewise.
 248         * score-datadep.h: Likewise.
 249         * score-inst.h: Likewise.
 250         * sparc.h: Likewise.
 251         * spu-insns.h: Likewise.
 252         * spu.h: Likewise.
 253         * tic30.h: Likewise.
 254         * tic4x.h: Likewise.
 255         * tic54x.h: Likewise.
 256         * tic80.h: Likewise.
 257         * v850.h: Likewise.
 258         * vax.h: Likewise.
 259
 260 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 261
 262         * tic6x-control-registers.h, tic6x-insn-formats.h,
 263         tic6x-opcode-table.h, tic6x.h: New.
 264
 265 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 266
 267         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 268
 269 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 270
 271         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 272
 273 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * ia64.h (ia64_find_opcode): Remove argument name.
 276         (ia64_find_next_opcode): Likewise.
 277         (ia64_dis_opcode): Likewise.
 278         (ia64_free_opcode): Likewise.
 279         (ia64_find_dependency): Likewise.
 280
 281 2009-11-22  Doug Evans  <dje@sebabeach.org>
 282
 283         * cgen.h: Include bfd_stdint.h.
 284         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 285
 286 2009-11-18  Paul Brook  <paul@codesourcery.com>
 287
 288         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 289
 290 2009-11-17  Paul Brook  <paul@codesourcery.com>
 291         Daniel Jacobowitz  <dan@codesourcery.com>
 292
 293         * arm.h (ARM_EXT_V6_DSP): Define.
 294         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 295         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 296
 297 2009-11-04  DJ Delorie  <dj@redhat.com>
 298
 299         * rx.h (rx_decode_opcode) (mvtipl): Add.
 300         (mvtcp, mvfcp, opecp): Remove.
 301
 302 2009-11-02  Paul Brook  <paul@codesourcery.com>
 303
 304         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 305         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 306         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 307         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 308         FPU_ARCH_NEON_VFP_V4): Define.
 309
 310 2009-10-23  Doug Evans  <dje@sebabeach.org>
 311
 312         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 313         * cgen.h: Update.  Improve multi-inclusion macro name.
 314
 315 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 316
 317         * ppc.h (PPC_OPCODE_476): Define.
 318
 319 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 320
 321         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 322
 323 2009-09-29  DJ Delorie  <dj@redhat.com>
 324
 325         * rx.h: New file.
 326
 327 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 328
 329         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 330
 331 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 332
 333         * ppc.h (PPC_OPCODE_PPCA2): New.
 334
 335 2009-09-05  Martin Thuresson  <martin@mtme.org>
 336
 337         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 338
 339 2009-08-29  Martin Thuresson  <martin@mtme.org>
 340
 341         * tic30.h (template): Rename type template to
 342         insn_template. Updated code to use new name.
 343         * tic54x.h (template): Rename type template to
 344         insn_template.
 345
 346 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 347
 348         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 349
 350 2009-06-11  Anthony Green  <green@moxielogic.com>
 351
 352         * moxie.h (MOXIE_F3_PCREL): Define.
 353         (moxie_form3_opc_info): Grow.
 354
 355 2009-06-06  Anthony Green  <green@moxielogic.com>
 356
 357         * moxie.h (MOXIE_F1_M): Define.
 358
 359 2009-04-15  Anthony Green  <green@moxielogic.com>
 360
 361         * moxie.h: Created.
 362
 363 2009-04-06  DJ Delorie  <dj@redhat.com>
 364
 365         * h8300.h: Add relaxation attributes to MOVA opcodes.
 366
 367 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 368
 369         * ppc.h (ppc_parse_cpu): Declare.
 370
 371 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 372
 373         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 374         and _IMM11 for mbitclr and mbitset.
 375         * score-datadep.h: Update dependency information.
 376
 377 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 378
 379         * ppc.h (PPC_OPCODE_POWER7): New.
 380
 381 2009-02-06  Doug Evans  <dje@google.com>
 382
 383         * i386.h: Add comment regarding sse* insns and prefixes.
 384
 385 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 386
 387         * mips.h (INSN_XLR): Define.
 388         (INSN_CHIP_MASK): Update.
 389         (CPU_XLR): Define.
 390         (OPCODE_IS_MEMBER): Update.
 391         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 392
 393 2009-01-28  Doug Evans  <dje@google.com>
 394
 395         * opcode/i386.h: Add multiple inclusion protection.
 396         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 397         (EDI_REG_NUM): New macros.
 398         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 399         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 400         (REX_PREFIX_P): New macro.
 401
 402 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 403
 404         * ppc.h (struct powerpc_opcode): New field "deprecated".
 405         (PPC_OPCODE_NOPOWER4): Delete.
 406
 407 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 408
 409         * mips.h: Define CPU_R14000, CPU_R16000.
 410         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 411
 412 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 413
 414         * arm.h (FPU_NEON_FP16): New.
 415         (FPU_ARCH_NEON_FP16): New.
 416
 417 2008-11-06  Chao-ying Fu  <fu@mips.com>
 418
 419         * mips.h: Doucument '1' for 5-bit sync type.
 420
 421 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 422
 423         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 424         IA64_RS_CR.
 425
 426 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 427
 428         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 429
 430 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 431
 432         * ppc.h (PPC_OPCODE_405): Define.
 433         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 434
 435 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 436
 437         * ppc.h (ppc_cpu_t): New typedef.
 438         (struct powerpc_opcode <flags>): Use it.
 439         (struct powerpc_operand <insert, extract>): Likewise.
 440         (struct powerpc_macro <flags>): Likewise.
 441
 442 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 443
 444         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 445         Update comment before MIPS16 field descriptors to mention MIPS16.
 446         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 447         BBIT.
 448         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 449         New bit masks and shift counts for cins and exts.
 450
 451         * mips.h: Document new field descriptors +Q.
 452         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 453
 454 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 455
 456         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 457         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 458
 459 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 460
 461         * ppc.h: (PPC_OPCODE_E500MC): New.
 462
 463 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         * i386.h (MAX_OPERANDS): Set to 5.
 466         (MAX_MNEM_SIZE): Changed to 20.
 467
 468 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 469
 470         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 471
 472 2008-03-09  Paul Brook  <paul@codesourcery.com>
 473
 474         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 475
 476 2008-03-04  Paul Brook  <paul@codesourcery.com>
 477
 478         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 479         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 480         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 481
 482 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 483             Nick Clifton  <nickc@redhat.com>
 484
 485         PR 3134
 486         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 487         with a 32-bit displacement but without the top bit of the 4th byte
 488         set.
 489
 490 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 491
 492         * cr16.h (cr16_num_optab): Declared.
 493
 494 2008-02-14  Hakan Ardo  <hakan@debian.org>
 495
 496         PR gas/2626
 497         * avr.h (AVR_ISA_2xxe): Define.
 498
 499 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 500
 501         * mips.h: Update copyright.
 502         (INSN_CHIP_MASK): New macro.
 503         (INSN_OCTEON): New macro.
 504         (CPU_OCTEON): New macro.
 505         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 506
 507 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 508
 509         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 510
 511 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 512
 513         * avr.h (AVR_ISA_USB162): Add new opcode set.
 514         (AVR_ISA_AVR3): Likewise.
 515
 516 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 517
 518         * mips.h (INSN_LOONGSON_2E): New.
 519         (INSN_LOONGSON_2F): New.
 520         (CPU_LOONGSON_2E): New.
 521         (CPU_LOONGSON_2F): New.
 522         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 523
 524 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 525
 526         * mips.h (INSN_ISA*): Redefine certain values as an
 527         enumeration.  Update comments.
 528         (mips_isa_table): New.
 529         (ISA_MIPS*): Redefine to match enumeration.
 530         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 531         values.
 532
 533 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 534
 535         * ppc.h (PPC_OPCODE_PPCPS): New.
 536
 537 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 538
 539         * m68k.h: Document j K & E.
 540
 541 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 542
 543         * cr16.h: New file for CR16 target.
 544
 545 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 546
 547         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 548
 549 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 550
 551         * m68k.h (mcfisa_c): New.
 552         (mcfusp, mcf_mask): Adjust.
 553
 554 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 555
 556         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 557         (num_powerpc_operands): Declare.
 558         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 559         (PPC_OPERAND_PLUS1): Define.
 560
 561 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386.h (REX_MODE64): Renamed to ...
 564         (REX_W): This.
 565         (REX_EXTX): Renamed to ...
 566         (REX_R): This.
 567         (REX_EXTY): Renamed to ...
 568         (REX_X): This.
 569         (REX_EXTZ): Renamed to ...
 570         (REX_B): This.
 571
 572 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         * i386.h: Add entries from config/tc-i386.h and move tables
 575         to opcodes/i386-opc.h.
 576
 577 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * i386.h (FloatDR): Removed.
 580         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 581
 582 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 583
 584         * spu-insns.h: Add soma double-float insns.
 585
 586 2007-02-20  Thiemo Seufer  <ths@mips.com>
 587             Chao-Ying Fu  <fu@mips.com>
 588
 589         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 590         (INSN_DSPR2): Add flag for DSP R2 instructions.
 591         (M_BALIGN): New macro.
 592
 593 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 594
 595         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 596         and Seg3ShortFrom with Shortform.
 597
 598 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         PR gas/4027
 601         * i386.h (i386_optab): Put the real "test" before the pseudo
 602         one.
 603
 604 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 605
 606         * m68k.h (m68010up): OR fido_a.
 607
 608 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 609
 610         * m68k.h (fido_a): New.
 611
 612 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 613
 614         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 615         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 616         values.
 617
 618 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 621
 622 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 623
 624         * score-inst.h (enum score_insn_type): Add Insn_internal.
 625
 626 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 627             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 628             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 629             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 630             Alan Modra  <amodra@bigpond.net.au>
 631
 632         * spu-insns.h: New file.
 633         * spu.h: New file.
 634
 635 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 636
 637         * ppc.h (PPC_OPCODE_CELL): Define.
 638
 639 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 640
 641         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 642         in amdfam10 architecture.
 643
 644 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 645
 646         * i386.h: Replace CpuMNI with CpuSSSE3.
 647
 648 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 649             Joseph Myers  <joseph@codesourcery.com>
 650             Ian Lance Taylor  <ian@wasabisystems.com>
 651             Ben Elliston  <bje@wasabisystems.com>
 652
 653         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 654
 655 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 656
 657         * score-datadep.h: New file.
 658         * score-inst.h: New file.
 659
 660 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 661
 662         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 663         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 664         movdq2q and movq2dq.
 665
 666 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 667            Michael Meissner             <michael.meissner@amd.com>
 668
 669         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 670
 671 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         * i386.h (i386_optab): Add "nop" with memory reference.
 674
 675 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         * i386.h (i386_optab): Update comment for 64bit NOP.
 678
 679 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 680             Anton Blanchard  <anton@samba.org>
 681
 682         * ppc.h (PPC_OPCODE_POWER6): Define.
 683         Adjust whitespace.
 684
 685 2006-06-05  Thiemo Seufer  <ths@mips.com>
 686
 687         * mips.h: Improve description of MT flags.
 688
 689 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 690
 691         * m68k.h (mcf_mask): Define.
 692
 693 2006-05-05  Thiemo Seufer  <ths@mips.com>
 694             David Ung  <davidu@mips.com>
 695
 696         * mips.h (enum): Add macro M_CACHE_AB.
 697
 698 2006-05-04  Thiemo Seufer  <ths@mips.com>
 699             Nigel Stephens  <nigel@mips.com>
 700             David Ung  <davidu@mips.com>
 701
 702         * mips.h: Add INSN_SMARTMIPS define.
 703
 704 2006-04-30  Thiemo Seufer  <ths@mips.com>
 705             David Ung  <davidu@mips.com>
 706
 707         * mips.h: Defines udi bits and masks.  Add description of
 708         characters which may appear in the args field of udi
 709         instructions.
 710
 711 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 712
 713         * mips.h: Improve comments describing the bitfield instruction
 714         fields.
 715
 716 2006-04-26  Julian Brown  <julian@codesourcery.com>
 717
 718         * arm.h (FPU_VFP_EXT_V3): Define constant.
 719         (FPU_NEON_EXT_V1): Likewise.
 720         (FPU_VFP_HARD): Update.
 721         (FPU_VFP_V3): Define macro.
 722         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 723
 724 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 725
 726         * avr.h (AVR_ISA_PWMx): New.
 727
 728 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 729
 730         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 731         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 732         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 733         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 734         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 735
 736 2006-03-10  Paul Brook  <paul@codesourcery.com>
 737
 738         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 739
 740 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 741
 742         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 743         first.  Correct mask of bb "B" opcode.
 744
 745 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 746
 747         * i386.h (i386_optab): Support Intel Merom New Instructions.
 748
 749 2006-02-24  Paul Brook  <paul@codesourcery.com>
 750
 751         * arm.h: Add V7 feature bits.
 752
 753 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 756
 757 2006-01-31  Paul Brook  <paul@codesourcery.com>
 758         Richard Earnshaw <rearnsha@arm.com>
 759
 760         * arm.h: Use ARM_CPU_FEATURE.
 761         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 762         (arm_feature_set): Change to a structure.
 763         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 764         ARM_FEATURE): New macros.
 765
 766 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 767
 768         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 769         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 770         (ADD_PC_INCR_OPCODE): Don't define.
 771
 772 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 773
 774         PR gas/1874
 775         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 776
 777 2005-11-14  David Ung  <davidu@mips.com>
 778
 779         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 780         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 781         save/restore encoding of the args field.
 782
 783 2005-10-28  Dave Brolley  <brolley@redhat.com>
 784
 785         Contribute the following changes:
 786         2005-02-16  Dave Brolley  <brolley@redhat.com>
 787
 788         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 789         cgen_isa_mask_* to cgen_bitset_*.
 790         * cgen.h: Likewise.
 791
 792         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 793
 794         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 795         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 796         (CGEN_CPU_TABLE): Make isas a ponter.
 797
 798         2003-09-29  Dave Brolley  <brolley@redhat.com>
 799
 800         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 801         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 802         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 803
 804         2002-12-13  Dave Brolley  <brolley@redhat.com>
 805
 806         * cgen.h (symcat.h): #include it.
 807         (cgen-bitset.h): #include it.
 808         (CGEN_ATTR_VALUE_TYPE): Now a union.
 809         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 810         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 811         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 812         * cgen-bitset.h: New file.
 813
 814 2005-09-30  Catherine Moore  <clm@cm00re.com>
 815
 816         * bfin.h: New file.
 817
 818 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 819
 820         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 821         indirect operands.
 822
 823 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 824
 825         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 826         Add FLAG_STRICT to pa10 ftest opcode.
 827
 828 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 829
 830         * hppa.h (pa_opcodes): Remove lha entries.
 831
 832 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 833
 834         * hppa.h (FLAG_STRICT): Revise comment.
 835         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 836         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 837         entries for "fdc".
 838
 839 2005-09-30  Catherine Moore  <clm@cm00re.com>
 840
 841         * bfin.h: New file.
 842
 843 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 844
 845         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 846
 847 2005-09-06  Chao-ying Fu  <fu@mips.com>
 848
 849         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 850         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 851         define.
 852         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 853         (INSN_ASE_MASK): Update to include INSN_MT.
 854         (INSN_MT): New define for MT ASE.
 855
 856 2005-08-25  Chao-ying Fu  <fu@mips.com>
 857
 858         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 859         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 860         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 861         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 862         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 863         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 864         instructions.
 865         (INSN_DSP): New define for DSP ASE.
 866
 867 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 868
 869         * a29k.h: Delete.
 870
 871 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 872
 873         * ppc.h (PPC_OPCODE_E300): Define.
 874
 875 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 876
 877         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 878
 879 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 880
 881         PR gas/336
 882         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 883         and pitlb.
 884
 885 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 886
 887         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 888         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 889         Add movq-s as 64-bit variants of movd-s.
 890
 891 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 892
 893         * hppa.h: Fix punctuation in comment.
 894
 895         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 896         implicit space-register addressing.  Set space-register bits on opcodes
 897         using implicit space-register addressing.  Add various missing pa20
 898         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 899         space-register addressing.  Use "fE" instead of "fe" in various
 900         fstw opcodes.
 901
 902 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 903
 904         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 905
 906 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 907
 908         * i386.h (i386_optab): Support Intel VMX Instructions.
 909
 910 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 911
 912         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 913
 914 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 915
 916         * i386.h (i386_optab): Add new insns.
 917
 918 2005-07-01  Nick Clifton  <nickc@redhat.com>
 919
 920         * sparc.h: Add typedefs to structure declarations.
 921
 922 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         PR 1013
 925         * i386.h (i386_optab): Update comments for 64bit addressing on
 926         mov. Allow 64bit addressing for mov and movq.
 927
 928 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 929
 930         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 931         respectively, in various floating-point load and store patterns.
 932
 933 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 934
 935         * hppa.h (FLAG_STRICT): Correct comment.
 936         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 937         PA 2.0 mneumonics when equivalent.  Entries with cache control
 938         completers now require PA 1.1.  Adjust whitespace.
 939
 940 2005-05-19  Anton Blanchard  <anton@samba.org>
 941
 942         * ppc.h (PPC_OPCODE_POWER5): Define.
 943
 944 2005-05-10  Nick Clifton  <nickc@redhat.com>
 945
 946         * Update the address and phone number of the FSF organization in
 947         the GPL notices in the following files:
 948         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 949         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 950         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 951         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 952         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 953         tic54x.h, tic80.h, v850.h, vax.h
 954
 955 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 956
 957         * i386.h (i386_optab): Add ht and hnt.
 958
 959 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 960
 961         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 962         Add xcrypt-ctr.  Provide aliases without hyphens.
 963
 964 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         Moved from ../ChangeLog
 967
 968         2005-04-12  Paul Brook  <paul@codesourcery.com>
 969         * m88k.h: Rename psr macros to avoid conflicts.
 970
 971         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 972         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 973         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 974         and ARM_ARCH_V6ZKT2.
 975
 976         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 977         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 978         Remove redundant instruction types.
 979         (struct argument): X_op - new field.
 980         (struct cst4_entry): Remove.
 981         (no_op_insn): Declare.
 982
 983         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 984         * crx.h (enum argtype): Rename types, remove unused types.
 985
 986         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 987         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 988         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 989         (enum operand_type): Rearrange operands, edit comments.
 990         replace us<N> with ui<N> for unsigned immediate.
 991         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 992         displacements (respectively).
 993         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 994         (instruction type): Add NO_TYPE_INS.
 995         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 996         (operand_entry): New field - 'flags'.
 997         (operand flags): New.
 998
 999         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1000         * crx.h (operand_type): Remove redundant types i3, i4,
1001         i5, i8, i12.
1002         Add new unsigned immediate types us3, us4, us5, us16.
1003
1004 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1005
1006         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1007         adjust them accordingly.
1008
1009 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1010
1011         * i386.h (i386_optab): Add rdtscp.
1012
1013 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1014
1015         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1016         between memory and segment register. Allow movq for moving between
1017         general-purpose register and segment register.
1018
1019 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1020
1021         PR gas/707
1022         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1023         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1024         fnstsw.
1025
1026 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1027
1028         * m68k.h (m68008, m68ec030, m68882): Remove.
1029         (m68k_mask): New.
1030         (cpu_m68k, cpu_cf): New.
1031         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1032         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1033
1034 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1035
1036         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1037         * cgen.h (enum cgen_parse_operand_type): Add
1038         CGEN_PARSE_OPERAND_SYMBOLIC.
1039
1040 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1041
1042         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1043         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1044         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1045
1046 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1047
1048         * mips.h (struct mips_opcode): Add new pinfo2 member.
1049         (INSN_ALIAS): New define for opcode table entries that are
1050         specific instances of another entry, such as 'move' for an 'or'
1051         with a zero operand.
1052         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1053         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1054
1055 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1056
1057         * mips.h (CPU_RM9000): Define.
1058         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1059
1060 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1061
1062         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1063         to/from test registers are illegal in 64-bit mode. Add missing
1064         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1065         (previously one had to explicitly encode a rex64 prefix). Re-enable
1066         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1067         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1068
1069 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1070
1071         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1072         available only with SSE2. Change the MMX additions introduced by SSE
1073         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1074         instructions by their now designated identifier (since combining i686
1075         and 3DNow! does not really imply 3DNow!A).
1076
1077 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1078
1079         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1080         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1081
1082 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1083             Vineet Sharma      <vineets@noida.hcltech.com>
1084
1085         * maxq.h: New file: Disassembly information for the maxq port.
1086
1087 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1088
1089         * i386.h (i386_optab): Put back "movzb".
1090
1091 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1092
1093         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1094         comments.  Remove member cris_ver_sim.  Add members
1095         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1096         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1097         (struct cris_support_reg, struct cris_cond15): New types.
1098         (cris_conds15): Declare.
1099         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1100         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1101         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1102         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1103         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1104         SIZE_FIELD_UNSIGNED.
1105
1106 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1107
1108         * i386.h (sldx_Suf): Remove.
1109         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1110         (q_FP): Define, implying no REX64.
1111         (x_FP, sl_FP): Imply FloatMF.
1112         (i386_optab): Split reg and mem forms of moving from segment registers
1113         so that the memory forms can ignore the 16-/32-bit operand size
1114         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1115         all non-floating-point instructions. Unite 32- and 64-bit forms of
1116         movsx, movzx, and movd. Adjust floating point operations for the above
1117         changes to the *FP macros. Add DefaultSize to floating point control
1118         insns operating on larger memory ranges. Remove left over comments
1119         hinting at certain insns being Intel-syntax ones where the ones
1120         actually meant are already gone.
1121
1122 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1123
1124         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1125         instruction type.
1126
1127 2004-09-30  Paul Brook  <paul@codesourcery.com>
1128
1129         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1130         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1131
1132 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1133
1134         * avr.h: Add support for
1135         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1136
1137 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1138
1139         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1140
1141 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1142
1143         * msp430.h (msp430_opc): Add new instructions.
1144         (msp430_rcodes): Declare new instructions.
1145         (msp430_hcodes): Likewise..
1146
1147 2004-08-13  Nick Clifton  <nickc@redhat.com>
1148
1149         PR/301
1150         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1151         processors.
1152
1153 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1154
1155         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1156
1157 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1158
1159         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1160
1161 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1162
1163         * i386.h: Adjust instruction descriptions to better match the
1164         specification.
1165
1166 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1167
1168         * arm.h: Remove all old content.  Replace with architecture defines
1169         from gas/config/tc-arm.c.
1170
1171 2004-07-09  Andreas Schwab  <schwab@suse.de>
1172
1173         * m68k.h: Fix comment.
1174
1175 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1176
1177         * crx.h: New file.
1178
1179 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1180
1181         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1182
1183 2004-05-24  Peter Barada  <peter@the-baradas.com>
1184
1185         * m68k.h: Add 'size' to m68k_opcode.
1186
1187 2004-05-05  Peter Barada  <peter@the-baradas.com>
1188
1189         * m68k.h: Switch from ColdFire chip name to core variant.
1190
1191 2004-04-22  Peter Barada  <peter@the-baradas.com>
1192
1193         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1194         descriptions for new EMAC cases.
1195         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1196         handle Motorola MAC syntax.
1197         Allow disassembly of ColdFire V4e object files.
1198
1199 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1200
1201         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1202
1203 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1204
1205         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1206
1207 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1208
1209         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1210
1211 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1212
1213         * i386.h (i386_optab): Added xstore/xcrypt insns.
1214
1215 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1216
1217         * h8300.h (32bit ldc/stc): Add relaxing support.
1218
1219 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1220
1221         * h8300.h (BITOP): Pass MEMRELAX flag.
1222
1223 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1224
1225         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1226         except for the H8S.
1227
1228 For older changes see ChangeLog-9103
1229 \f
1230 Local Variables:
1231 mode: change-log
1232 left-margin: 8
1233 fill-column: 74
1234 version-control: never
1235 End: