include/opcode/ChangeLog

   1 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
   2
   3         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
   4         adjust them accordingly.
   5
   6 2005-04-01  Jan Beulich  <jbeulich@novell.com>
   7
   8         * i386.h (i386_optab): Add rdtscp.
   9
  10 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  13         between memory and segment register. Allow movq for moving between
  14         general-purpose register and segment register.
  15
  16 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  17
  18         PR gas/707
  19         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  20         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  21         fnstsw.
  22
  23 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  24
  25         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  26         * cgen.h (enum cgen_parse_operand_type): Add
  27         CGEN_PARSE_OPERAND_SYMBOLIC.
  28
  29 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  30
  31         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  32         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  33         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  34
  35 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  36
  37         * mips.h (struct mips_opcode): Add new pinfo2 member.
  38         (INSN_ALIAS): New define for opcode table entries that are
  39         specific instances of another entry, such as 'move' for an 'or'
  40         with a zero operand.
  41         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  42         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  43
  44 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  45
  46         * mips.h (CPU_RM9000): Define.
  47         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  48
  49 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  50
  51         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  52         to/from test registers are illegal in 64-bit mode. Add missing
  53         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  54         (previously one had to explicitly encode a rex64 prefix). Re-enable
  55         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  56         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  57
  58 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  59
  60         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
  61         available only with SSE2. Change the MMX additions introduced by SSE
  62         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
  63         instructions by their now designated identifier (since combining i686
  64         and 3DNow! does not really imply 3DNow!A).
  65
  66 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  67
  68         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
  69         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
  70
  71 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  72             Vineet Sharma      <vineets@noida.hcltech.com>
  73
  74         * maxq.h: New file: Disassembly information for the maxq port.
  75
  76 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386.h (i386_optab): Put back "movzb".
  79
  80 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  81
  82         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  83         comments.  Remove member cris_ver_sim.  Add members
  84         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  85         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  86         (struct cris_support_reg, struct cris_cond15): New types.
  87         (cris_conds15): Declare.
  88         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  89         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  90         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  91         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  92         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  93         SIZE_FIELD_UNSIGNED.
  94
  95 2004-11-04 Jan Beulich  <jbeulich@novell.com>
  96
  97         * i386.h (sldx_Suf): Remove.
  98         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  99         (q_FP): Define, implying no REX64.
 100         (x_FP, sl_FP): Imply FloatMF.
 101         (i386_optab): Split reg and mem forms of moving from segment registers
 102         so that the memory forms can ignore the 16-/32-bit operand size
 103         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 104         all non-floating-point instructions. Unite 32- and 64-bit forms of
 105         movsx, movzx, and movd. Adjust floating point operations for the above
 106         changes to the *FP macros. Add DefaultSize to floating point control
 107         insns operating on larger memory ranges. Remove left over comments
 108         hinting at certain insns being Intel-syntax ones where the ones
 109         actually meant are already gone.
 110
 111 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 112
 113         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 114         instruction type.
 115
 116 2004-09-30  Paul Brook  <paul@codesourcery.com>
 117
 118         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 119         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 120
 121 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 122
 123         * avr.h: Add support for
 124         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 125
 126 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 127
 128         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 129
 130 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 131
 132         * msp430.h (msp430_opc): Add new instructions.
 133         (msp430_rcodes): Declare new instructions.
 134         (msp430_hcodes): Likewise..
 135
 136 2004-08-13  Nick Clifton  <nickc@redhat.com>
 137
 138         PR/301
 139         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 140         processors.
 141
 142 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 143
 144         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 145
 146 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 149
 150 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 151
 152         * i386.h: Adjust instruction descriptions to better match the
 153         specification.
 154
 155 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 156
 157         * arm.h: Remove all old content.  Replace with architecture defines
 158         from gas/config/tc-arm.c.
 159
 160 2004-07-09  Andreas Schwab  <schwab@suse.de>
 161
 162         * m68k.h: Fix comment.
 163
 164 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 165
 166         * crx.h: New file.
 167
 168 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 169
 170         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 171
 172 2004-05-24  Peter Barada  <peter@the-baradas.com>
 173
 174         * m68k.h: Add 'size' to m68k_opcode.
 175
 176 2004-05-05  Peter Barada  <peter@the-baradas.com>
 177
 178         * m68k.h: Switch from ColdFire chip name to core variant.
 179
 180 2004-04-22  Peter Barada  <peter@the-baradas.com>
 181
 182         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 183         descriptions for new EMAC cases.
 184         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 185         handle Motorola MAC syntax.
 186         Allow disassembly of ColdFire V4e object files.
 187
 188 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 189
 190         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 191
 192 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 193
 194         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 195
 196 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 197
 198         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 199
 200 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 201
 202         * i386.h (i386_optab): Added xstore/xcrypt insns.
 203
 204 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 205
 206         * h8300.h (32bit ldc/stc): Add relaxing support.
 207
 208 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 209
 210         * h8300.h (BITOP): Pass MEMRELAX flag.
 211
 212 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 213
 214         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 215         except for the H8S.
 216
 217 For older changes see ChangeLog-9103
 218 \f
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