include/opcode/ChangeLog

   1 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
   2
   3         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
   4         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
   5         values.
   6
   7 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  10
  11 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  12
  13         * score-inst.h (enum score_insn_type): Add Insn_internal.
  14
  15 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  16             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  17             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  18             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  19             Alan Modra  <amodra@bigpond.net.au>
  20
  21         * spu-insns.h: New file.
  22         * spu.h: New file.
  23
  24 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  25
  26         * ppc.h (PPC_OPCODE_CELL): Define.
  27
  28 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  29
  30         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  31         in amdfam10 architecture.
  32
  33 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386.h: Replace CpuMNI with CpuSSSE3.
  36
  37 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  38             Joseph Myers  <joseph@codesourcery.com>
  39             Ian Lance Taylor  <ian@wasabisystems.com>
  40             Ben Elliston  <bje@wasabisystems.com>
  41
  42         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  43
  44 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  45
  46         * score-datadep.h: New file.
  47         * score-inst.h: New file.
  48
  49 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  52         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  53         movdq2q and movq2dq.
  54
  55 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  56            Michael Meissner             <michael.meissner@amd.com>
  57
  58         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  59
  60 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386.h (i386_optab): Add "nop" with memory reference.
  63
  64 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386.h (i386_optab): Update comment for 64bit NOP.
  67
  68 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  69             Anton Blanchard  <anton@samba.org>
  70
  71         * ppc.h (PPC_OPCODE_POWER6): Define.
  72         Adjust whitespace.
  73
  74 2006-06-05  Thiemo Seufer  <ths@mips.com>
  75
  76         * mips.h: Improve description of MT flags.
  77
  78 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  79
  80         * m68k.h (mcf_mask): Define.
  81
  82 2006-05-05  Thiemo Seufer  <ths@mips.com>
  83             David Ung  <davidu@mips.com>
  84
  85         * mips.h (enum): Add macro M_CACHE_AB.
  86
  87 2006-05-04  Thiemo Seufer  <ths@mips.com>
  88             Nigel Stephens  <nigel@mips.com>
  89             David Ung  <davidu@mips.com>
  90
  91         * mips.h: Add INSN_SMARTMIPS define.
  92
  93 2006-04-30  Thiemo Seufer  <ths@mips.com>
  94             David Ung  <davidu@mips.com>
  95
  96         * mips.h: Defines udi bits and masks.  Add description of
  97         characters which may appear in the args field of udi
  98         instructions.
  99
 100 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 101
 102         * mips.h: Improve comments describing the bitfield instruction
 103         fields.
 104
 105 2006-04-26  Julian Brown  <julian@codesourcery.com>
 106
 107         * arm.h (FPU_VFP_EXT_V3): Define constant.
 108         (FPU_NEON_EXT_V1): Likewise.
 109         (FPU_VFP_HARD): Update.
 110         (FPU_VFP_V3): Define macro.
 111         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 112
 113 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 114
 115         * avr.h (AVR_ISA_PWMx): New.
 116
 117 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 118
 119         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 120         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 121         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 122         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 123         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 124
 125 2006-03-10  Paul Brook  <paul@codesourcery.com>
 126
 127         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 128
 129 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 130
 131         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 132         first.  Correct mask of bb "B" opcode.
 133
 134 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 135
 136         * i386.h (i386_optab): Support Intel Merom New Instructions.
 137
 138 2006-02-24  Paul Brook  <paul@codesourcery.com>
 139
 140         * arm.h: Add V7 feature bits.
 141
 142 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 145
 146 2006-01-31  Paul Brook  <paul@codesourcery.com>
 147         Richard Earnshaw <rearnsha@arm.com>
 148
 149         * arm.h: Use ARM_CPU_FEATURE.
 150         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 151         (arm_feature_set): Change to a structure.
 152         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 153         ARM_FEATURE): New macros.
 154
 155 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 156
 157         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 158         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 159         (ADD_PC_INCR_OPCODE): Don't define.
 160
 161 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         PR gas/1874
 164         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 165
 166 2005-11-14  David Ung  <davidu@mips.com>
 167
 168         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 169         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 170         save/restore encoding of the args field.
 171
 172 2005-10-28  Dave Brolley  <brolley@redhat.com>
 173
 174         Contribute the following changes:
 175         2005-02-16  Dave Brolley  <brolley@redhat.com>
 176
 177         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 178         cgen_isa_mask_* to cgen_bitset_*.
 179         * cgen.h: Likewise.
 180
 181         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 182
 183         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 184         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 185         (CGEN_CPU_TABLE): Make isas a ponter.
 186
 187         2003-09-29  Dave Brolley  <brolley@redhat.com>
 188
 189         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 190         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 191         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 192
 193         2002-12-13  Dave Brolley  <brolley@redhat.com>
 194
 195         * cgen.h (symcat.h): #include it.
 196         (cgen-bitset.h): #include it.
 197         (CGEN_ATTR_VALUE_TYPE): Now a union.
 198         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 199         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 200         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 201         * cgen-bitset.h: New file.
 202
 203 2005-09-30  Catherine Moore  <clm@cm00re.com>
 204
 205         * bfin.h: New file.
 206
 207 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 208
 209         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 210         indirect operands.
 211
 212 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 213
 214         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 215         Add FLAG_STRICT to pa10 ftest opcode.
 216
 217 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 218
 219         * hppa.h (pa_opcodes): Remove lha entries.
 220
 221 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 222
 223         * hppa.h (FLAG_STRICT): Revise comment.
 224         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 225         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 226         entries for "fdc".
 227
 228 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 229
 230         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 231
 232 2005-09-06  Chao-ying Fu  <fu@mips.com>
 233
 234         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 235         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 236         define.
 237         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 238         (INSN_ASE_MASK): Update to include INSN_MT.
 239         (INSN_MT): New define for MT ASE.
 240
 241 2005-08-25  Chao-ying Fu  <fu@mips.com>
 242
 243         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 244         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 245         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 246         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 247         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 248         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 249         instructions.
 250         (INSN_DSP): New define for DSP ASE.
 251
 252 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 253
 254         * a29k.h: Delete.
 255
 256 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 257
 258         * ppc.h (PPC_OPCODE_E300): Define.
 259
 260 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 261
 262         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 263
 264 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 265
 266         PR gas/336
 267         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 268         and pitlb.
 269
 270 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 271
 272         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 273         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 274         Add movq-s as 64-bit variants of movd-s.
 275
 276 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 277
 278         * hppa.h: Fix punctuation in comment.
 279
 280         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 281         implicit space-register addressing.  Set space-register bits on opcodes
 282         using implicit space-register addressing.  Add various missing pa20
 283         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 284         space-register addressing.  Use "fE" instead of "fe" in various
 285         fstw opcodes.
 286
 287 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 288
 289         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 290
 291 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 292
 293         * i386.h (i386_optab): Support Intel VMX Instructions.
 294
 295 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 296
 297         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 298
 299 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 300
 301         * i386.h (i386_optab): Add new insns.
 302
 303 2005-07-01  Nick Clifton  <nickc@redhat.com>
 304
 305         * sparc.h: Add typedefs to structure declarations.
 306
 307 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         PR 1013
 310         * i386.h (i386_optab): Update comments for 64bit addressing on
 311         mov. Allow 64bit addressing for mov and movq.
 312
 313 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 314
 315         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 316         respectively, in various floating-point load and store patterns.
 317
 318 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 319
 320         * hppa.h (FLAG_STRICT): Correct comment.
 321         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 322         PA 2.0 mneumonics when equivalent.  Entries with cache control
 323         completers now require PA 1.1.  Adjust whitespace.
 324
 325 2005-05-19  Anton Blanchard  <anton@samba.org>
 326
 327         * ppc.h (PPC_OPCODE_POWER5): Define.
 328
 329 2005-05-10  Nick Clifton  <nickc@redhat.com>
 330
 331         * Update the address and phone number of the FSF organization in
 332         the GPL notices in the following files:
 333         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 334         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 335         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 336         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 337         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 338         tic54x.h, tic80.h, v850.h, vax.h
 339
 340 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 341
 342         * i386.h (i386_optab): Add ht and hnt.
 343
 344 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 345
 346         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 347         Add xcrypt-ctr.  Provide aliases without hyphens.
 348
 349 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         Moved from ../ChangeLog
 352
 353         2005-04-12  Paul Brook  <paul@codesourcery.com>
 354         * m88k.h: Rename psr macros to avoid conflicts.
 355
 356         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 357         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 358         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 359         and ARM_ARCH_V6ZKT2.
 360
 361         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 362         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 363         Remove redundant instruction types.
 364         (struct argument): X_op - new field.
 365         (struct cst4_entry): Remove.
 366         (no_op_insn): Declare.
 367
 368         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 369         * crx.h (enum argtype): Rename types, remove unused types.
 370
 371         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 372         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 373         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 374         (enum operand_type): Rearrange operands, edit comments.
 375         replace us<N> with ui<N> for unsigned immediate.
 376         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 377         displacements (respectively).
 378         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 379         (instruction type): Add NO_TYPE_INS.
 380         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 381         (operand_entry): New field - 'flags'.
 382         (operand flags): New.
 383
 384         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 385         * crx.h (operand_type): Remove redundant types i3, i4,
 386         i5, i8, i12.
 387         Add new unsigned immediate types us3, us4, us5, us16.
 388
 389 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 390
 391         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 392         adjust them accordingly.
 393
 394 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 395
 396         * i386.h (i386_optab): Add rdtscp.
 397
 398 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 401         between memory and segment register. Allow movq for moving between
 402         general-purpose register and segment register.
 403
 404 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 405
 406         PR gas/707
 407         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 408         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 409         fnstsw.
 410
 411 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 412
 413         * m68k.h (m68008, m68ec030, m68882): Remove.
 414         (m68k_mask): New.
 415         (cpu_m68k, cpu_cf): New.
 416         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 417         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 418
 419 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 420
 421         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 422         * cgen.h (enum cgen_parse_operand_type): Add
 423         CGEN_PARSE_OPERAND_SYMBOLIC.
 424
 425 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 426
 427         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 428         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 429         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 430
 431 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 432
 433         * mips.h (struct mips_opcode): Add new pinfo2 member.
 434         (INSN_ALIAS): New define for opcode table entries that are
 435         specific instances of another entry, such as 'move' for an 'or'
 436         with a zero operand.
 437         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 438         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 439
 440 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 441
 442         * mips.h (CPU_RM9000): Define.
 443         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 444
 445 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 446
 447         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 448         to/from test registers are illegal in 64-bit mode. Add missing
 449         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 450         (previously one had to explicitly encode a rex64 prefix). Re-enable
 451         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 452         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 453
 454 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 455
 456         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 457         available only with SSE2. Change the MMX additions introduced by SSE
 458         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 459         instructions by their now designated identifier (since combining i686
 460         and 3DNow! does not really imply 3DNow!A).
 461
 462 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 463
 464         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 465         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 466
 467 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 468             Vineet Sharma      <vineets@noida.hcltech.com>
 469
 470         * maxq.h: New file: Disassembly information for the maxq port.
 471
 472 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         * i386.h (i386_optab): Put back "movzb".
 475
 476 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 477
 478         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 479         comments.  Remove member cris_ver_sim.  Add members
 480         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 481         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 482         (struct cris_support_reg, struct cris_cond15): New types.
 483         (cris_conds15): Declare.
 484         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 485         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 486         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 487         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 488         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 489         SIZE_FIELD_UNSIGNED.
 490
 491 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 492
 493         * i386.h (sldx_Suf): Remove.
 494         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 495         (q_FP): Define, implying no REX64.
 496         (x_FP, sl_FP): Imply FloatMF.
 497         (i386_optab): Split reg and mem forms of moving from segment registers
 498         so that the memory forms can ignore the 16-/32-bit operand size
 499         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 500         all non-floating-point instructions. Unite 32- and 64-bit forms of
 501         movsx, movzx, and movd. Adjust floating point operations for the above
 502         changes to the *FP macros. Add DefaultSize to floating point control
 503         insns operating on larger memory ranges. Remove left over comments
 504         hinting at certain insns being Intel-syntax ones where the ones
 505         actually meant are already gone.
 506
 507 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 508
 509         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 510         instruction type.
 511
 512 2004-09-30  Paul Brook  <paul@codesourcery.com>
 513
 514         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 515         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 516
 517 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 518
 519         * avr.h: Add support for
 520         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 521
 522 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 523
 524         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 525
 526 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 527
 528         * msp430.h (msp430_opc): Add new instructions.
 529         (msp430_rcodes): Declare new instructions.
 530         (msp430_hcodes): Likewise..
 531
 532 2004-08-13  Nick Clifton  <nickc@redhat.com>
 533
 534         PR/301
 535         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 536         processors.
 537
 538 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 539
 540         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 541
 542 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 543
 544         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 545
 546 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 547
 548         * i386.h: Adjust instruction descriptions to better match the
 549         specification.
 550
 551 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 552
 553         * arm.h: Remove all old content.  Replace with architecture defines
 554         from gas/config/tc-arm.c.
 555
 556 2004-07-09  Andreas Schwab  <schwab@suse.de>
 557
 558         * m68k.h: Fix comment.
 559
 560 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 561
 562         * crx.h: New file.
 563
 564 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 565
 566         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 567
 568 2004-05-24  Peter Barada  <peter@the-baradas.com>
 569
 570         * m68k.h: Add 'size' to m68k_opcode.
 571
 572 2004-05-05  Peter Barada  <peter@the-baradas.com>
 573
 574         * m68k.h: Switch from ColdFire chip name to core variant.
 575
 576 2004-04-22  Peter Barada  <peter@the-baradas.com>
 577
 578         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 579         descriptions for new EMAC cases.
 580         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 581         handle Motorola MAC syntax.
 582         Allow disassembly of ColdFire V4e object files.
 583
 584 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 585
 586         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 587
 588 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 589
 590         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 591
 592 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 593
 594         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 595
 596 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 597
 598         * i386.h (i386_optab): Added xstore/xcrypt insns.
 599
 600 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 601
 602         * h8300.h (32bit ldc/stc): Add relaxing support.
 603
 604 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 605
 606         * h8300.h (BITOP): Pass MEMRELAX flag.
 607
 608 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 609
 610         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 611         except for the H8S.
 612
 613 For older changes see ChangeLog-9103
 614 \f
 615 Local Variables:
 616 mode: change-log
 617 left-margin: 8
 618 fill-column: 74
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 620 End: