1 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
3 * mips.h: Add support for r5900 instructions including lq and sq.
5 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
7 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
8 (make_instruction,match_opcode): Added function prototypes.
9 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
11 2012-11-23 Alan Modra <amodra@gmail.com>
13 * ppc.h (ppc_parse_cpu): Update prototype.
15 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
17 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
18 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
20 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
22 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
24 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
26 * ia64.h (ia64_opnd): Add new operand types.
28 2012-08-21 David S. Miller <davem@davemloft.net>
30 * sparc.h (F3F4): New macro.
32 2012-08-13 Ian Bolton <ian.bolton@arm.com>
33 Laurent Desnogues <laurent.desnogues@arm.com>
34 Jim MacArthur <jim.macarthur@arm.com>
35 Marcus Shawcroft <marcus.shawcroft@arm.com>
36 Nigel Stephens <nigel.stephens@arm.com>
37 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
38 Richard Earnshaw <rearnsha@arm.com>
39 Sofiane Naci <sofiane.naci@arm.com>
40 Tejas Belagod <tejas.belagod@arm.com>
41 Yufeng Zhang <yufeng.zhang@arm.com>
43 * aarch64.h: New file.
45 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
46 Maciej W. Rozycki <macro@codesourcery.com>
48 * mips.h (mips_opcode): Add the exclusions field.
49 (OPCODE_IS_MEMBER): Remove macro.
50 (cpu_is_member): New inline function.
51 (opcode_is_member): Likewise.
53 2012-07-31 Chao-Ying Fu <fu@mips.com>
54 Catherine Moore <clm@codesourcery.com>
55 Maciej W. Rozycki <macro@codesourcery.com>
57 * mips.h: Document microMIPS DSP ASE usage.
58 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
59 microMIPS DSP ASE support.
60 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
61 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
62 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
63 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
64 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
65 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
66 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
68 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
70 * mips.h: Fix a typo in description.
72 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
74 * avr.h: (AVR_ISA_XCH): New define.
75 (AVR_ISA_XMEGA): Use it.
76 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
78 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
80 * m68hc11.h: Add XGate definitions.
81 (struct m68hc11_opcode): Add xg_mask field.
83 2012-05-14 Catherine Moore <clm@codesourcery.com>
84 Maciej W. Rozycki <macro@codesourcery.com>
85 Rhonda Wittels <rhonda@codesourcery.com>
87 * ppc.h (PPC_OPCODE_VLE): New definition.
88 (PPC_OP_SA): New macro.
89 (PPC_OP_SE_VLE): New macro.
90 (PPC_OP): Use a variable shift amount.
91 (powerpc_operand): Update comments.
92 (PPC_OPSHIFT_INV): New macro.
93 (PPC_OPERAND_CR): Replace with...
94 (PPC_OPERAND_CR_BIT): ...this and
95 (PPC_OPERAND_CR_REG): ...this.
98 2012-05-03 Sean Keys <skeys@ipdatasys.com>
100 * xgate.h: Header file for XGATE assembler.
102 2012-04-27 David S. Miller <davem@davemloft.net>
104 * sparc.h: Document new arg code' )' for crypto RS3
107 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
108 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
109 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
110 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
111 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
112 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
113 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
114 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
115 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
116 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
117 HWCAP_CBCOND, HWCAP_CRC32): New defines.
119 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
121 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
123 2012-02-27 Alan Modra <amodra@gmail.com>
125 * crx.h (cst4_map): Update declaration.
127 2012-02-25 Walter Lee <walt@tilera.com>
129 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
131 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
132 TILEPRO_OPC_LW_TLS_SN.
134 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
136 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
137 (XRELEASE_PREFIX_OPCODE): Likewise.
139 2011-12-08 Andrew Pinski <apinski@cavium.com>
140 Adam Nemet <anemet@caviumnetworks.com>
142 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
143 (INSN_OCTEON2): New macro.
144 (CPU_OCTEON2): New macro.
145 (OPCODE_IS_MEMBER): Add Octeon2.
147 2011-11-29 Andrew Pinski <apinski@cavium.com>
149 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
150 (INSN_OCTEONP): New macro.
151 (CPU_OCTEONP): New macro.
152 (OPCODE_IS_MEMBER): Add Octeon+.
153 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
155 2011-11-01 DJ Delorie <dj@redhat.com>
159 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
161 * mips.h: Fix a typo in description.
163 2011-09-21 David S. Miller <davem@davemloft.net>
165 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
166 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
167 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
168 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
170 2011-08-09 Chao-ying Fu <fu@mips.com>
171 Maciej W. Rozycki <macro@codesourcery.com>
173 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
174 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
175 (INSN_ASE_MASK): Add the MCU bit.
176 (INSN_MCU): New macro.
177 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
178 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
180 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
182 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
183 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
184 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
185 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
186 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
187 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
188 (INSN2_READ_GPR_MMN): Likewise.
189 (INSN2_READ_FPR_D): Change the bit used.
190 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
191 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
192 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
193 (INSN2_COND_BRANCH): Likewise.
194 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
195 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
196 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
197 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
198 (INSN2_MOD_GPR_MN): Likewise.
200 2011-08-05 David S. Miller <davem@davemloft.net>
202 * sparc.h: Document new format codes '4', '5', and '('.
203 (OPF_LOW4, RS3): New macros.
205 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
207 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
208 order of flags documented.
210 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
212 * mips.h: Clarify the description of microMIPS instruction
214 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
216 2011-07-24 Chao-ying Fu <fu@mips.com>
217 Maciej W. Rozycki <macro@codesourcery.com>
219 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
220 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
221 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
222 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
223 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
224 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
225 (OP_MASK_RS3, OP_SH_RS3): Likewise.
226 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
227 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
228 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
229 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
230 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
231 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
232 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
233 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
234 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
235 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
236 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
237 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
238 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
239 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
240 (INSN_WRITE_GPR_S): New macro.
241 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
242 (INSN2_READ_FPR_D): Likewise.
243 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
244 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
245 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
246 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
247 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
248 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
249 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
250 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
251 (CPU_MICROMIPS): New macro.
252 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
253 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
254 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
255 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
256 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
257 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
258 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
259 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
260 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
261 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
262 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
263 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
264 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
265 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
266 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
267 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
268 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
269 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
270 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
271 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
272 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
273 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
274 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
275 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
276 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
277 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
278 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
279 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
280 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
281 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
282 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
283 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
284 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
285 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
286 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
287 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
288 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
289 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
290 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
291 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
292 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
293 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
294 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
295 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
296 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
297 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
298 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
299 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
300 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
301 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
302 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
303 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
304 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
305 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
306 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
307 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
308 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
309 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
310 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
311 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
312 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
313 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
314 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
315 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
316 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
317 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
318 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
319 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
320 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
321 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
322 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
323 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
324 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
325 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
326 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
327 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
328 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
329 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
330 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
331 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
332 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
333 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
334 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
335 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
336 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
337 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
338 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
339 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
340 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
341 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
342 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
343 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
344 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
345 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
346 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
347 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
348 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
349 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
350 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
351 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
352 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
353 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
354 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
355 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
356 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
357 (micromips_opcodes): New declaration.
358 (bfd_micromips_num_opcodes): Likewise.
360 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
362 * mips.h (INSN_TRAP): Rename to...
363 (INSN_NO_DELAY_SLOT): ... this.
364 (INSN_SYNC): Remove macro.
366 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
368 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
369 a duplicate of AVR_ISA_SPM.
371 2011-07-01 Nick Clifton <nickc@redhat.com>
373 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
375 2011-06-18 Robin Getz <robin.getz@analog.com>
377 * bfin.h (is_macmod_signed): New func
379 2011-06-18 Mike Frysinger <vapier@gentoo.org>
381 * bfin.h (is_macmod_pmove): Add missing space before func args.
382 (is_macmod_hmove): Likewise.
384 2011-06-13 Walter Lee <walt@tilera.com>
386 * tilegx.h: New file.
387 * tilepro.h: New file.
389 2011-05-31 Paul Brook <paul@codesourcery.com>
391 * arm.h (ARM_ARCH_V7R_IDIV): Define.
393 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
395 * s390.h: Replace S390_OPERAND_REG_EVEN with
396 S390_OPERAND_REG_PAIR.
398 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
400 * s390.h: Add S390_OPCODE_REG_EVEN flag.
402 2011-04-18 Julian Brown <julian@codesourcery.com>
404 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
406 2011-04-11 Dan McDonald <dan@wellkeeper.com>
409 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
411 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
413 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
414 New instruction set flags.
415 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
417 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
419 * mips.h (M_PREF_AB): New enum value.
421 2011-02-12 Mike Frysinger <vapier@gentoo.org>
423 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
425 (is_macmod_pmove, is_macmod_hmove): New functions.
427 2011-02-11 Mike Frysinger <vapier@gentoo.org>
429 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
431 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
433 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
434 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
436 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
439 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
442 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
445 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
447 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
449 * mips.h: Update commentary after last commit.
451 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
453 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
454 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
455 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
457 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
459 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
461 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
463 * mips.h: Fix previous commit.
465 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
467 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
468 (INSN_LOONGSON_3A): Clear bit 31.
470 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
473 * arm.h (ARM_AEXT_V6M_ONLY): New define.
474 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
475 (ARM_ARCH_V6M_ONLY): New define.
477 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
479 * mips.h (INSN_LOONGSON_3A): Defined.
480 (CPU_LOONGSON_3A): Defined.
481 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
483 2010-10-09 Matt Rice <ratmice@gmail.com>
485 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
486 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
488 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
490 * arm.h (ARM_EXT_VIRT): New define.
491 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
492 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
495 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
497 * arm.h (ARM_AEXT_ADIV): New define.
498 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
500 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
502 * arm.h (ARM_EXT_OS): New define.
503 (ARM_AEXT_V6SM): Likewise.
504 (ARM_ARCH_V6SM): Likewise.
506 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
508 * arm.h (ARM_EXT_MP): Add.
509 (ARM_ARCH_V7A_MP): Likewise.
511 2010-09-22 Mike Frysinger <vapier@gentoo.org>
513 * bfin.h: Declare pseudoChr structs/defines.
515 2010-09-21 Mike Frysinger <vapier@gentoo.org>
517 * bfin.h: Strip trailing whitespace.
519 2010-07-29 DJ Delorie <dj@redhat.com>
521 * rx.h (RX_Operand_Type): Add TwoReg.
522 (RX_Opcode_ID): Remove ediv and ediv2.
524 2010-07-27 DJ Delorie <dj@redhat.com>
526 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
528 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
529 Ina Pandit <ina.pandit@kpitcummins.com>
531 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
532 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
533 PROCESSOR_V850E2_ALL.
534 Remove PROCESSOR_V850EA support.
535 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
536 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
537 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
538 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
539 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
540 V850_OPERAND_PERCENT.
541 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
543 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
546 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
548 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
549 (MIPS16_INSN_BRANCH): Rename to...
550 (MIPS16_INSN_COND_BRANCH): ... this.
552 2010-07-03 Alan Modra <amodra@gmail.com>
554 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
555 Renumber other PPC_OPCODE defines.
557 2010-07-03 Alan Modra <amodra@gmail.com>
559 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
561 2010-06-29 Alan Modra <amodra@gmail.com>
563 * maxq.h: Delete file.
565 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
567 * ppc.h (PPC_OPCODE_E500): Define.
569 2010-05-26 Catherine Moore <clm@codesourcery.com>
571 * opcode/mips.h (INSN_MIPS16): Remove.
573 2010-04-21 Joseph Myers <joseph@codesourcery.com>
575 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
577 2010-04-15 Nick Clifton <nickc@redhat.com>
579 * alpha.h: Update copyright notice to use GPLv3.
585 * convex.h: Likewise.
599 * m68hc11.h: Likewise.
605 * mn10200.h: Likewise.
606 * mn10300.h: Likewise.
607 * msp430.h: Likewise.
618 * score-datadep.h: Likewise.
619 * score-inst.h: Likewise.
621 * spu-insns.h: Likewise.
625 * tic54x.h: Likewise.
630 2010-03-25 Joseph Myers <joseph@codesourcery.com>
632 * tic6x-control-registers.h, tic6x-insn-formats.h,
633 tic6x-opcode-table.h, tic6x.h: New.
635 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
637 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
639 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
641 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
643 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
645 * ia64.h (ia64_find_opcode): Remove argument name.
646 (ia64_find_next_opcode): Likewise.
647 (ia64_dis_opcode): Likewise.
648 (ia64_free_opcode): Likewise.
649 (ia64_find_dependency): Likewise.
651 2009-11-22 Doug Evans <dje@sebabeach.org>
653 * cgen.h: Include bfd_stdint.h.
654 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
656 2009-11-18 Paul Brook <paul@codesourcery.com>
658 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
660 2009-11-17 Paul Brook <paul@codesourcery.com>
661 Daniel Jacobowitz <dan@codesourcery.com>
663 * arm.h (ARM_EXT_V6_DSP): Define.
664 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
665 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
667 2009-11-04 DJ Delorie <dj@redhat.com>
669 * rx.h (rx_decode_opcode) (mvtipl): Add.
670 (mvtcp, mvfcp, opecp): Remove.
672 2009-11-02 Paul Brook <paul@codesourcery.com>
674 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
675 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
676 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
677 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
678 FPU_ARCH_NEON_VFP_V4): Define.
680 2009-10-23 Doug Evans <dje@sebabeach.org>
682 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
683 * cgen.h: Update. Improve multi-inclusion macro name.
685 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
687 * ppc.h (PPC_OPCODE_476): Define.
689 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
691 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
693 2009-09-29 DJ Delorie <dj@redhat.com>
697 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
699 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
701 2009-09-21 Ben Elliston <bje@au.ibm.com>
703 * ppc.h (PPC_OPCODE_PPCA2): New.
705 2009-09-05 Martin Thuresson <martin@mtme.org>
707 * ia64.h (struct ia64_operand): Renamed member class to op_class.
709 2009-08-29 Martin Thuresson <martin@mtme.org>
711 * tic30.h (template): Rename type template to
712 insn_template. Updated code to use new name.
713 * tic54x.h (template): Rename type template to
716 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
718 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
720 2009-06-11 Anthony Green <green@moxielogic.com>
722 * moxie.h (MOXIE_F3_PCREL): Define.
723 (moxie_form3_opc_info): Grow.
725 2009-06-06 Anthony Green <green@moxielogic.com>
727 * moxie.h (MOXIE_F1_M): Define.
729 2009-04-15 Anthony Green <green@moxielogic.com>
733 2009-04-06 DJ Delorie <dj@redhat.com>
735 * h8300.h: Add relaxation attributes to MOVA opcodes.
737 2009-03-10 Alan Modra <amodra@bigpond.net.au>
739 * ppc.h (ppc_parse_cpu): Declare.
741 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
743 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
744 and _IMM11 for mbitclr and mbitset.
745 * score-datadep.h: Update dependency information.
747 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
749 * ppc.h (PPC_OPCODE_POWER7): New.
751 2009-02-06 Doug Evans <dje@google.com>
753 * i386.h: Add comment regarding sse* insns and prefixes.
755 2009-02-03 Sandip Matte <sandip@rmicorp.com>
757 * mips.h (INSN_XLR): Define.
758 (INSN_CHIP_MASK): Update.
760 (OPCODE_IS_MEMBER): Update.
761 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
763 2009-01-28 Doug Evans <dje@google.com>
765 * opcode/i386.h: Add multiple inclusion protection.
766 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
767 (EDI_REG_NUM): New macros.
768 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
769 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
770 (REX_PREFIX_P): New macro.
772 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
774 * ppc.h (struct powerpc_opcode): New field "deprecated".
775 (PPC_OPCODE_NOPOWER4): Delete.
777 2008-11-28 Joshua Kinard <kumba@gentoo.org>
779 * mips.h: Define CPU_R14000, CPU_R16000.
780 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
782 2008-11-18 Catherine Moore <clm@codesourcery.com>
784 * arm.h (FPU_NEON_FP16): New.
785 (FPU_ARCH_NEON_FP16): New.
787 2008-11-06 Chao-ying Fu <fu@mips.com>
789 * mips.h: Doucument '1' for 5-bit sync type.
791 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
793 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
796 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
798 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
800 2008-07-30 Michael J. Eager <eager@eagercon.com>
802 * ppc.h (PPC_OPCODE_405): Define.
803 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
805 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
807 * ppc.h (ppc_cpu_t): New typedef.
808 (struct powerpc_opcode <flags>): Use it.
809 (struct powerpc_operand <insert, extract>): Likewise.
810 (struct powerpc_macro <flags>): Likewise.
812 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
814 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
815 Update comment before MIPS16 field descriptors to mention MIPS16.
816 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
818 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
819 New bit masks and shift counts for cins and exts.
821 * mips.h: Document new field descriptors +Q.
822 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
824 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
826 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
827 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
829 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
831 * ppc.h: (PPC_OPCODE_E500MC): New.
833 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
835 * i386.h (MAX_OPERANDS): Set to 5.
836 (MAX_MNEM_SIZE): Changed to 20.
838 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
840 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
842 2008-03-09 Paul Brook <paul@codesourcery.com>
844 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
846 2008-03-04 Paul Brook <paul@codesourcery.com>
848 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
849 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
850 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
852 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
853 Nick Clifton <nickc@redhat.com>
856 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
857 with a 32-bit displacement but without the top bit of the 4th byte
860 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
862 * cr16.h (cr16_num_optab): Declared.
864 2008-02-14 Hakan Ardo <hakan@debian.org>
867 * avr.h (AVR_ISA_2xxe): Define.
869 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
871 * mips.h: Update copyright.
872 (INSN_CHIP_MASK): New macro.
873 (INSN_OCTEON): New macro.
874 (CPU_OCTEON): New macro.
875 (OPCODE_IS_MEMBER): Handle Octeon instructions.
877 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
879 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
881 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
883 * avr.h (AVR_ISA_USB162): Add new opcode set.
884 (AVR_ISA_AVR3): Likewise.
886 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
888 * mips.h (INSN_LOONGSON_2E): New.
889 (INSN_LOONGSON_2F): New.
890 (CPU_LOONGSON_2E): New.
891 (CPU_LOONGSON_2F): New.
892 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
894 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
896 * mips.h (INSN_ISA*): Redefine certain values as an
897 enumeration. Update comments.
898 (mips_isa_table): New.
899 (ISA_MIPS*): Redefine to match enumeration.
900 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
903 2007-08-08 Ben Elliston <bje@au.ibm.com>
905 * ppc.h (PPC_OPCODE_PPCPS): New.
907 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
909 * m68k.h: Document j K & E.
911 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
913 * cr16.h: New file for CR16 target.
915 2007-05-02 Alan Modra <amodra@bigpond.net.au>
917 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
919 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
921 * m68k.h (mcfisa_c): New.
922 (mcfusp, mcf_mask): Adjust.
924 2007-04-20 Alan Modra <amodra@bigpond.net.au>
926 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
927 (num_powerpc_operands): Declare.
928 (PPC_OPERAND_SIGNED et al): Redefine as hex.
929 (PPC_OPERAND_PLUS1): Define.
931 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
933 * i386.h (REX_MODE64): Renamed to ...
935 (REX_EXTX): Renamed to ...
937 (REX_EXTY): Renamed to ...
939 (REX_EXTZ): Renamed to ...
942 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
944 * i386.h: Add entries from config/tc-i386.h and move tables
945 to opcodes/i386-opc.h.
947 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
949 * i386.h (FloatDR): Removed.
950 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
952 2007-03-01 Alan Modra <amodra@bigpond.net.au>
954 * spu-insns.h: Add soma double-float insns.
956 2007-02-20 Thiemo Seufer <ths@mips.com>
957 Chao-Ying Fu <fu@mips.com>
959 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
960 (INSN_DSPR2): Add flag for DSP R2 instructions.
961 (M_BALIGN): New macro.
963 2007-02-14 Alan Modra <amodra@bigpond.net.au>
965 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
966 and Seg3ShortFrom with Shortform.
968 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
971 * i386.h (i386_optab): Put the real "test" before the pseudo
974 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
976 * m68k.h (m68010up): OR fido_a.
978 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
980 * m68k.h (fido_a): New.
982 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
984 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
985 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
988 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
990 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
992 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
994 * score-inst.h (enum score_insn_type): Add Insn_internal.
996 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
997 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
998 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
999 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1000 Alan Modra <amodra@bigpond.net.au>
1002 * spu-insns.h: New file.
1005 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1007 * ppc.h (PPC_OPCODE_CELL): Define.
1009 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1011 * i386.h : Modify opcode to support for the change in POPCNT opcode
1012 in amdfam10 architecture.
1014 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1016 * i386.h: Replace CpuMNI with CpuSSSE3.
1018 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1019 Joseph Myers <joseph@codesourcery.com>
1020 Ian Lance Taylor <ian@wasabisystems.com>
1021 Ben Elliston <bje@wasabisystems.com>
1023 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1025 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1027 * score-datadep.h: New file.
1028 * score-inst.h: New file.
1030 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1032 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1033 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1034 movdq2q and movq2dq.
1036 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1037 Michael Meissner <michael.meissner@amd.com>
1039 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1041 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1043 * i386.h (i386_optab): Add "nop" with memory reference.
1045 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386.h (i386_optab): Update comment for 64bit NOP.
1049 2006-06-06 Ben Elliston <bje@au.ibm.com>
1050 Anton Blanchard <anton@samba.org>
1052 * ppc.h (PPC_OPCODE_POWER6): Define.
1055 2006-06-05 Thiemo Seufer <ths@mips.com>
1057 * mips.h: Improve description of MT flags.
1059 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1061 * m68k.h (mcf_mask): Define.
1063 2006-05-05 Thiemo Seufer <ths@mips.com>
1064 David Ung <davidu@mips.com>
1066 * mips.h (enum): Add macro M_CACHE_AB.
1068 2006-05-04 Thiemo Seufer <ths@mips.com>
1069 Nigel Stephens <nigel@mips.com>
1070 David Ung <davidu@mips.com>
1072 * mips.h: Add INSN_SMARTMIPS define.
1074 2006-04-30 Thiemo Seufer <ths@mips.com>
1075 David Ung <davidu@mips.com>
1077 * mips.h: Defines udi bits and masks. Add description of
1078 characters which may appear in the args field of udi
1081 2006-04-26 Thiemo Seufer <ths@networkno.de>
1083 * mips.h: Improve comments describing the bitfield instruction
1086 2006-04-26 Julian Brown <julian@codesourcery.com>
1088 * arm.h (FPU_VFP_EXT_V3): Define constant.
1089 (FPU_NEON_EXT_V1): Likewise.
1090 (FPU_VFP_HARD): Update.
1091 (FPU_VFP_V3): Define macro.
1092 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1094 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1096 * avr.h (AVR_ISA_PWMx): New.
1098 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1100 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1101 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1102 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1103 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1104 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1106 2006-03-10 Paul Brook <paul@codesourcery.com>
1108 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1110 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1112 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1113 first. Correct mask of bb "B" opcode.
1115 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1117 * i386.h (i386_optab): Support Intel Merom New Instructions.
1119 2006-02-24 Paul Brook <paul@codesourcery.com>
1121 * arm.h: Add V7 feature bits.
1123 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1125 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1127 2006-01-31 Paul Brook <paul@codesourcery.com>
1128 Richard Earnshaw <rearnsha@arm.com>
1130 * arm.h: Use ARM_CPU_FEATURE.
1131 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1132 (arm_feature_set): Change to a structure.
1133 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1134 ARM_FEATURE): New macros.
1136 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1138 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1139 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1140 (ADD_PC_INCR_OPCODE): Don't define.
1142 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1145 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1147 2005-11-14 David Ung <davidu@mips.com>
1149 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1150 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1151 save/restore encoding of the args field.
1153 2005-10-28 Dave Brolley <brolley@redhat.com>
1155 Contribute the following changes:
1156 2005-02-16 Dave Brolley <brolley@redhat.com>
1158 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1159 cgen_isa_mask_* to cgen_bitset_*.
1162 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1164 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1165 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1166 (CGEN_CPU_TABLE): Make isas a ponter.
1168 2003-09-29 Dave Brolley <brolley@redhat.com>
1170 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1171 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1172 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1174 2002-12-13 Dave Brolley <brolley@redhat.com>
1176 * cgen.h (symcat.h): #include it.
1177 (cgen-bitset.h): #include it.
1178 (CGEN_ATTR_VALUE_TYPE): Now a union.
1179 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1180 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1181 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1182 * cgen-bitset.h: New file.
1184 2005-09-30 Catherine Moore <clm@cm00re.com>
1188 2005-10-24 Jan Beulich <jbeulich@novell.com>
1190 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1193 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1195 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1196 Add FLAG_STRICT to pa10 ftest opcode.
1198 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1200 * hppa.h (pa_opcodes): Remove lha entries.
1202 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1204 * hppa.h (FLAG_STRICT): Revise comment.
1205 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1206 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1209 2005-09-30 Catherine Moore <clm@cm00re.com>
1213 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1215 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1217 2005-09-06 Chao-ying Fu <fu@mips.com>
1219 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1220 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1222 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1223 (INSN_ASE_MASK): Update to include INSN_MT.
1224 (INSN_MT): New define for MT ASE.
1226 2005-08-25 Chao-ying Fu <fu@mips.com>
1228 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1229 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1230 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1231 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1232 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1233 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1235 (INSN_DSP): New define for DSP ASE.
1237 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1241 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1243 * ppc.h (PPC_OPCODE_E300): Define.
1245 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1247 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1249 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1252 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1255 2005-07-27 Jan Beulich <jbeulich@novell.com>
1257 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1258 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1259 Add movq-s as 64-bit variants of movd-s.
1261 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1263 * hppa.h: Fix punctuation in comment.
1265 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1266 implicit space-register addressing. Set space-register bits on opcodes
1267 using implicit space-register addressing. Add various missing pa20
1268 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1269 space-register addressing. Use "fE" instead of "fe" in various
1272 2005-07-18 Jan Beulich <jbeulich@novell.com>
1274 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1276 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1278 * i386.h (i386_optab): Support Intel VMX Instructions.
1280 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1282 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1284 2005-07-05 Jan Beulich <jbeulich@novell.com>
1286 * i386.h (i386_optab): Add new insns.
1288 2005-07-01 Nick Clifton <nickc@redhat.com>
1290 * sparc.h: Add typedefs to structure declarations.
1292 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1295 * i386.h (i386_optab): Update comments for 64bit addressing on
1296 mov. Allow 64bit addressing for mov and movq.
1298 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1300 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1301 respectively, in various floating-point load and store patterns.
1303 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1305 * hppa.h (FLAG_STRICT): Correct comment.
1306 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1307 PA 2.0 mneumonics when equivalent. Entries with cache control
1308 completers now require PA 1.1. Adjust whitespace.
1310 2005-05-19 Anton Blanchard <anton@samba.org>
1312 * ppc.h (PPC_OPCODE_POWER5): Define.
1314 2005-05-10 Nick Clifton <nickc@redhat.com>
1316 * Update the address and phone number of the FSF organization in
1317 the GPL notices in the following files:
1318 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1319 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1320 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1321 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1322 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1323 tic54x.h, tic80.h, v850.h, vax.h
1325 2005-05-09 Jan Beulich <jbeulich@novell.com>
1327 * i386.h (i386_optab): Add ht and hnt.
1329 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1331 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1332 Add xcrypt-ctr. Provide aliases without hyphens.
1334 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1336 Moved from ../ChangeLog
1338 2005-04-12 Paul Brook <paul@codesourcery.com>
1339 * m88k.h: Rename psr macros to avoid conflicts.
1341 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1342 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1343 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1344 and ARM_ARCH_V6ZKT2.
1346 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1347 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1348 Remove redundant instruction types.
1349 (struct argument): X_op - new field.
1350 (struct cst4_entry): Remove.
1351 (no_op_insn): Declare.
1353 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1354 * crx.h (enum argtype): Rename types, remove unused types.
1356 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1357 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1358 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1359 (enum operand_type): Rearrange operands, edit comments.
1360 replace us<N> with ui<N> for unsigned immediate.
1361 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1362 displacements (respectively).
1363 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1364 (instruction type): Add NO_TYPE_INS.
1365 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1366 (operand_entry): New field - 'flags'.
1367 (operand flags): New.
1369 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1370 * crx.h (operand_type): Remove redundant types i3, i4,
1372 Add new unsigned immediate types us3, us4, us5, us16.
1374 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1376 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1377 adjust them accordingly.
1379 2005-04-01 Jan Beulich <jbeulich@novell.com>
1381 * i386.h (i386_optab): Add rdtscp.
1383 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1385 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1386 between memory and segment register. Allow movq for moving between
1387 general-purpose register and segment register.
1389 2005-02-09 Jan Beulich <jbeulich@novell.com>
1392 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1393 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1396 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1398 * m68k.h (m68008, m68ec030, m68882): Remove.
1400 (cpu_m68k, cpu_cf): New.
1401 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1402 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1404 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1406 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1407 * cgen.h (enum cgen_parse_operand_type): Add
1408 CGEN_PARSE_OPERAND_SYMBOLIC.
1410 2005-01-21 Fred Fish <fnf@specifixinc.com>
1412 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1413 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1414 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1416 2005-01-19 Fred Fish <fnf@specifixinc.com>
1418 * mips.h (struct mips_opcode): Add new pinfo2 member.
1419 (INSN_ALIAS): New define for opcode table entries that are
1420 specific instances of another entry, such as 'move' for an 'or'
1421 with a zero operand.
1422 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1423 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1425 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1427 * mips.h (CPU_RM9000): Define.
1428 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1430 2004-11-25 Jan Beulich <jbeulich@novell.com>
1432 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1433 to/from test registers are illegal in 64-bit mode. Add missing
1434 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1435 (previously one had to explicitly encode a rex64 prefix). Re-enable
1436 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1437 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1439 2004-11-23 Jan Beulich <jbeulich@novell.com>
1441 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1442 available only with SSE2. Change the MMX additions introduced by SSE
1443 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1444 instructions by their now designated identifier (since combining i686
1445 and 3DNow! does not really imply 3DNow!A).
1447 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1449 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1450 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1452 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1453 Vineet Sharma <vineets@noida.hcltech.com>
1455 * maxq.h: New file: Disassembly information for the maxq port.
1457 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1459 * i386.h (i386_optab): Put back "movzb".
1461 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1463 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1464 comments. Remove member cris_ver_sim. Add members
1465 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1466 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1467 (struct cris_support_reg, struct cris_cond15): New types.
1468 (cris_conds15): Declare.
1469 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1470 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1471 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1472 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1473 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1474 SIZE_FIELD_UNSIGNED.
1476 2004-11-04 Jan Beulich <jbeulich@novell.com>
1478 * i386.h (sldx_Suf): Remove.
1479 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1480 (q_FP): Define, implying no REX64.
1481 (x_FP, sl_FP): Imply FloatMF.
1482 (i386_optab): Split reg and mem forms of moving from segment registers
1483 so that the memory forms can ignore the 16-/32-bit operand size
1484 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1485 all non-floating-point instructions. Unite 32- and 64-bit forms of
1486 movsx, movzx, and movd. Adjust floating point operations for the above
1487 changes to the *FP macros. Add DefaultSize to floating point control
1488 insns operating on larger memory ranges. Remove left over comments
1489 hinting at certain insns being Intel-syntax ones where the ones
1490 actually meant are already gone.
1492 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1494 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1497 2004-09-30 Paul Brook <paul@codesourcery.com>
1499 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1500 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1502 2004-09-11 Theodore A. Roth <troth@openavr.org>
1504 * avr.h: Add support for
1505 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1507 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1509 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1511 2004-08-24 Dmitry Diky <diwil@spec.ru>
1513 * msp430.h (msp430_opc): Add new instructions.
1514 (msp430_rcodes): Declare new instructions.
1515 (msp430_hcodes): Likewise..
1517 2004-08-13 Nick Clifton <nickc@redhat.com>
1520 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1523 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1525 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1527 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1529 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1531 2004-07-21 Jan Beulich <jbeulich@novell.com>
1533 * i386.h: Adjust instruction descriptions to better match the
1536 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1538 * arm.h: Remove all old content. Replace with architecture defines
1539 from gas/config/tc-arm.c.
1541 2004-07-09 Andreas Schwab <schwab@suse.de>
1543 * m68k.h: Fix comment.
1545 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1549 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1551 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1553 2004-05-24 Peter Barada <peter@the-baradas.com>
1555 * m68k.h: Add 'size' to m68k_opcode.
1557 2004-05-05 Peter Barada <peter@the-baradas.com>
1559 * m68k.h: Switch from ColdFire chip name to core variant.
1561 2004-04-22 Peter Barada <peter@the-baradas.com>
1563 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1564 descriptions for new EMAC cases.
1565 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1566 handle Motorola MAC syntax.
1567 Allow disassembly of ColdFire V4e object files.
1569 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1571 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1573 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1575 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1577 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1579 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1581 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1583 * i386.h (i386_optab): Added xstore/xcrypt insns.
1585 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1587 * h8300.h (32bit ldc/stc): Add relaxing support.
1589 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1591 * h8300.h (BITOP): Pass MEMRELAX flag.
1593 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1595 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1598 For older changes see ChangeLog-9103
1600 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1602 Copying and distribution of this file, with or without modification,
1603 are permitted in any medium without royalty provided the copyright
1604 notice and this notice are preserved.
1610 version-control: never