include/opcode/ChangeLog

   1 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
   2             Vineet Sharma      <vineets@noida.hcltech.com>
   3
   4         * maxq.h: New file: Disassembly information for the maxq port.
   5
   6 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386.h (i386_optab): Put back "movzb".
   9
  10 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  11
  12         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  13         comments.  Remove member cris_ver_sim.  Add members
  14         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  15         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  16         (struct cris_support_reg, struct cris_cond15): New types.
  17         (cris_conds15): Declare.
  18         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  19         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  20         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  21         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  22         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  23         SIZE_FIELD_UNSIGNED.
  24
  25 2004-11-04 Jan Beulich <jbeulich@novell.com>
  26
  27         * i386.h (sldx_Suf): Remove.
  28         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  29         (q_FP): Define, implying no REX64.
  30         (x_FP, sl_FP): Imply FloatMF.
  31         (i386_optab): Split reg and mem forms of moving from segment registers
  32         so that the memory forms can ignore the 16-/32-bit operand size
  33         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  34         all non-floating-point instructions. Unite 32- and 64-bit forms of
  35         movsx, movzx, and movd. Adjust floating point operations for the above
  36         changes to the *FP macros. Add DefaultSize to floating point control
  37         insns operating on larger memory ranges. Remove left over comments
  38         hinting at certain insns being Intel-syntax ones where the ones
  39         actually meant are already gone.
  40
  41 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  42
  43         * crx.h: Add COPS_REG_INS - Coprocessor Special register
  44         instruction type.
  45
  46 2004-09-30  Paul Brook  <paul@codesourcery.com>
  47
  48         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
  49         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
  50
  51 2004-09-11  Theodore A. Roth  <troth@openavr.org>
  52
  53         * avr.h: Add support for
  54         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
  55
  56 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
  57
  58         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
  59
  60 2004-08-24  Dmitry Diky  <diwil@spec.ru>
  61
  62         * msp430.h (msp430_opc): Add new instructions.
  63         (msp430_rcodes): Declare new instructions.
  64         (msp430_hcodes): Likewise..
  65
  66 2004-08-13  Nick Clifton  <nickc@redhat.com>
  67
  68         PR/301
  69         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
  70         processors.
  71
  72 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
  73
  74         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
  75
  76 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
  79
  80 2004-07-21  Jan Beulich  <jbeulich@novell.com>
  81
  82         * i386.h: Adjust instruction descriptions to better match the
  83         specification.
  84
  85 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
  86
  87         * arm.h: Remove all old content.  Replace with architecture defines
  88         from gas/config/tc-arm.c.
  89
  90 2004-07-09  Andreas Schwab  <schwab@suse.de>
  91
  92         * m68k.h: Fix comment.
  93
  94 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  95
  96         * crx.h: New file.
  97
  98 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  99
 100         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 101
 102 2004-05-24  Peter Barada  <peter@the-baradas.com>
 103
 104         * m68k.h: Add 'size' to m68k_opcode.
 105
 106 2004-05-05  Peter Barada  <peter@the-baradas.com>
 107
 108         * m68k.h: Switch from ColdFire chip name to core variant.
 109
 110 2004-04-22  Peter Barada  <peter@the-baradas.com>
 111
 112         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 113         descriptions for new EMAC cases.
 114         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 115         handle Motorola MAC syntax.
 116         Allow disassembly of ColdFire V4e object files.
 117
 118 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 119
 120         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 121
 122 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 123
 124         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 125
 126 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 127
 128         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 129
 130 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 131
 132         * i386.h (i386_optab): Added xstore/xcrypt insns.
 133
 134 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 135
 136         * h8300.h (32bit ldc/stc): Add relaxing support.
 137
 138 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 139
 140         * h8300.h (BITOP): Pass MEMRELAX flag.
 141
 142 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 143
 144         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 145         except for the H8S.
 146
 147 For older changes see ChangeLog-9103
 148 \f
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