projects / deliverable / binutils-gdb.git / blob
? search:


9eed10498717d348cb43fdbd6c3d1ef9db8dee8a
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
1 2013-04-06 David S. Miller <davem@davemloft.net>
2
3 * sparc.h (F_PREFERRED): Define.
4 (F_PREF_ALIAS): Define.
5
6 2013-04-03 Nick Clifton <nickc@redhat.com>
7
8 * v850.h (V850_INVERSE_PCREL): Define.
9
10 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
11
12 PR binutils/15068
13 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
14
15 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
16
17 PR binutils/15068
18 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
19 Add 16-bit opcodes.
20 * tic6xc-opcode-table.h: Add 16-bit insns.
21 * tic6x.h: Add support for 16-bit insns.
22
23 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
24
25 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
26 and mov.b/w/l Rs,@(d:32,ERd).
27
28 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
29
30 PR gas/15082
31 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
32 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
33 tic6x_operand_xregpair operand coding type.
34 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
35 opcode field, usu ORXREGD1324 for the src2 operand and remove the
36 TIC6X_FLAG_NO_CROSS.
37
38 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
39
40 PR gas/15095
41 * tic6x.h (enum tic6x_coding_method): Add
42 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
43 separately the msb and lsb of a register pair. This is needed to
44 encode the opcodes in the same way as TI assembler does.
45 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
46 and rsqrdp opcodes to use the new field coding types.
47
48 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
49
50 * arm.h (CRC_EXT_ARMV8): New constant.
51 (ARCH_CRC_ARMV8): New macro.
52
53 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
54
55 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
56
57 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
58 Andrew Jenner <andrew@codesourcery.com>
59
60 Based on patches from Altera Corporation.
61
62 * nios2.h: New file.
63
64 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
65
66 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
67
68 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
69
70 PR gas/15069
71 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
72
73 2013-01-24 Nick Clifton <nickc@redhat.com>
74
75 * v850.h: Add e3v5 support.
76
77 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
78
79 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
80
81 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
82
83 * ppc.h (PPC_OPCODE_POWER8): New define.
84 (PPC_OPCODE_HTM): Likewise.
85
86 2013-01-10 Will Newton <will.newton@imgtec.com>
87
88 * metag.h: New file.
89
90 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
91
92 * cr16.h (make_instruction): Rename to cr16_make_instruction.
93 (match_opcode): Rename to cr16_match_opcode.
94
95 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
96
97 * mips.h: Add support for r5900 instructions including lq and sq.
98
99 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
100
101 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
102 (make_instruction,match_opcode): Added function prototypes.
103 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
104
105 2012-11-23 Alan Modra <amodra@gmail.com>
106
107 * ppc.h (ppc_parse_cpu): Update prototype.
108
109 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
110
111 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
112 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
113
114 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
115
116 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
117
118 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
119
120 * ia64.h (ia64_opnd): Add new operand types.
121
122 2012-08-21 David S. Miller <davem@davemloft.net>
123
124 * sparc.h (F3F4): New macro.
125
126 2012-08-13 Ian Bolton <ian.bolton@arm.com>
127 Laurent Desnogues <laurent.desnogues@arm.com>
128 Jim MacArthur <jim.macarthur@arm.com>
129 Marcus Shawcroft <marcus.shawcroft@arm.com>
130 Nigel Stephens <nigel.stephens@arm.com>
131 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
132 Richard Earnshaw <rearnsha@arm.com>
133 Sofiane Naci <sofiane.naci@arm.com>
134 Tejas Belagod <tejas.belagod@arm.com>
135 Yufeng Zhang <yufeng.zhang@arm.com>
136
137 * aarch64.h: New file.
138
139 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
140 Maciej W. Rozycki <macro@codesourcery.com>
141
142 * mips.h (mips_opcode): Add the exclusions field.
143 (OPCODE_IS_MEMBER): Remove macro.
144 (cpu_is_member): New inline function.
145 (opcode_is_member): Likewise.
146
147 2012-07-31 Chao-Ying Fu <fu@mips.com>
148 Catherine Moore <clm@codesourcery.com>
149 Maciej W. Rozycki <macro@codesourcery.com>
150
151 * mips.h: Document microMIPS DSP ASE usage.
152 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
153 microMIPS DSP ASE support.
154 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
155 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
156 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
157 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
158 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
159 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
160 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
161
162 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
163
164 * mips.h: Fix a typo in description.
165
166 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
167
168 * avr.h: (AVR_ISA_XCH): New define.
169 (AVR_ISA_XMEGA): Use it.
170 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
171
172 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
173
174 * m68hc11.h: Add XGate definitions.
175 (struct m68hc11_opcode): Add xg_mask field.
176
177 2012-05-14 Catherine Moore <clm@codesourcery.com>
178 Maciej W. Rozycki <macro@codesourcery.com>
179 Rhonda Wittels <rhonda@codesourcery.com>
180
181 * ppc.h (PPC_OPCODE_VLE): New definition.
182 (PPC_OP_SA): New macro.
183 (PPC_OP_SE_VLE): New macro.
184 (PPC_OP): Use a variable shift amount.
185 (powerpc_operand): Update comments.
186 (PPC_OPSHIFT_INV): New macro.
187 (PPC_OPERAND_CR): Replace with...
188 (PPC_OPERAND_CR_BIT): ...this and
189 (PPC_OPERAND_CR_REG): ...this.
190
191
192 2012-05-03 Sean Keys <skeys@ipdatasys.com>
193
194 * xgate.h: Header file for XGATE assembler.
195
196 2012-04-27 David S. Miller <davem@davemloft.net>
197
198 * sparc.h: Document new arg code' )' for crypto RS3
199 immediates.
200
201 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
202 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
203 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
204 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
205 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
206 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
207 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
208 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
209 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
210 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
211 HWCAP_CBCOND, HWCAP_CRC32): New defines.
212
213 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
214
215 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
216
217 2012-02-27 Alan Modra <amodra@gmail.com>
218
219 * crx.h (cst4_map): Update declaration.
220
221 2012-02-25 Walter Lee <walt@tilera.com>
222
223 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
224 TILEGX_OPC_LD_TLS.
225 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
226 TILEPRO_OPC_LW_TLS_SN.
227
228 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
231 (XRELEASE_PREFIX_OPCODE): Likewise.
232
233 2011-12-08 Andrew Pinski <apinski@cavium.com>
234 Adam Nemet <anemet@caviumnetworks.com>
235
236 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
237 (INSN_OCTEON2): New macro.
238 (CPU_OCTEON2): New macro.
239 (OPCODE_IS_MEMBER): Add Octeon2.
240
241 2011-11-29 Andrew Pinski <apinski@cavium.com>
242
243 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
244 (INSN_OCTEONP): New macro.
245 (CPU_OCTEONP): New macro.
246 (OPCODE_IS_MEMBER): Add Octeon+.
247 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
248
249 2011-11-01 DJ Delorie <dj@redhat.com>
250
251 * rl78.h: New file.
252
253 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
254
255 * mips.h: Fix a typo in description.
256
257 2011-09-21 David S. Miller <davem@davemloft.net>
258
259 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
260 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
261 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
262 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
263
264 2011-08-09 Chao-ying Fu <fu@mips.com>
265 Maciej W. Rozycki <macro@codesourcery.com>
266
267 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
268 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
269 (INSN_ASE_MASK): Add the MCU bit.
270 (INSN_MCU): New macro.
271 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
272 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
273
274 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
275
276 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
277 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
278 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
279 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
280 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
281 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
282 (INSN2_READ_GPR_MMN): Likewise.
283 (INSN2_READ_FPR_D): Change the bit used.
284 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
285 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
286 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
287 (INSN2_COND_BRANCH): Likewise.
288 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
289 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
290 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
291 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
292 (INSN2_MOD_GPR_MN): Likewise.
293
294 2011-08-05 David S. Miller <davem@davemloft.net>
295
296 * sparc.h: Document new format codes '4', '5', and '('.
297 (OPF_LOW4, RS3): New macros.
298
299 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
300
301 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
302 order of flags documented.
303
304 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
305
306 * mips.h: Clarify the description of microMIPS instruction
307 manipulation macros.
308 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
309
310 2011-07-24 Chao-ying Fu <fu@mips.com>
311 Maciej W. Rozycki <macro@codesourcery.com>
312
313 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
314 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
315 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
316 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
317 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
318 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
319 (OP_MASK_RS3, OP_SH_RS3): Likewise.
320 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
321 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
322 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
323 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
324 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
325 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
326 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
327 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
328 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
329 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
330 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
331 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
332 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
333 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
334 (INSN_WRITE_GPR_S): New macro.
335 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
336 (INSN2_READ_FPR_D): Likewise.
337 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
338 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
339 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
340 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
341 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
342 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
343 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
344 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
345 (CPU_MICROMIPS): New macro.
346 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
347 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
348 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
349 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
350 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
351 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
352 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
353 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
354 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
355 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
356 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
357 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
358 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
359 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
360 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
361 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
362 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
363 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
364 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
365 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
366 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
367 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
368 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
369 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
370 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
371 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
372 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
373 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
374 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
375 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
376 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
377 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
378 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
379 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
380 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
381 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
382 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
383 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
384 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
385 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
386 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
387 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
388 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
389 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
390 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
391 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
392 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
393 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
394 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
395 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
396 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
397 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
398 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
399 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
400 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
401 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
402 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
403 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
404 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
405 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
406 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
407 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
408 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
409 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
410 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
411 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
412 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
413 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
414 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
415 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
416 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
417 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
418 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
419 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
420 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
421 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
422 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
423 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
424 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
425 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
426 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
427 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
428 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
429 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
430 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
431 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
432 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
433 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
434 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
435 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
436 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
437 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
438 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
439 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
440 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
441 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
442 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
443 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
444 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
445 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
446 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
447 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
448 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
449 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
450 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
451 (micromips_opcodes): New declaration.
452 (bfd_micromips_num_opcodes): Likewise.
453
454 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
455
456 * mips.h (INSN_TRAP): Rename to...
457 (INSN_NO_DELAY_SLOT): ... this.
458 (INSN_SYNC): Remove macro.
459
460 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
461
462 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
463 a duplicate of AVR_ISA_SPM.
464
465 2011-07-01 Nick Clifton <nickc@redhat.com>
466
467 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
468
469 2011-06-18 Robin Getz <robin.getz@analog.com>
470
471 * bfin.h (is_macmod_signed): New func
472
473 2011-06-18 Mike Frysinger <vapier@gentoo.org>
474
475 * bfin.h (is_macmod_pmove): Add missing space before func args.
476 (is_macmod_hmove): Likewise.
477
478 2011-06-13 Walter Lee <walt@tilera.com>
479
480 * tilegx.h: New file.
481 * tilepro.h: New file.
482
483 2011-05-31 Paul Brook <paul@codesourcery.com>
484
485 * arm.h (ARM_ARCH_V7R_IDIV): Define.
486
487 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
488
489 * s390.h: Replace S390_OPERAND_REG_EVEN with
490 S390_OPERAND_REG_PAIR.
491
492 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
493
494 * s390.h: Add S390_OPCODE_REG_EVEN flag.
495
496 2011-04-18 Julian Brown <julian@codesourcery.com>
497
498 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
499
500 2011-04-11 Dan McDonald <dan@wellkeeper.com>
501
502 PR gas/12296
503 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
504
505 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
506
507 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
508 New instruction set flags.
509 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
510
511 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
512
513 * mips.h (M_PREF_AB): New enum value.
514
515 2011-02-12 Mike Frysinger <vapier@gentoo.org>
516
517 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
518 M_IU): Define.
519 (is_macmod_pmove, is_macmod_hmove): New functions.
520
521 2011-02-11 Mike Frysinger <vapier@gentoo.org>
522
523 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
524
525 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
526
527 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
528 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
529
530 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
531
532 PR gas/11395
533 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
534 "bb" entries.
535
536 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
537
538 PR gas/11395
539 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
540
541 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
542
543 * mips.h: Update commentary after last commit.
544
545 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
546
547 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
548 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
549 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
550
551 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
552
553 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
554
555 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
556
557 * mips.h: Fix previous commit.
558
559 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
560
561 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
562 (INSN_LOONGSON_3A): Clear bit 31.
563
564 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
565
566 PR gas/12198
567 * arm.h (ARM_AEXT_V6M_ONLY): New define.
568 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
569 (ARM_ARCH_V6M_ONLY): New define.
570
571 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
572
573 * mips.h (INSN_LOONGSON_3A): Defined.
574 (CPU_LOONGSON_3A): Defined.
575 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
576
577 2010-10-09 Matt Rice <ratmice@gmail.com>
578
579 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
580 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
581
582 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
583
584 * arm.h (ARM_EXT_VIRT): New define.
585 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
586 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
587 Extensions.
588
589 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
590
591 * arm.h (ARM_AEXT_ADIV): New define.
592 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
593
594 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
595
596 * arm.h (ARM_EXT_OS): New define.
597 (ARM_AEXT_V6SM): Likewise.
598 (ARM_ARCH_V6SM): Likewise.
599
600 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
601
602 * arm.h (ARM_EXT_MP): Add.
603 (ARM_ARCH_V7A_MP): Likewise.
604
605 2010-09-22 Mike Frysinger <vapier@gentoo.org>
606
607 * bfin.h: Declare pseudoChr structs/defines.
608
609 2010-09-21 Mike Frysinger <vapier@gentoo.org>
610
611 * bfin.h: Strip trailing whitespace.
612
613 2010-07-29 DJ Delorie <dj@redhat.com>
614
615 * rx.h (RX_Operand_Type): Add TwoReg.
616 (RX_Opcode_ID): Remove ediv and ediv2.
617
618 2010-07-27 DJ Delorie <dj@redhat.com>
619
620 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
621
622 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
623 Ina Pandit <ina.pandit@kpitcummins.com>
624
625 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
626 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
627 PROCESSOR_V850E2_ALL.
628 Remove PROCESSOR_V850EA support.
629 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
630 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
631 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
632 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
633 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
634 V850_OPERAND_PERCENT.
635 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
636 V850_NOT_R0.
637 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
638 and V850E_PUSH_POP
639
640 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
641
642 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
643 (MIPS16_INSN_BRANCH): Rename to...
644 (MIPS16_INSN_COND_BRANCH): ... this.
645
646 2010-07-03 Alan Modra <amodra@gmail.com>
647
648 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
649 Renumber other PPC_OPCODE defines.
650
651 2010-07-03 Alan Modra <amodra@gmail.com>
652
653 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
654
655 2010-06-29 Alan Modra <amodra@gmail.com>
656
657 * maxq.h: Delete file.
658
659 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
660
661 * ppc.h (PPC_OPCODE_E500): Define.
662
663 2010-05-26 Catherine Moore <clm@codesourcery.com>
664
665 * opcode/mips.h (INSN_MIPS16): Remove.
666
667 2010-04-21 Joseph Myers <joseph@codesourcery.com>
668
669 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
670
671 2010-04-15 Nick Clifton <nickc@redhat.com>
672
673 * alpha.h: Update copyright notice to use GPLv3.
674 * arc.h: Likewise.
675 * arm.h: Likewise.
676 * avr.h: Likewise.
677 * bfin.h: Likewise.
678 * cgen.h: Likewise.
679 * convex.h: Likewise.
680 * cr16.h: Likewise.
681 * cris.h: Likewise.
682 * crx.h: Likewise.
683 * d10v.h: Likewise.
684 * d30v.h: Likewise.
685 * dlx.h: Likewise.
686 * h8300.h: Likewise.
687 * hppa.h: Likewise.
688 * i370.h: Likewise.
689 * i386.h: Likewise.
690 * i860.h: Likewise.
691 * i960.h: Likewise.
692 * ia64.h: Likewise.
693 * m68hc11.h: Likewise.
694 * m68k.h: Likewise.
695 * m88k.h: Likewise.
696 * maxq.h: Likewise.
697 * mips.h: Likewise.
698 * mmix.h: Likewise.
699 * mn10200.h: Likewise.
700 * mn10300.h: Likewise.
701 * msp430.h: Likewise.
702 * np1.h: Likewise.
703 * ns32k.h: Likewise.
704 * or32.h: Likewise.
705 * pdp11.h: Likewise.
706 * pj.h: Likewise.
707 * pn.h: Likewise.
708 * ppc.h: Likewise.
709 * pyr.h: Likewise.
710 * rx.h: Likewise.
711 * s390.h: Likewise.
712 * score-datadep.h: Likewise.
713 * score-inst.h: Likewise.
714 * sparc.h: Likewise.
715 * spu-insns.h: Likewise.
716 * spu.h: Likewise.
717 * tic30.h: Likewise.
718 * tic4x.h: Likewise.
719 * tic54x.h: Likewise.
720 * tic80.h: Likewise.
721 * v850.h: Likewise.
722 * vax.h: Likewise.
723
724 2010-03-25 Joseph Myers <joseph@codesourcery.com>
725
726 * tic6x-control-registers.h, tic6x-insn-formats.h,
727 tic6x-opcode-table.h, tic6x.h: New.
728
729 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
730
731 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
732
733 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
734
735 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
736
737 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
738
739 * ia64.h (ia64_find_opcode): Remove argument name.
740 (ia64_find_next_opcode): Likewise.
741 (ia64_dis_opcode): Likewise.
742 (ia64_free_opcode): Likewise.
743 (ia64_find_dependency): Likewise.
744
745 2009-11-22 Doug Evans <dje@sebabeach.org>
746
747 * cgen.h: Include bfd_stdint.h.
748 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
749
750 2009-11-18 Paul Brook <paul@codesourcery.com>
751
752 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
753
754 2009-11-17 Paul Brook <paul@codesourcery.com>
755 Daniel Jacobowitz <dan@codesourcery.com>
756
757 * arm.h (ARM_EXT_V6_DSP): Define.
758 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
759 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
760
761 2009-11-04 DJ Delorie <dj@redhat.com>
762
763 * rx.h (rx_decode_opcode) (mvtipl): Add.
764 (mvtcp, mvfcp, opecp): Remove.
765
766 2009-11-02 Paul Brook <paul@codesourcery.com>
767
768 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
769 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
770 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
771 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
772 FPU_ARCH_NEON_VFP_V4): Define.
773
774 2009-10-23 Doug Evans <dje@sebabeach.org>
775
776 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
777 * cgen.h: Update. Improve multi-inclusion macro name.
778
779 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
780
781 * ppc.h (PPC_OPCODE_476): Define.
782
783 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
784
785 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
786
787 2009-09-29 DJ Delorie <dj@redhat.com>
788
789 * rx.h: New file.
790
791 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
792
793 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
794
795 2009-09-21 Ben Elliston <bje@au.ibm.com>
796
797 * ppc.h (PPC_OPCODE_PPCA2): New.
798
799 2009-09-05 Martin Thuresson <martin@mtme.org>
800
801 * ia64.h (struct ia64_operand): Renamed member class to op_class.
802
803 2009-08-29 Martin Thuresson <martin@mtme.org>
804
805 * tic30.h (template): Rename type template to
806 insn_template. Updated code to use new name.
807 * tic54x.h (template): Rename type template to
808 insn_template.
809
810 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
811
812 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
813
814 2009-06-11 Anthony Green <green@moxielogic.com>
815
816 * moxie.h (MOXIE_F3_PCREL): Define.
817 (moxie_form3_opc_info): Grow.
818
819 2009-06-06 Anthony Green <green@moxielogic.com>
820
821 * moxie.h (MOXIE_F1_M): Define.
822
823 2009-04-15 Anthony Green <green@moxielogic.com>
824
825 * moxie.h: Created.
826
827 2009-04-06 DJ Delorie <dj@redhat.com>
828
829 * h8300.h: Add relaxation attributes to MOVA opcodes.
830
831 2009-03-10 Alan Modra <amodra@bigpond.net.au>
832
833 * ppc.h (ppc_parse_cpu): Declare.
834
835 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
836
837 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
838 and _IMM11 for mbitclr and mbitset.
839 * score-datadep.h: Update dependency information.
840
841 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
842
843 * ppc.h (PPC_OPCODE_POWER7): New.
844
845 2009-02-06 Doug Evans <dje@google.com>
846
847 * i386.h: Add comment regarding sse* insns and prefixes.
848
849 2009-02-03 Sandip Matte <sandip@rmicorp.com>
850
851 * mips.h (INSN_XLR): Define.
852 (INSN_CHIP_MASK): Update.
853 (CPU_XLR): Define.
854 (OPCODE_IS_MEMBER): Update.
855 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
856
857 2009-01-28 Doug Evans <dje@google.com>
858
859 * opcode/i386.h: Add multiple inclusion protection.
860 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
861 (EDI_REG_NUM): New macros.
862 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
863 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
864 (REX_PREFIX_P): New macro.
865
866 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
867
868 * ppc.h (struct powerpc_opcode): New field "deprecated".
869 (PPC_OPCODE_NOPOWER4): Delete.
870
871 2008-11-28 Joshua Kinard <kumba@gentoo.org>
872
873 * mips.h: Define CPU_R14000, CPU_R16000.
874 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
875
876 2008-11-18 Catherine Moore <clm@codesourcery.com>
877
878 * arm.h (FPU_NEON_FP16): New.
879 (FPU_ARCH_NEON_FP16): New.
880
881 2008-11-06 Chao-ying Fu <fu@mips.com>
882
883 * mips.h: Doucument '1' for 5-bit sync type.
884
885 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
886
887 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
888 IA64_RS_CR.
889
890 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
891
892 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
893
894 2008-07-30 Michael J. Eager <eager@eagercon.com>
895
896 * ppc.h (PPC_OPCODE_405): Define.
897 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
898
899 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
900
901 * ppc.h (ppc_cpu_t): New typedef.
902 (struct powerpc_opcode <flags>): Use it.
903 (struct powerpc_operand <insert, extract>): Likewise.
904 (struct powerpc_macro <flags>): Likewise.
905
906 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
907
908 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
909 Update comment before MIPS16 field descriptors to mention MIPS16.
910 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
911 BBIT.
912 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
913 New bit masks and shift counts for cins and exts.
914
915 * mips.h: Document new field descriptors +Q.
916 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
917
918 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
919
920 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
921 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
922
923 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
924
925 * ppc.h: (PPC_OPCODE_E500MC): New.
926
927 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
928
929 * i386.h (MAX_OPERANDS): Set to 5.
930 (MAX_MNEM_SIZE): Changed to 20.
931
932 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
933
934 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
935
936 2008-03-09 Paul Brook <paul@codesourcery.com>
937
938 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
939
940 2008-03-04 Paul Brook <paul@codesourcery.com>
941
942 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
943 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
944 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
945
946 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
947 Nick Clifton <nickc@redhat.com>
948
949 PR 3134
950 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
951 with a 32-bit displacement but without the top bit of the 4th byte
952 set.
953
954 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
955
956 * cr16.h (cr16_num_optab): Declared.
957
958 2008-02-14 Hakan Ardo <hakan@debian.org>
959
960 PR gas/2626
961 * avr.h (AVR_ISA_2xxe): Define.
962
963 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
964
965 * mips.h: Update copyright.
966 (INSN_CHIP_MASK): New macro.
967 (INSN_OCTEON): New macro.
968 (CPU_OCTEON): New macro.
969 (OPCODE_IS_MEMBER): Handle Octeon instructions.
970
971 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
972
973 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
974
975 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
976
977 * avr.h (AVR_ISA_USB162): Add new opcode set.
978 (AVR_ISA_AVR3): Likewise.
979
980 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
981
982 * mips.h (INSN_LOONGSON_2E): New.
983 (INSN_LOONGSON_2F): New.
984 (CPU_LOONGSON_2E): New.
985 (CPU_LOONGSON_2F): New.
986 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
987
988 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
989
990 * mips.h (INSN_ISA*): Redefine certain values as an
991 enumeration. Update comments.
992 (mips_isa_table): New.
993 (ISA_MIPS*): Redefine to match enumeration.
994 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
995 values.
996
997 2007-08-08 Ben Elliston <bje@au.ibm.com>
998
999 * ppc.h (PPC_OPCODE_PPCPS): New.
1000
1001 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1002
1003 * m68k.h: Document j K & E.
1004
1005 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1006
1007 * cr16.h: New file for CR16 target.
1008
1009 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1010
1011 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1012
1013 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1014
1015 * m68k.h (mcfisa_c): New.
1016 (mcfusp, mcf_mask): Adjust.
1017
1018 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1019
1020 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1021 (num_powerpc_operands): Declare.
1022 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1023 (PPC_OPERAND_PLUS1): Define.
1024
1025 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1026
1027 * i386.h (REX_MODE64): Renamed to ...
1028 (REX_W): This.
1029 (REX_EXTX): Renamed to ...
1030 (REX_R): This.
1031 (REX_EXTY): Renamed to ...
1032 (REX_X): This.
1033 (REX_EXTZ): Renamed to ...
1034 (REX_B): This.
1035
1036 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1037
1038 * i386.h: Add entries from config/tc-i386.h and move tables
1039 to opcodes/i386-opc.h.
1040
1041 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1042
1043 * i386.h (FloatDR): Removed.
1044 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1045
1046 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1047
1048 * spu-insns.h: Add soma double-float insns.
1049
1050 2007-02-20 Thiemo Seufer <ths@mips.com>
1051 Chao-Ying Fu <fu@mips.com>
1052
1053 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1054 (INSN_DSPR2): Add flag for DSP R2 instructions.
1055 (M_BALIGN): New macro.
1056
1057 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1058
1059 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1060 and Seg3ShortFrom with Shortform.
1061
1062 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1063
1064 PR gas/4027
1065 * i386.h (i386_optab): Put the real "test" before the pseudo
1066 one.
1067
1068 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1069
1070 * m68k.h (m68010up): OR fido_a.
1071
1072 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1073
1074 * m68k.h (fido_a): New.
1075
1076 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1077
1078 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1079 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1080 values.
1081
1082 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1083
1084 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1085
1086 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1087
1088 * score-inst.h (enum score_insn_type): Add Insn_internal.
1089
1090 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1091 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1092 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1093 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1094 Alan Modra <amodra@bigpond.net.au>
1095
1096 * spu-insns.h: New file.
1097 * spu.h: New file.
1098
1099 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1100
1101 * ppc.h (PPC_OPCODE_CELL): Define.
1102
1103 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1104
1105 * i386.h : Modify opcode to support for the change in POPCNT opcode
1106 in amdfam10 architecture.
1107
1108 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1109
1110 * i386.h: Replace CpuMNI with CpuSSSE3.
1111
1112 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1113 Joseph Myers <joseph@codesourcery.com>
1114 Ian Lance Taylor <ian@wasabisystems.com>
1115 Ben Elliston <bje@wasabisystems.com>
1116
1117 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1118
1119 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1120
1121 * score-datadep.h: New file.
1122 * score-inst.h: New file.
1123
1124 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1125
1126 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1127 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1128 movdq2q and movq2dq.
1129
1130 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1131 Michael Meissner <michael.meissner@amd.com>
1132
1133 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1134
1135 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 * i386.h (i386_optab): Add "nop" with memory reference.
1138
1139 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1140
1141 * i386.h (i386_optab): Update comment for 64bit NOP.
1142
1143 2006-06-06 Ben Elliston <bje@au.ibm.com>
1144 Anton Blanchard <anton@samba.org>
1145
1146 * ppc.h (PPC_OPCODE_POWER6): Define.
1147 Adjust whitespace.
1148
1149 2006-06-05 Thiemo Seufer <ths@mips.com>
1150
1151 * mips.h: Improve description of MT flags.
1152
1153 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1154
1155 * m68k.h (mcf_mask): Define.
1156
1157 2006-05-05 Thiemo Seufer <ths@mips.com>
1158 David Ung <davidu@mips.com>
1159
1160 * mips.h (enum): Add macro M_CACHE_AB.
1161
1162 2006-05-04 Thiemo Seufer <ths@mips.com>
1163 Nigel Stephens <nigel@mips.com>
1164 David Ung <davidu@mips.com>
1165
1166 * mips.h: Add INSN_SMARTMIPS define.
1167
1168 2006-04-30 Thiemo Seufer <ths@mips.com>
1169 David Ung <davidu@mips.com>
1170
1171 * mips.h: Defines udi bits and masks. Add description of
1172 characters which may appear in the args field of udi
1173 instructions.
1174
1175 2006-04-26 Thiemo Seufer <ths@networkno.de>
1176
1177 * mips.h: Improve comments describing the bitfield instruction
1178 fields.
1179
1180 2006-04-26 Julian Brown <julian@codesourcery.com>
1181
1182 * arm.h (FPU_VFP_EXT_V3): Define constant.
1183 (FPU_NEON_EXT_V1): Likewise.
1184 (FPU_VFP_HARD): Update.
1185 (FPU_VFP_V3): Define macro.
1186 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1187
1188 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1189
1190 * avr.h (AVR_ISA_PWMx): New.
1191
1192 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1193
1194 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1195 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1196 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1197 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1198 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1199
1200 2006-03-10 Paul Brook <paul@codesourcery.com>
1201
1202 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1203
1204 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1205
1206 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1207 first. Correct mask of bb "B" opcode.
1208
1209 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1210
1211 * i386.h (i386_optab): Support Intel Merom New Instructions.
1212
1213 2006-02-24 Paul Brook <paul@codesourcery.com>
1214
1215 * arm.h: Add V7 feature bits.
1216
1217 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1218
1219 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1220
1221 2006-01-31 Paul Brook <paul@codesourcery.com>
1222 Richard Earnshaw <rearnsha@arm.com>
1223
1224 * arm.h: Use ARM_CPU_FEATURE.
1225 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1226 (arm_feature_set): Change to a structure.
1227 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1228 ARM_FEATURE): New macros.
1229
1230 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1231
1232 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1233 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1234 (ADD_PC_INCR_OPCODE): Don't define.
1235
1236 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1237
1238 PR gas/1874
1239 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1240
1241 2005-11-14 David Ung <davidu@mips.com>
1242
1243 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1244 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1245 save/restore encoding of the args field.
1246
1247 2005-10-28 Dave Brolley <brolley@redhat.com>
1248
1249 Contribute the following changes:
1250 2005-02-16 Dave Brolley <brolley@redhat.com>
1251
1252 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1253 cgen_isa_mask_* to cgen_bitset_*.
1254 * cgen.h: Likewise.
1255
1256 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1257
1258 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1259 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1260 (CGEN_CPU_TABLE): Make isas a ponter.
1261
1262 2003-09-29 Dave Brolley <brolley@redhat.com>
1263
1264 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1265 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1266 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1267
1268 2002-12-13 Dave Brolley <brolley@redhat.com>
1269
1270 * cgen.h (symcat.h): #include it.
1271 (cgen-bitset.h): #include it.
1272 (CGEN_ATTR_VALUE_TYPE): Now a union.
1273 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1274 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1275 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1276 * cgen-bitset.h: New file.
1277
1278 2005-09-30 Catherine Moore <clm@cm00re.com>
1279
1280 * bfin.h: New file.
1281
1282 2005-10-24 Jan Beulich <jbeulich@novell.com>
1283
1284 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1285 indirect operands.
1286
1287 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1288
1289 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1290 Add FLAG_STRICT to pa10 ftest opcode.
1291
1292 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1293
1294 * hppa.h (pa_opcodes): Remove lha entries.
1295
1296 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1297
1298 * hppa.h (FLAG_STRICT): Revise comment.
1299 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1300 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1301 entries for "fdc".
1302
1303 2005-09-30 Catherine Moore <clm@cm00re.com>
1304
1305 * bfin.h: New file.
1306
1307 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1308
1309 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1310
1311 2005-09-06 Chao-ying Fu <fu@mips.com>
1312
1313 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1314 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1315 define.
1316 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1317 (INSN_ASE_MASK): Update to include INSN_MT.
1318 (INSN_MT): New define for MT ASE.
1319
1320 2005-08-25 Chao-ying Fu <fu@mips.com>
1321
1322 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1323 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1324 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1325 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1326 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1327 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1328 instructions.
1329 (INSN_DSP): New define for DSP ASE.
1330
1331 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1332
1333 * a29k.h: Delete.
1334
1335 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1336
1337 * ppc.h (PPC_OPCODE_E300): Define.
1338
1339 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1340
1341 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1342
1343 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1344
1345 PR gas/336
1346 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1347 and pitlb.
1348
1349 2005-07-27 Jan Beulich <jbeulich@novell.com>
1350
1351 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1352 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1353 Add movq-s as 64-bit variants of movd-s.
1354
1355 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1356
1357 * hppa.h: Fix punctuation in comment.
1358
1359 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1360 implicit space-register addressing. Set space-register bits on opcodes
1361 using implicit space-register addressing. Add various missing pa20
1362 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1363 space-register addressing. Use "fE" instead of "fe" in various
1364 fstw opcodes.
1365
1366 2005-07-18 Jan Beulich <jbeulich@novell.com>
1367
1368 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1369
1370 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1371
1372 * i386.h (i386_optab): Support Intel VMX Instructions.
1373
1374 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1375
1376 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1377
1378 2005-07-05 Jan Beulich <jbeulich@novell.com>
1379
1380 * i386.h (i386_optab): Add new insns.
1381
1382 2005-07-01 Nick Clifton <nickc@redhat.com>
1383
1384 * sparc.h: Add typedefs to structure declarations.
1385
1386 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1387
1388 PR 1013
1389 * i386.h (i386_optab): Update comments for 64bit addressing on
1390 mov. Allow 64bit addressing for mov and movq.
1391
1392 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1393
1394 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1395 respectively, in various floating-point load and store patterns.
1396
1397 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1398
1399 * hppa.h (FLAG_STRICT): Correct comment.
1400 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1401 PA 2.0 mneumonics when equivalent. Entries with cache control
1402 completers now require PA 1.1. Adjust whitespace.
1403
1404 2005-05-19 Anton Blanchard <anton@samba.org>
1405
1406 * ppc.h (PPC_OPCODE_POWER5): Define.
1407
1408 2005-05-10 Nick Clifton <nickc@redhat.com>
1409
1410 * Update the address and phone number of the FSF organization in
1411 the GPL notices in the following files:
1412 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1413 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1414 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1415 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1416 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1417 tic54x.h, tic80.h, v850.h, vax.h
1418
1419 2005-05-09 Jan Beulich <jbeulich@novell.com>
1420
1421 * i386.h (i386_optab): Add ht and hnt.
1422
1423 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1424
1425 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1426 Add xcrypt-ctr. Provide aliases without hyphens.
1427
1428 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1429
1430 Moved from ../ChangeLog
1431
1432 2005-04-12 Paul Brook <paul@codesourcery.com>
1433 * m88k.h: Rename psr macros to avoid conflicts.
1434
1435 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1436 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1437 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1438 and ARM_ARCH_V6ZKT2.
1439
1440 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1441 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1442 Remove redundant instruction types.
1443 (struct argument): X_op - new field.
1444 (struct cst4_entry): Remove.
1445 (no_op_insn): Declare.
1446
1447 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1448 * crx.h (enum argtype): Rename types, remove unused types.
1449
1450 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1451 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1452 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1453 (enum operand_type): Rearrange operands, edit comments.
1454 replace us<N> with ui<N> for unsigned immediate.
1455 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1456 displacements (respectively).
1457 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1458 (instruction type): Add NO_TYPE_INS.
1459 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1460 (operand_entry): New field - 'flags'.
1461 (operand flags): New.
1462
1463 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1464 * crx.h (operand_type): Remove redundant types i3, i4,
1465 i5, i8, i12.
1466 Add new unsigned immediate types us3, us4, us5, us16.
1467
1468 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1469
1470 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1471 adjust them accordingly.
1472
1473 2005-04-01 Jan Beulich <jbeulich@novell.com>
1474
1475 * i386.h (i386_optab): Add rdtscp.
1476
1477 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1478
1479 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1480 between memory and segment register. Allow movq for moving between
1481 general-purpose register and segment register.
1482
1483 2005-02-09 Jan Beulich <jbeulich@novell.com>
1484
1485 PR gas/707
1486 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1487 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1488 fnstsw.
1489
1490 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1491
1492 * m68k.h (m68008, m68ec030, m68882): Remove.
1493 (m68k_mask): New.
1494 (cpu_m68k, cpu_cf): New.
1495 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1496 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1497
1498 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1499
1500 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1501 * cgen.h (enum cgen_parse_operand_type): Add
1502 CGEN_PARSE_OPERAND_SYMBOLIC.
1503
1504 2005-01-21 Fred Fish <fnf@specifixinc.com>
1505
1506 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1507 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1508 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1509
1510 2005-01-19 Fred Fish <fnf@specifixinc.com>
1511
1512 * mips.h (struct mips_opcode): Add new pinfo2 member.
1513 (INSN_ALIAS): New define for opcode table entries that are
1514 specific instances of another entry, such as 'move' for an 'or'
1515 with a zero operand.
1516 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1517 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1518
1519 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1520
1521 * mips.h (CPU_RM9000): Define.
1522 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1523
1524 2004-11-25 Jan Beulich <jbeulich@novell.com>
1525
1526 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1527 to/from test registers are illegal in 64-bit mode. Add missing
1528 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1529 (previously one had to explicitly encode a rex64 prefix). Re-enable
1530 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1531 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1532
1533 2004-11-23 Jan Beulich <jbeulich@novell.com>
1534
1535 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1536 available only with SSE2. Change the MMX additions introduced by SSE
1537 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1538 instructions by their now designated identifier (since combining i686
1539 and 3DNow! does not really imply 3DNow!A).
1540
1541 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1542
1543 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1544 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1545
1546 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1547 Vineet Sharma <vineets@noida.hcltech.com>
1548
1549 * maxq.h: New file: Disassembly information for the maxq port.
1550
1551 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1552
1553 * i386.h (i386_optab): Put back "movzb".
1554
1555 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1556
1557 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1558 comments. Remove member cris_ver_sim. Add members
1559 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1560 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1561 (struct cris_support_reg, struct cris_cond15): New types.
1562 (cris_conds15): Declare.
1563 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1564 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1565 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1566 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1567 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1568 SIZE_FIELD_UNSIGNED.
1569
1570 2004-11-04 Jan Beulich <jbeulich@novell.com>
1571
1572 * i386.h (sldx_Suf): Remove.
1573 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1574 (q_FP): Define, implying no REX64.
1575 (x_FP, sl_FP): Imply FloatMF.
1576 (i386_optab): Split reg and mem forms of moving from segment registers
1577 so that the memory forms can ignore the 16-/32-bit operand size
1578 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1579 all non-floating-point instructions. Unite 32- and 64-bit forms of
1580 movsx, movzx, and movd. Adjust floating point operations for the above
1581 changes to the *FP macros. Add DefaultSize to floating point control
1582 insns operating on larger memory ranges. Remove left over comments
1583 hinting at certain insns being Intel-syntax ones where the ones
1584 actually meant are already gone.
1585
1586 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1587
1588 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1589 instruction type.
1590
1591 2004-09-30 Paul Brook <paul@codesourcery.com>
1592
1593 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1594 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1595
1596 2004-09-11 Theodore A. Roth <troth@openavr.org>
1597
1598 * avr.h: Add support for
1599 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1600
1601 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1602
1603 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1604
1605 2004-08-24 Dmitry Diky <diwil@spec.ru>
1606
1607 * msp430.h (msp430_opc): Add new instructions.
1608 (msp430_rcodes): Declare new instructions.
1609 (msp430_hcodes): Likewise..
1610
1611 2004-08-13 Nick Clifton <nickc@redhat.com>
1612
1613 PR/301
1614 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1615 processors.
1616
1617 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1618
1619 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1620
1621 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1622
1623 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1624
1625 2004-07-21 Jan Beulich <jbeulich@novell.com>
1626
1627 * i386.h: Adjust instruction descriptions to better match the
1628 specification.
1629
1630 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1631
1632 * arm.h: Remove all old content. Replace with architecture defines
1633 from gas/config/tc-arm.c.
1634
1635 2004-07-09 Andreas Schwab <schwab@suse.de>
1636
1637 * m68k.h: Fix comment.
1638
1639 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1640
1641 * crx.h: New file.
1642
1643 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1644
1645 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1646
1647 2004-05-24 Peter Barada <peter@the-baradas.com>
1648
1649 * m68k.h: Add 'size' to m68k_opcode.
1650
1651 2004-05-05 Peter Barada <peter@the-baradas.com>
1652
1653 * m68k.h: Switch from ColdFire chip name to core variant.
1654
1655 2004-04-22 Peter Barada <peter@the-baradas.com>
1656
1657 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1658 descriptions for new EMAC cases.
1659 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1660 handle Motorola MAC syntax.
1661 Allow disassembly of ColdFire V4e object files.
1662
1663 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1664
1665 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1666
1667 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1668
1669 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1670
1671 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1672
1673 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1674
1675 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1676
1677 * i386.h (i386_optab): Added xstore/xcrypt insns.
1678
1679 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1680
1681 * h8300.h (32bit ldc/stc): Add relaxing support.
1682
1683 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1684
1685 * h8300.h (BITOP): Pass MEMRELAX flag.
1686
1687 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1688
1689 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1690 except for the H8S.
1691
1692 For older changes see ChangeLog-9103
1693 \f
1694 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1695
1696 Copying and distribution of this file, with or without modification,
1697 are permitted in any medium without royalty provided the copyright
1698 notice and this notice are preserved.
1699
1700 Local Variables:
1701 mode: change-log
1702 left-margin: 8
1703 fill-column: 74
1704 version-control: never
1705 End:
GDB Binutils - Deliverables
This page took 0.085771 seconds and 3 git commands to generate.