1 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h: Fix a typo in description.
5 2011-09-21 David S. Miller <davem@davemloft.net>
7 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
8 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
9 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
10 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
12 2011-08-09 Chao-ying Fu <fu@mips.com>
13 Maciej W. Rozycki <macro@codesourcery.com>
15 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
16 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
17 (INSN_ASE_MASK): Add the MCU bit.
18 (INSN_MCU): New macro.
19 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
20 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
22 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
24 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
25 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
26 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
27 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
28 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
29 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
30 (INSN2_READ_GPR_MMN): Likewise.
31 (INSN2_READ_FPR_D): Change the bit used.
32 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
33 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
34 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
35 (INSN2_COND_BRANCH): Likewise.
36 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
37 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
38 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
39 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
40 (INSN2_MOD_GPR_MN): Likewise.
42 2011-08-05 David S. Miller <davem@davemloft.net>
44 * sparc.h: Document new format codes '4', '5', and '('.
45 (OPF_LOW4, RS3): New macros.
47 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
49 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
50 order of flags documented.
52 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
54 * mips.h: Clarify the description of microMIPS instruction
56 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
58 2011-07-24 Chao-ying Fu <fu@mips.com>
59 Maciej W. Rozycki <macro@codesourcery.com>
61 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
62 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
63 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
64 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
65 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
66 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
67 (OP_MASK_RS3, OP_SH_RS3): Likewise.
68 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
69 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
70 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
71 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
72 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
73 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
74 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
75 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
76 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
77 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
78 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
79 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
80 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
81 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
82 (INSN_WRITE_GPR_S): New macro.
83 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
84 (INSN2_READ_FPR_D): Likewise.
85 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
86 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
87 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
88 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
89 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
90 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
91 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
92 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
93 (CPU_MICROMIPS): New macro.
94 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
95 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
96 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
97 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
98 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
99 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
100 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
101 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
102 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
103 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
104 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
105 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
106 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
107 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
108 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
109 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
110 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
111 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
112 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
113 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
114 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
115 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
116 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
117 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
118 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
119 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
120 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
121 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
122 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
123 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
124 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
125 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
126 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
127 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
128 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
129 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
130 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
131 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
132 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
133 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
134 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
135 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
136 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
137 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
138 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
139 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
140 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
141 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
142 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
143 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
144 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
145 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
146 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
147 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
148 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
149 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
150 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
151 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
152 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
153 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
154 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
155 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
156 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
157 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
158 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
159 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
160 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
161 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
162 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
163 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
164 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
165 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
166 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
167 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
168 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
169 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
170 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
171 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
172 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
173 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
174 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
175 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
176 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
177 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
178 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
179 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
180 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
181 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
182 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
183 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
184 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
185 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
186 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
187 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
188 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
189 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
190 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
191 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
192 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
193 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
194 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
195 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
196 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
197 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
198 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
199 (micromips_opcodes): New declaration.
200 (bfd_micromips_num_opcodes): Likewise.
202 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
204 * mips.h (INSN_TRAP): Rename to...
205 (INSN_NO_DELAY_SLOT): ... this.
206 (INSN_SYNC): Remove macro.
208 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
210 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
211 a duplicate of AVR_ISA_SPM.
213 2011-07-01 Nick Clifton <nickc@redhat.com>
215 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
217 2011-06-18 Robin Getz <robin.getz@analog.com>
219 * bfin.h (is_macmod_signed): New func
221 2011-06-18 Mike Frysinger <vapier@gentoo.org>
223 * bfin.h (is_macmod_pmove): Add missing space before func args.
224 (is_macmod_hmove): Likewise.
226 2011-06-13 Walter Lee <walt@tilera.com>
228 * tilegx.h: New file.
229 * tilepro.h: New file.
231 2011-05-31 Paul Brook <paul@codesourcery.com>
233 * arm.h (ARM_ARCH_V7R_IDIV): Define.
235 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
237 * s390.h: Replace S390_OPERAND_REG_EVEN with
238 S390_OPERAND_REG_PAIR.
240 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
242 * s390.h: Add S390_OPCODE_REG_EVEN flag.
244 2011-04-18 Julian Brown <julian@codesourcery.com>
246 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
248 2011-04-11 Dan McDonald <dan@wellkeeper.com>
251 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
253 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
255 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
256 New instruction set flags.
257 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
259 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
261 * mips.h (M_PREF_AB): New enum value.
263 2011-02-12 Mike Frysinger <vapier@gentoo.org>
265 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
267 (is_macmod_pmove, is_macmod_hmove): New functions.
269 2011-02-11 Mike Frysinger <vapier@gentoo.org>
271 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
273 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
275 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
276 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
278 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
281 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
284 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
287 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
289 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
291 * mips.h: Update commentary after last commit.
293 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
295 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
296 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
297 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
299 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
301 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
303 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
305 * mips.h: Fix previous commit.
307 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
309 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
310 (INSN_LOONGSON_3A): Clear bit 31.
312 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
315 * arm.h (ARM_AEXT_V6M_ONLY): New define.
316 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
317 (ARM_ARCH_V6M_ONLY): New define.
319 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
321 * mips.h (INSN_LOONGSON_3A): Defined.
322 (CPU_LOONGSON_3A): Defined.
323 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
325 2010-10-09 Matt Rice <ratmice@gmail.com>
327 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
328 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
330 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
332 * arm.h (ARM_EXT_VIRT): New define.
333 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
334 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
337 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
339 * arm.h (ARM_AEXT_ADIV): New define.
340 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
342 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
344 * arm.h (ARM_EXT_OS): New define.
345 (ARM_AEXT_V6SM): Likewise.
346 (ARM_ARCH_V6SM): Likewise.
348 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
350 * arm.h (ARM_EXT_MP): Add.
351 (ARM_ARCH_V7A_MP): Likewise.
353 2010-09-22 Mike Frysinger <vapier@gentoo.org>
355 * bfin.h: Declare pseudoChr structs/defines.
357 2010-09-21 Mike Frysinger <vapier@gentoo.org>
359 * bfin.h: Strip trailing whitespace.
361 2010-07-29 DJ Delorie <dj@redhat.com>
363 * rx.h (RX_Operand_Type): Add TwoReg.
364 (RX_Opcode_ID): Remove ediv and ediv2.
366 2010-07-27 DJ Delorie <dj@redhat.com>
368 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
370 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
371 Ina Pandit <ina.pandit@kpitcummins.com>
373 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
374 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
375 PROCESSOR_V850E2_ALL.
376 Remove PROCESSOR_V850EA support.
377 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
378 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
379 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
380 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
381 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
382 V850_OPERAND_PERCENT.
383 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
385 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
388 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
390 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
391 (MIPS16_INSN_BRANCH): Rename to...
392 (MIPS16_INSN_COND_BRANCH): ... this.
394 2010-07-03 Alan Modra <amodra@gmail.com>
396 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
397 Renumber other PPC_OPCODE defines.
399 2010-07-03 Alan Modra <amodra@gmail.com>
401 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
403 2010-06-29 Alan Modra <amodra@gmail.com>
405 * maxq.h: Delete file.
407 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
409 * ppc.h (PPC_OPCODE_E500): Define.
411 2010-05-26 Catherine Moore <clm@codesourcery.com>
413 * opcode/mips.h (INSN_MIPS16): Remove.
415 2010-04-21 Joseph Myers <joseph@codesourcery.com>
417 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
419 2010-04-15 Nick Clifton <nickc@redhat.com>
421 * alpha.h: Update copyright notice to use GPLv3.
427 * convex.h: Likewise.
441 * m68hc11.h: Likewise.
447 * mn10200.h: Likewise.
448 * mn10300.h: Likewise.
449 * msp430.h: Likewise.
460 * score-datadep.h: Likewise.
461 * score-inst.h: Likewise.
463 * spu-insns.h: Likewise.
467 * tic54x.h: Likewise.
472 2010-03-25 Joseph Myers <joseph@codesourcery.com>
474 * tic6x-control-registers.h, tic6x-insn-formats.h,
475 tic6x-opcode-table.h, tic6x.h: New.
477 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
479 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
481 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
483 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
485 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
487 * ia64.h (ia64_find_opcode): Remove argument name.
488 (ia64_find_next_opcode): Likewise.
489 (ia64_dis_opcode): Likewise.
490 (ia64_free_opcode): Likewise.
491 (ia64_find_dependency): Likewise.
493 2009-11-22 Doug Evans <dje@sebabeach.org>
495 * cgen.h: Include bfd_stdint.h.
496 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
498 2009-11-18 Paul Brook <paul@codesourcery.com>
500 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
502 2009-11-17 Paul Brook <paul@codesourcery.com>
503 Daniel Jacobowitz <dan@codesourcery.com>
505 * arm.h (ARM_EXT_V6_DSP): Define.
506 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
507 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
509 2009-11-04 DJ Delorie <dj@redhat.com>
511 * rx.h (rx_decode_opcode) (mvtipl): Add.
512 (mvtcp, mvfcp, opecp): Remove.
514 2009-11-02 Paul Brook <paul@codesourcery.com>
516 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
517 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
518 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
519 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
520 FPU_ARCH_NEON_VFP_V4): Define.
522 2009-10-23 Doug Evans <dje@sebabeach.org>
524 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
525 * cgen.h: Update. Improve multi-inclusion macro name.
527 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
529 * ppc.h (PPC_OPCODE_476): Define.
531 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
533 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
535 2009-09-29 DJ Delorie <dj@redhat.com>
539 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
541 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
543 2009-09-21 Ben Elliston <bje@au.ibm.com>
545 * ppc.h (PPC_OPCODE_PPCA2): New.
547 2009-09-05 Martin Thuresson <martin@mtme.org>
549 * ia64.h (struct ia64_operand): Renamed member class to op_class.
551 2009-08-29 Martin Thuresson <martin@mtme.org>
553 * tic30.h (template): Rename type template to
554 insn_template. Updated code to use new name.
555 * tic54x.h (template): Rename type template to
558 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
560 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
562 2009-06-11 Anthony Green <green@moxielogic.com>
564 * moxie.h (MOXIE_F3_PCREL): Define.
565 (moxie_form3_opc_info): Grow.
567 2009-06-06 Anthony Green <green@moxielogic.com>
569 * moxie.h (MOXIE_F1_M): Define.
571 2009-04-15 Anthony Green <green@moxielogic.com>
575 2009-04-06 DJ Delorie <dj@redhat.com>
577 * h8300.h: Add relaxation attributes to MOVA opcodes.
579 2009-03-10 Alan Modra <amodra@bigpond.net.au>
581 * ppc.h (ppc_parse_cpu): Declare.
583 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
585 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
586 and _IMM11 for mbitclr and mbitset.
587 * score-datadep.h: Update dependency information.
589 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
591 * ppc.h (PPC_OPCODE_POWER7): New.
593 2009-02-06 Doug Evans <dje@google.com>
595 * i386.h: Add comment regarding sse* insns and prefixes.
597 2009-02-03 Sandip Matte <sandip@rmicorp.com>
599 * mips.h (INSN_XLR): Define.
600 (INSN_CHIP_MASK): Update.
602 (OPCODE_IS_MEMBER): Update.
603 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
605 2009-01-28 Doug Evans <dje@google.com>
607 * opcode/i386.h: Add multiple inclusion protection.
608 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
609 (EDI_REG_NUM): New macros.
610 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
611 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
612 (REX_PREFIX_P): New macro.
614 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
616 * ppc.h (struct powerpc_opcode): New field "deprecated".
617 (PPC_OPCODE_NOPOWER4): Delete.
619 2008-11-28 Joshua Kinard <kumba@gentoo.org>
621 * mips.h: Define CPU_R14000, CPU_R16000.
622 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
624 2008-11-18 Catherine Moore <clm@codesourcery.com>
626 * arm.h (FPU_NEON_FP16): New.
627 (FPU_ARCH_NEON_FP16): New.
629 2008-11-06 Chao-ying Fu <fu@mips.com>
631 * mips.h: Doucument '1' for 5-bit sync type.
633 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
635 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
638 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
640 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
642 2008-07-30 Michael J. Eager <eager@eagercon.com>
644 * ppc.h (PPC_OPCODE_405): Define.
645 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
647 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
649 * ppc.h (ppc_cpu_t): New typedef.
650 (struct powerpc_opcode <flags>): Use it.
651 (struct powerpc_operand <insert, extract>): Likewise.
652 (struct powerpc_macro <flags>): Likewise.
654 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
656 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
657 Update comment before MIPS16 field descriptors to mention MIPS16.
658 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
660 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
661 New bit masks and shift counts for cins and exts.
663 * mips.h: Document new field descriptors +Q.
664 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
666 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
668 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
669 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
671 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
673 * ppc.h: (PPC_OPCODE_E500MC): New.
675 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
677 * i386.h (MAX_OPERANDS): Set to 5.
678 (MAX_MNEM_SIZE): Changed to 20.
680 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
682 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
684 2008-03-09 Paul Brook <paul@codesourcery.com>
686 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
688 2008-03-04 Paul Brook <paul@codesourcery.com>
690 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
691 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
692 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
694 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
695 Nick Clifton <nickc@redhat.com>
698 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
699 with a 32-bit displacement but without the top bit of the 4th byte
702 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
704 * cr16.h (cr16_num_optab): Declared.
706 2008-02-14 Hakan Ardo <hakan@debian.org>
709 * avr.h (AVR_ISA_2xxe): Define.
711 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
713 * mips.h: Update copyright.
714 (INSN_CHIP_MASK): New macro.
715 (INSN_OCTEON): New macro.
716 (CPU_OCTEON): New macro.
717 (OPCODE_IS_MEMBER): Handle Octeon instructions.
719 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
721 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
723 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
725 * avr.h (AVR_ISA_USB162): Add new opcode set.
726 (AVR_ISA_AVR3): Likewise.
728 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
730 * mips.h (INSN_LOONGSON_2E): New.
731 (INSN_LOONGSON_2F): New.
732 (CPU_LOONGSON_2E): New.
733 (CPU_LOONGSON_2F): New.
734 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
736 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
738 * mips.h (INSN_ISA*): Redefine certain values as an
739 enumeration. Update comments.
740 (mips_isa_table): New.
741 (ISA_MIPS*): Redefine to match enumeration.
742 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
745 2007-08-08 Ben Elliston <bje@au.ibm.com>
747 * ppc.h (PPC_OPCODE_PPCPS): New.
749 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
751 * m68k.h: Document j K & E.
753 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
755 * cr16.h: New file for CR16 target.
757 2007-05-02 Alan Modra <amodra@bigpond.net.au>
759 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
761 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
763 * m68k.h (mcfisa_c): New.
764 (mcfusp, mcf_mask): Adjust.
766 2007-04-20 Alan Modra <amodra@bigpond.net.au>
768 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
769 (num_powerpc_operands): Declare.
770 (PPC_OPERAND_SIGNED et al): Redefine as hex.
771 (PPC_OPERAND_PLUS1): Define.
773 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
775 * i386.h (REX_MODE64): Renamed to ...
777 (REX_EXTX): Renamed to ...
779 (REX_EXTY): Renamed to ...
781 (REX_EXTZ): Renamed to ...
784 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
786 * i386.h: Add entries from config/tc-i386.h and move tables
787 to opcodes/i386-opc.h.
789 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
791 * i386.h (FloatDR): Removed.
792 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
794 2007-03-01 Alan Modra <amodra@bigpond.net.au>
796 * spu-insns.h: Add soma double-float insns.
798 2007-02-20 Thiemo Seufer <ths@mips.com>
799 Chao-Ying Fu <fu@mips.com>
801 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
802 (INSN_DSPR2): Add flag for DSP R2 instructions.
803 (M_BALIGN): New macro.
805 2007-02-14 Alan Modra <amodra@bigpond.net.au>
807 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
808 and Seg3ShortFrom with Shortform.
810 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
813 * i386.h (i386_optab): Put the real "test" before the pseudo
816 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
818 * m68k.h (m68010up): OR fido_a.
820 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
822 * m68k.h (fido_a): New.
824 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
826 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
827 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
830 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
832 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
834 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
836 * score-inst.h (enum score_insn_type): Add Insn_internal.
838 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
839 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
840 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
841 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
842 Alan Modra <amodra@bigpond.net.au>
844 * spu-insns.h: New file.
847 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
849 * ppc.h (PPC_OPCODE_CELL): Define.
851 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
853 * i386.h : Modify opcode to support for the change in POPCNT opcode
854 in amdfam10 architecture.
856 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
858 * i386.h: Replace CpuMNI with CpuSSSE3.
860 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
861 Joseph Myers <joseph@codesourcery.com>
862 Ian Lance Taylor <ian@wasabisystems.com>
863 Ben Elliston <bje@wasabisystems.com>
865 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
867 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
869 * score-datadep.h: New file.
870 * score-inst.h: New file.
872 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
874 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
875 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
878 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
879 Michael Meissner <michael.meissner@amd.com>
881 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
883 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
885 * i386.h (i386_optab): Add "nop" with memory reference.
887 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
889 * i386.h (i386_optab): Update comment for 64bit NOP.
891 2006-06-06 Ben Elliston <bje@au.ibm.com>
892 Anton Blanchard <anton@samba.org>
894 * ppc.h (PPC_OPCODE_POWER6): Define.
897 2006-06-05 Thiemo Seufer <ths@mips.com>
899 * mips.h: Improve description of MT flags.
901 2006-05-25 Richard Sandiford <richard@codesourcery.com>
903 * m68k.h (mcf_mask): Define.
905 2006-05-05 Thiemo Seufer <ths@mips.com>
906 David Ung <davidu@mips.com>
908 * mips.h (enum): Add macro M_CACHE_AB.
910 2006-05-04 Thiemo Seufer <ths@mips.com>
911 Nigel Stephens <nigel@mips.com>
912 David Ung <davidu@mips.com>
914 * mips.h: Add INSN_SMARTMIPS define.
916 2006-04-30 Thiemo Seufer <ths@mips.com>
917 David Ung <davidu@mips.com>
919 * mips.h: Defines udi bits and masks. Add description of
920 characters which may appear in the args field of udi
923 2006-04-26 Thiemo Seufer <ths@networkno.de>
925 * mips.h: Improve comments describing the bitfield instruction
928 2006-04-26 Julian Brown <julian@codesourcery.com>
930 * arm.h (FPU_VFP_EXT_V3): Define constant.
931 (FPU_NEON_EXT_V1): Likewise.
932 (FPU_VFP_HARD): Update.
933 (FPU_VFP_V3): Define macro.
934 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
936 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
938 * avr.h (AVR_ISA_PWMx): New.
940 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
942 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
943 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
944 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
945 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
946 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
948 2006-03-10 Paul Brook <paul@codesourcery.com>
950 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
952 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
954 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
955 first. Correct mask of bb "B" opcode.
957 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
959 * i386.h (i386_optab): Support Intel Merom New Instructions.
961 2006-02-24 Paul Brook <paul@codesourcery.com>
963 * arm.h: Add V7 feature bits.
965 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
967 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
969 2006-01-31 Paul Brook <paul@codesourcery.com>
970 Richard Earnshaw <rearnsha@arm.com>
972 * arm.h: Use ARM_CPU_FEATURE.
973 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
974 (arm_feature_set): Change to a structure.
975 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
976 ARM_FEATURE): New macros.
978 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
980 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
981 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
982 (ADD_PC_INCR_OPCODE): Don't define.
984 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
987 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
989 2005-11-14 David Ung <davidu@mips.com>
991 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
992 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
993 save/restore encoding of the args field.
995 2005-10-28 Dave Brolley <brolley@redhat.com>
997 Contribute the following changes:
998 2005-02-16 Dave Brolley <brolley@redhat.com>
1000 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1001 cgen_isa_mask_* to cgen_bitset_*.
1004 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1006 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1007 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1008 (CGEN_CPU_TABLE): Make isas a ponter.
1010 2003-09-29 Dave Brolley <brolley@redhat.com>
1012 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1013 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1014 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1016 2002-12-13 Dave Brolley <brolley@redhat.com>
1018 * cgen.h (symcat.h): #include it.
1019 (cgen-bitset.h): #include it.
1020 (CGEN_ATTR_VALUE_TYPE): Now a union.
1021 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1022 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1023 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1024 * cgen-bitset.h: New file.
1026 2005-09-30 Catherine Moore <clm@cm00re.com>
1030 2005-10-24 Jan Beulich <jbeulich@novell.com>
1032 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1035 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1037 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1038 Add FLAG_STRICT to pa10 ftest opcode.
1040 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1042 * hppa.h (pa_opcodes): Remove lha entries.
1044 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1046 * hppa.h (FLAG_STRICT): Revise comment.
1047 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1048 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1051 2005-09-30 Catherine Moore <clm@cm00re.com>
1055 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1057 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1059 2005-09-06 Chao-ying Fu <fu@mips.com>
1061 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1062 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1064 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1065 (INSN_ASE_MASK): Update to include INSN_MT.
1066 (INSN_MT): New define for MT ASE.
1068 2005-08-25 Chao-ying Fu <fu@mips.com>
1070 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1071 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1072 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1073 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1074 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1075 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1077 (INSN_DSP): New define for DSP ASE.
1079 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1083 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1085 * ppc.h (PPC_OPCODE_E300): Define.
1087 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1089 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1091 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1094 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1097 2005-07-27 Jan Beulich <jbeulich@novell.com>
1099 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1100 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1101 Add movq-s as 64-bit variants of movd-s.
1103 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1105 * hppa.h: Fix punctuation in comment.
1107 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1108 implicit space-register addressing. Set space-register bits on opcodes
1109 using implicit space-register addressing. Add various missing pa20
1110 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1111 space-register addressing. Use "fE" instead of "fe" in various
1114 2005-07-18 Jan Beulich <jbeulich@novell.com>
1116 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1118 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1120 * i386.h (i386_optab): Support Intel VMX Instructions.
1122 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1124 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1126 2005-07-05 Jan Beulich <jbeulich@novell.com>
1128 * i386.h (i386_optab): Add new insns.
1130 2005-07-01 Nick Clifton <nickc@redhat.com>
1132 * sparc.h: Add typedefs to structure declarations.
1134 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1137 * i386.h (i386_optab): Update comments for 64bit addressing on
1138 mov. Allow 64bit addressing for mov and movq.
1140 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1142 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1143 respectively, in various floating-point load and store patterns.
1145 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1147 * hppa.h (FLAG_STRICT): Correct comment.
1148 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1149 PA 2.0 mneumonics when equivalent. Entries with cache control
1150 completers now require PA 1.1. Adjust whitespace.
1152 2005-05-19 Anton Blanchard <anton@samba.org>
1154 * ppc.h (PPC_OPCODE_POWER5): Define.
1156 2005-05-10 Nick Clifton <nickc@redhat.com>
1158 * Update the address and phone number of the FSF organization in
1159 the GPL notices in the following files:
1160 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1161 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1162 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1163 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1164 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1165 tic54x.h, tic80.h, v850.h, vax.h
1167 2005-05-09 Jan Beulich <jbeulich@novell.com>
1169 * i386.h (i386_optab): Add ht and hnt.
1171 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1173 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1174 Add xcrypt-ctr. Provide aliases without hyphens.
1176 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1178 Moved from ../ChangeLog
1180 2005-04-12 Paul Brook <paul@codesourcery.com>
1181 * m88k.h: Rename psr macros to avoid conflicts.
1183 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1184 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1185 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1186 and ARM_ARCH_V6ZKT2.
1188 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1189 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1190 Remove redundant instruction types.
1191 (struct argument): X_op - new field.
1192 (struct cst4_entry): Remove.
1193 (no_op_insn): Declare.
1195 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1196 * crx.h (enum argtype): Rename types, remove unused types.
1198 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1199 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1200 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1201 (enum operand_type): Rearrange operands, edit comments.
1202 replace us<N> with ui<N> for unsigned immediate.
1203 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1204 displacements (respectively).
1205 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1206 (instruction type): Add NO_TYPE_INS.
1207 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1208 (operand_entry): New field - 'flags'.
1209 (operand flags): New.
1211 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1212 * crx.h (operand_type): Remove redundant types i3, i4,
1214 Add new unsigned immediate types us3, us4, us5, us16.
1216 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1218 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1219 adjust them accordingly.
1221 2005-04-01 Jan Beulich <jbeulich@novell.com>
1223 * i386.h (i386_optab): Add rdtscp.
1225 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1227 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1228 between memory and segment register. Allow movq for moving between
1229 general-purpose register and segment register.
1231 2005-02-09 Jan Beulich <jbeulich@novell.com>
1234 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1235 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1238 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1240 * m68k.h (m68008, m68ec030, m68882): Remove.
1242 (cpu_m68k, cpu_cf): New.
1243 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1244 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1246 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1248 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1249 * cgen.h (enum cgen_parse_operand_type): Add
1250 CGEN_PARSE_OPERAND_SYMBOLIC.
1252 2005-01-21 Fred Fish <fnf@specifixinc.com>
1254 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1255 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1256 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1258 2005-01-19 Fred Fish <fnf@specifixinc.com>
1260 * mips.h (struct mips_opcode): Add new pinfo2 member.
1261 (INSN_ALIAS): New define for opcode table entries that are
1262 specific instances of another entry, such as 'move' for an 'or'
1263 with a zero operand.
1264 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1265 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1267 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1269 * mips.h (CPU_RM9000): Define.
1270 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1272 2004-11-25 Jan Beulich <jbeulich@novell.com>
1274 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1275 to/from test registers are illegal in 64-bit mode. Add missing
1276 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1277 (previously one had to explicitly encode a rex64 prefix). Re-enable
1278 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1279 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1281 2004-11-23 Jan Beulich <jbeulich@novell.com>
1283 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1284 available only with SSE2. Change the MMX additions introduced by SSE
1285 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1286 instructions by their now designated identifier (since combining i686
1287 and 3DNow! does not really imply 3DNow!A).
1289 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1291 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1292 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1294 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1295 Vineet Sharma <vineets@noida.hcltech.com>
1297 * maxq.h: New file: Disassembly information for the maxq port.
1299 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1301 * i386.h (i386_optab): Put back "movzb".
1303 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1305 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1306 comments. Remove member cris_ver_sim. Add members
1307 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1308 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1309 (struct cris_support_reg, struct cris_cond15): New types.
1310 (cris_conds15): Declare.
1311 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1312 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1313 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1314 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1315 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1316 SIZE_FIELD_UNSIGNED.
1318 2004-11-04 Jan Beulich <jbeulich@novell.com>
1320 * i386.h (sldx_Suf): Remove.
1321 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1322 (q_FP): Define, implying no REX64.
1323 (x_FP, sl_FP): Imply FloatMF.
1324 (i386_optab): Split reg and mem forms of moving from segment registers
1325 so that the memory forms can ignore the 16-/32-bit operand size
1326 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1327 all non-floating-point instructions. Unite 32- and 64-bit forms of
1328 movsx, movzx, and movd. Adjust floating point operations for the above
1329 changes to the *FP macros. Add DefaultSize to floating point control
1330 insns operating on larger memory ranges. Remove left over comments
1331 hinting at certain insns being Intel-syntax ones where the ones
1332 actually meant are already gone.
1334 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1336 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1339 2004-09-30 Paul Brook <paul@codesourcery.com>
1341 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1342 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1344 2004-09-11 Theodore A. Roth <troth@openavr.org>
1346 * avr.h: Add support for
1347 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1349 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1351 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1353 2004-08-24 Dmitry Diky <diwil@spec.ru>
1355 * msp430.h (msp430_opc): Add new instructions.
1356 (msp430_rcodes): Declare new instructions.
1357 (msp430_hcodes): Likewise..
1359 2004-08-13 Nick Clifton <nickc@redhat.com>
1362 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1365 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1367 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1369 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1371 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1373 2004-07-21 Jan Beulich <jbeulich@novell.com>
1375 * i386.h: Adjust instruction descriptions to better match the
1378 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1380 * arm.h: Remove all old content. Replace with architecture defines
1381 from gas/config/tc-arm.c.
1383 2004-07-09 Andreas Schwab <schwab@suse.de>
1385 * m68k.h: Fix comment.
1387 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1391 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1393 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1395 2004-05-24 Peter Barada <peter@the-baradas.com>
1397 * m68k.h: Add 'size' to m68k_opcode.
1399 2004-05-05 Peter Barada <peter@the-baradas.com>
1401 * m68k.h: Switch from ColdFire chip name to core variant.
1403 2004-04-22 Peter Barada <peter@the-baradas.com>
1405 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1406 descriptions for new EMAC cases.
1407 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1408 handle Motorola MAC syntax.
1409 Allow disassembly of ColdFire V4e object files.
1411 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1413 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1415 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1417 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1419 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1421 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1423 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1425 * i386.h (i386_optab): Added xstore/xcrypt insns.
1427 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1429 * h8300.h (32bit ldc/stc): Add relaxing support.
1431 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1433 * h8300.h (BITOP): Pass MEMRELAX flag.
1435 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1437 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1440 For older changes see ChangeLog-9103
1446 version-control: never