include/opcode/ChangeLog

   1 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/1874
   4         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
   5
   6 2005-11-14  David Ung  <davidu@mips.com>
   7
   8         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
   9         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  10         save/restore encoding of the args field.
  11
  12 2005-10-28  Dave Brolley  <brolley@redhat.com>
  13
  14         Contribute the following changes:
  15         2005-02-16  Dave Brolley  <brolley@redhat.com>
  16
  17         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  18         cgen_isa_mask_* to cgen_bitset_*.
  19         * cgen.h: Likewise.
  20
  21         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  22
  23         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  24         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  25         (CGEN_CPU_TABLE): Make isas a ponter.
  26
  27         2003-09-29  Dave Brolley  <brolley@redhat.com>
  28
  29         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  30         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  31         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  32
  33         2002-12-13  Dave Brolley  <brolley@redhat.com>
  34
  35         * cgen.h (symcat.h): #include it.
  36         (cgen-bitset.h): #include it.
  37         (CGEN_ATTR_VALUE_TYPE): Now a union.
  38         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  39         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  40         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  41         * cgen-bitset.h: New file.
  42
  43 2005-09-30  Catherine Moore  <clm@cm00re.com>
  44
  45         * bfin.h: New file.
  46
  47 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  48
  49         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  50         indirect operands.
  51
  52 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  53
  54         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  55         Add FLAG_STRICT to pa10 ftest opcode.
  56
  57 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  58
  59         * hppa.h (pa_opcodes): Remove lha entries.
  60
  61 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  62
  63         * hppa.h (FLAG_STRICT): Revise comment.
  64         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  65         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  66         entries for "fdc".
  67
  68 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  69
  70         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  71
  72 2005-09-06  Chao-ying Fu  <fu@mips.com>
  73
  74         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
  75         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
  76         define.
  77         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
  78         (INSN_ASE_MASK): Update to include INSN_MT.
  79         (INSN_MT): New define for MT ASE.
  80
  81 2005-08-25  Chao-ying Fu  <fu@mips.com>
  82
  83         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  84         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  85         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  86         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  87         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  88         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  89         instructions.
  90         (INSN_DSP): New define for DSP ASE.
  91
  92 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  93
  94         * a29k.h: Delete.
  95
  96 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
  97
  98         * ppc.h (PPC_OPCODE_E300): Define.
  99
 100 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 101
 102         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 103
 104 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 105
 106         PR gas/336
 107         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 108         and pitlb.
 109
 110 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 111
 112         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 113         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 114         Add movq-s as 64-bit variants of movd-s.
 115
 116 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 117
 118         * hppa.h: Fix punctuation in comment.
 119
 120         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 121         implicit space-register addressing.  Set space-register bits on opcodes
 122         using implicit space-register addressing.  Add various missing pa20
 123         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 124         space-register addressing.  Use "fE" instead of "fe" in various
 125         fstw opcodes.
 126
 127 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 128
 129         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 130
 131 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 132
 133         * i386.h (i386_optab): Support Intel VMX Instructions.
 134
 135 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 136
 137         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 138
 139 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 140
 141         * i386.h (i386_optab): Add new insns.
 142
 143 2005-07-01  Nick Clifton  <nickc@redhat.com>
 144
 145         * sparc.h: Add typedefs to structure declarations.
 146
 147 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         PR 1013
 150         * i386.h (i386_optab): Update comments for 64bit addressing on
 151         mov. Allow 64bit addressing for mov and movq.
 152
 153 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 154
 155         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 156         respectively, in various floating-point load and store patterns.
 157
 158 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 159
 160         * hppa.h (FLAG_STRICT): Correct comment.
 161         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 162         PA 2.0 mneumonics when equivalent.  Entries with cache control
 163         completers now require PA 1.1.  Adjust whitespace.
 164
 165 2005-05-19  Anton Blanchard  <anton@samba.org>
 166
 167         * ppc.h (PPC_OPCODE_POWER5): Define.
 168
 169 2005-05-10  Nick Clifton  <nickc@redhat.com>
 170
 171         * Update the address and phone number of the FSF organization in
 172         the GPL notices in the following files:
 173         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 174         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 175         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 176         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 177         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 178         tic54x.h, tic80.h, v850.h, vax.h
 179
 180 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 181
 182         * i386.h (i386_optab): Add ht and hnt.
 183
 184 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 185
 186         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 187         Add xcrypt-ctr.  Provide aliases without hyphens.
 188
 189 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 190
 191         Moved from ../ChangeLog
 192
 193         2005-04-12  Paul Brook  <paul@codesourcery.com>
 194         * m88k.h: Rename psr macros to avoid conflicts.
 195
 196         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 197         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 198         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 199         and ARM_ARCH_V6ZKT2.
 200
 201         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 202         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 203         Remove redundant instruction types.
 204         (struct argument): X_op - new field.
 205         (struct cst4_entry): Remove.
 206         (no_op_insn): Declare.
 207
 208         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 209         * crx.h (enum argtype): Rename types, remove unused types.
 210
 211         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 212         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 213         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 214         (enum operand_type): Rearrange operands, edit comments.
 215         replace us<N> with ui<N> for unsigned immediate.
 216         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 217         displacements (respectively).
 218         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 219         (instruction type): Add NO_TYPE_INS.
 220         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 221         (operand_entry): New field - 'flags'.
 222         (operand flags): New.
 223
 224         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 225         * crx.h (operand_type): Remove redundant types i3, i4,
 226         i5, i8, i12.
 227         Add new unsigned immediate types us3, us4, us5, us16.
 228
 229 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 230
 231         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 232         adjust them accordingly.
 233
 234 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 235
 236         * i386.h (i386_optab): Add rdtscp.
 237
 238 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 241         between memory and segment register. Allow movq for moving between
 242         general-purpose register and segment register.
 243
 244 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 245
 246         PR gas/707
 247         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 248         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 249         fnstsw.
 250
 251 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 252
 253         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 254         * cgen.h (enum cgen_parse_operand_type): Add
 255         CGEN_PARSE_OPERAND_SYMBOLIC.
 256
 257 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 258
 259         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 260         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 261         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 262
 263 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 264
 265         * mips.h (struct mips_opcode): Add new pinfo2 member.
 266         (INSN_ALIAS): New define for opcode table entries that are
 267         specific instances of another entry, such as 'move' for an 'or'
 268         with a zero operand.
 269         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 270         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 271
 272 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 273
 274         * mips.h (CPU_RM9000): Define.
 275         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 276
 277 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 278
 279         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 280         to/from test registers are illegal in 64-bit mode. Add missing
 281         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 282         (previously one had to explicitly encode a rex64 prefix). Re-enable
 283         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 284         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 285
 286 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 287
 288         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 289         available only with SSE2. Change the MMX additions introduced by SSE
 290         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 291         instructions by their now designated identifier (since combining i686
 292         and 3DNow! does not really imply 3DNow!A).
 293
 294 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 295
 296         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 297         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 298
 299 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 300             Vineet Sharma      <vineets@noida.hcltech.com>
 301
 302         * maxq.h: New file: Disassembly information for the maxq port.
 303
 304 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * i386.h (i386_optab): Put back "movzb".
 307
 308 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 309
 310         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 311         comments.  Remove member cris_ver_sim.  Add members
 312         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 313         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 314         (struct cris_support_reg, struct cris_cond15): New types.
 315         (cris_conds15): Declare.
 316         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 317         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 318         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 319         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 320         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 321         SIZE_FIELD_UNSIGNED.
 322
 323 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 324
 325         * i386.h (sldx_Suf): Remove.
 326         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 327         (q_FP): Define, implying no REX64.
 328         (x_FP, sl_FP): Imply FloatMF.
 329         (i386_optab): Split reg and mem forms of moving from segment registers
 330         so that the memory forms can ignore the 16-/32-bit operand size
 331         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 332         all non-floating-point instructions. Unite 32- and 64-bit forms of
 333         movsx, movzx, and movd. Adjust floating point operations for the above
 334         changes to the *FP macros. Add DefaultSize to floating point control
 335         insns operating on larger memory ranges. Remove left over comments
 336         hinting at certain insns being Intel-syntax ones where the ones
 337         actually meant are already gone.
 338
 339 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 340
 341         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 342         instruction type.
 343
 344 2004-09-30  Paul Brook  <paul@codesourcery.com>
 345
 346         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 347         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 348
 349 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 350
 351         * avr.h: Add support for
 352         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 353
 354 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 355
 356         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 357
 358 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 359
 360         * msp430.h (msp430_opc): Add new instructions.
 361         (msp430_rcodes): Declare new instructions.
 362         (msp430_hcodes): Likewise..
 363
 364 2004-08-13  Nick Clifton  <nickc@redhat.com>
 365
 366         PR/301
 367         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 368         processors.
 369
 370 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 371
 372         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 373
 374 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 375
 376         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 377
 378 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 379
 380         * i386.h: Adjust instruction descriptions to better match the
 381         specification.
 382
 383 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 384
 385         * arm.h: Remove all old content.  Replace with architecture defines
 386         from gas/config/tc-arm.c.
 387
 388 2004-07-09  Andreas Schwab  <schwab@suse.de>
 389
 390         * m68k.h: Fix comment.
 391
 392 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 393
 394         * crx.h: New file.
 395
 396 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 397
 398         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 399
 400 2004-05-24  Peter Barada  <peter@the-baradas.com>
 401
 402         * m68k.h: Add 'size' to m68k_opcode.
 403
 404 2004-05-05  Peter Barada  <peter@the-baradas.com>
 405
 406         * m68k.h: Switch from ColdFire chip name to core variant.
 407
 408 2004-04-22  Peter Barada  <peter@the-baradas.com>
 409
 410         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 411         descriptions for new EMAC cases.
 412         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 413         handle Motorola MAC syntax.
 414         Allow disassembly of ColdFire V4e object files.
 415
 416 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 417
 418         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 419
 420 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 421
 422         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 423
 424 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 425
 426         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 427
 428 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 429
 430         * i386.h (i386_optab): Added xstore/xcrypt insns.
 431
 432 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 433
 434         * h8300.h (32bit ldc/stc): Add relaxing support.
 435
 436 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 437
 438         * h8300.h (BITOP): Pass MEMRELAX flag.
 439
 440 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 441
 442         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 443         except for the H8S.
 444
 445 For older changes see ChangeLog-9103
 446 \f
 447 Local Variables:
 448 mode: change-log
 449 left-margin: 8
 450 fill-column: 74
 451 version-control: never
 452 End: