1 2015-04-30 DJ Delorie <dj@redhat.com>
3 * rl78.h (RL78_Dis_Isa): New.
4 (rl78_decode_opcode): Add ISA parameter.
6 2015-03-24 Terry Guo <terry.guo@arm.com>
8 * arm.h (arm_feature_set): Extended to provide more available bits.
9 (ARM_ANY): Updated to follow above new definition.
10 (ARM_CPU_HAS_FEATURE): Likewise.
11 (ARM_CPU_IS_ANY): Likewise.
12 (ARM_MERGE_FEATURE_SETS): Likewise.
13 (ARM_CLEAR_FEATURE): Likewise.
14 (ARM_FEATURE): Likewise.
15 (ARM_FEATURE_COPY): New macro.
16 (ARM_FEATURE_EQUAL): Likewise.
17 (ARM_FEATURE_ZERO): Likewise.
18 (ARM_FEATURE_CORE_EQUAL): Likewise.
19 (ARM_FEATURE_LOW): Likewise.
20 (ARM_FEATURE_CORE_LOW): Likewise.
21 (ARM_FEATURE_CORE_COPROC): Likewise.
23 2015-02-19 Pedro Alves <palves@redhat.com>
25 * cgen.h [__cplusplus]: Wrap in extern "C".
26 * msp430-decode.h [__cplusplus]: Likewise.
27 * nios2.h [__cplusplus]: Likewise.
28 * rl78.h [__cplusplus]: Likewise.
29 * rx.h [__cplusplus]: Likewise.
30 * tilegx.h [__cplusplus]: Likewise.
32 2015-01-28 James Bowman <james.bowman@ftdichip.com>
36 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
38 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
40 2015-01-01 Alan Modra <amodra@gmail.com>
42 Update year range in copyright notice of all files.
44 2014-12-27 Anthony Green <green@moxielogic.com>
46 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
47 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
49 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
53 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
55 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
56 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
57 (NIOS2_INSN_OPTARG): Renumber.
59 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
61 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
62 declaration. Fix obsolete comment.
64 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
66 * nios2.h (enum iw_format_type): New.
67 (struct nios2_opcode): Update comments. Add size and format fields.
68 (NIOS2_INSN_OPTARG): New.
69 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
70 (struct nios2_reg): Add regtype field.
71 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
72 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
73 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
74 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
75 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
76 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
77 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
78 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
79 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
80 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
81 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
82 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
83 (OP_MASK_OP, OP_SH_OP): Delete.
84 (OP_MASK_IOP, OP_SH_IOP): Delete.
85 (OP_MASK_IRD, OP_SH_IRD): Delete.
86 (OP_MASK_IRT, OP_SH_IRT): Delete.
87 (OP_MASK_IRS, OP_SH_IRS): Delete.
88 (OP_MASK_ROP, OP_SH_ROP): Delete.
89 (OP_MASK_RRD, OP_SH_RRD): Delete.
90 (OP_MASK_RRT, OP_SH_RRT): Delete.
91 (OP_MASK_RRS, OP_SH_RRS): Delete.
92 (OP_MASK_JOP, OP_SH_JOP): Delete.
93 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
94 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
95 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
96 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
97 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
98 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
99 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
100 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
101 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
102 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
103 (OP_MASK_<insn>, OP_MASK): Delete.
104 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
105 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
106 Include nios2r1.h to define new instruction opcode constants
108 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
109 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
110 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
111 (NUMOPCODES, NUMREGISTERS): Delete.
112 * nios2r1.h: New file.
114 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
116 * sparc.h (HWCAP2_VIS3B): Documentation improved.
118 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
120 * sparc.h (sparc_opcode): new field `hwcaps2'.
121 (HWCAP2_FJATHPLUS): New define.
122 (HWCAP2_VIS3B): Likewise.
123 (HWCAP2_ADP): Likewise.
124 (HWCAP2_SPARC5): Likewise.
125 (HWCAP2_MWAIT): Likewise.
126 (HWCAP2_XMPMUL): Likewise.
127 (HWCAP2_XMONT): Likewise.
128 (HWCAP2_NSEC): Likewise.
129 (HWCAP2_FJATHHPC): Likewise.
130 (HWCAP2_FJDES): Likewise.
131 (HWCAP2_FJAES): Likewise.
132 Document the new operand kind `{', corresponding to the mcdper
133 ancillary state register.
134 Document the new operand kind }, which represents frsd floating
135 point registers (double precision) which must be the same than
136 frs1 in its containing instruction.
138 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
140 * nds32.h: Add new opcode declaration.
142 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
143 Matthew Fortune <matthew.fortune@imgtec.com>
145 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
146 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
147 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
148 +I, +O, +R, +:, +\, +", +;
149 (mips_check_prev_operand): New struct.
150 (INSN2_FORBIDDEN_SLOT): New define.
151 (INSN_ISA32R6): New define.
152 (INSN_ISA64R6): New define.
153 (INSN_UPTO32R6): New define.
154 (INSN_UPTO64R6): New define.
155 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
156 (ISA_MIPS32R6): New define.
157 (ISA_MIPS64R6): New define.
158 (CPU_MIPS32R6): New define.
159 (CPU_MIPS64R6): New define.
160 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
162 2014-09-03 Jiong Wang <jiong.wang@arm.com>
164 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
165 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
166 (aarch64_insn_class): Add lse_atomic.
167 (F_LSE_SZ): New field added.
168 (opcode_has_special_coder): Recognize F_LSE_SZ.
170 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
172 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
175 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
177 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
178 (INSN_LOAD_COPROC): New define.
179 (INSN_COPROC_MOVE_DELAY): Rename to...
180 (INSN_COPROC_MOVE): New define.
182 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
183 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
184 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
185 Soundararajan <Sounderarajan.D@atmel.com>
187 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
188 (AVR_ISA_2xxxa): Define ISA without LPM.
189 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
190 Add doc for contraint used in 16 bit lds/sts.
191 Adjust ISA group for icall, ijmp, pop and push.
192 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
194 2014-05-19 Nick Clifton <nickc@redhat.com>
196 * msp430.h (struct msp430_operand_s): Add vshift field.
198 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
200 * mips.h (INSN_ISA_MASK): Updated.
201 (INSN_ISA32R3): New define.
202 (INSN_ISA32R5): New define.
203 (INSN_ISA64R3): New define.
204 (INSN_ISA64R5): New define.
205 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
206 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
207 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
209 (INSN_UPTO32R3): New define.
210 (INSN_UPTO32R5): New define.
211 (INSN_UPTO64R3): New define.
212 (INSN_UPTO64R5): New define.
213 (ISA_MIPS32R3): New define.
214 (ISA_MIPS32R5): New define.
215 (ISA_MIPS64R3): New define.
216 (ISA_MIPS64R5): New define.
217 (CPU_MIPS32R3): New define.
218 (CPU_MIPS32R5): New define.
219 (CPU_MIPS64R3): New define.
220 (CPU_MIPS64R5): New define.
222 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
224 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
226 2014-04-22 Christian Svensson <blue@cmd.nu>
230 2014-03-05 Alan Modra <amodra@gmail.com>
232 Update copyright years.
234 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
236 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
239 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
240 Wei-Cheng Wang <cole945@gmail.com>
242 * nds32.h: New file for Andes NDS32.
244 2013-12-07 Mike Frysinger <vapier@gentoo.org>
246 * bfin.h: Remove +x file mode.
248 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
250 * aarch64.h (aarch64_pstatefields): Change element type to
253 2013-11-18 Renlin Li <Renlin.Li@arm.com>
255 * arm.h (ARM_AEXT_V7VE): New define.
256 (ARM_ARCH_V7VE): New define.
257 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
259 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
263 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
265 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
266 (aarch64_sys_reg_writeonly_p): Ditto.
268 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
270 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
271 (aarch64_sys_reg_writeonly_p): Ditto.
273 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
275 * aarch64.h (aarch64_sys_reg): New typedef.
276 (aarch64_sys_regs): Change to define with the new type.
277 (aarch64_sys_reg_deprecated_p): Declare.
279 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
281 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
282 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
284 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
286 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
287 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
288 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
289 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
290 For MIPS, update extension character sequences after +.
291 (ASE_MSA): New define.
292 (ASE_MSA64): New define.
293 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
294 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
295 For microMIPS, update extension character sequences after +.
297 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
302 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
304 * mips.h: Remove references to "+I" and imm2_expr.
306 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
308 * mips.h (M_DEXT, M_DINS): Delete.
310 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
312 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
313 (mips_optional_operand_p): New function.
315 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
316 Richard Sandiford <rdsandiford@googlemail.com>
318 * mips.h: Document new VU0 operand characters.
319 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
320 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
321 (OP_REG_R5900_ACC): New mips_reg_operand_types.
322 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
323 (mips_vu0_channel_mask): Declare.
325 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
327 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
328 (mips_int_operand_min, mips_int_operand_max): New functions.
329 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
331 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
333 * mips.h (mips_decode_reg_operand): New function.
334 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
335 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
336 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
338 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
339 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
340 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
341 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
342 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
343 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
344 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
345 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
346 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
347 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
348 macros to cover the gaps.
349 (INSN2_MOD_SP): Replace with...
350 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
351 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
352 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
353 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
354 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
357 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
359 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
360 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
361 (MIPS16_INSN_COND_BRANCH): Delete.
363 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
364 Kirill Yukhin <kirill.yukhin@intel.com>
365 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
367 * i386.h (BND_PREFIX_OPCODE): New.
369 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
371 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
372 OP_SAVE_RESTORE_LIST.
373 (decode_mips16_operand): Declare.
375 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
377 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
378 (mips_operand, mips_int_operand, mips_mapped_int_operand)
379 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
380 (mips_pcrel_operand): New structures.
381 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
382 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
383 (decode_mips_operand, decode_micromips_operand): Declare.
385 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
387 * mips.h: Document MIPS16 "I" opcode.
389 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
391 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
392 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
393 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
394 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
395 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
396 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
397 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
398 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
399 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
400 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
401 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
402 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
403 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
405 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
406 (M_USD_AB): ...these.
408 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
410 * mips.h: Remove documentation of "[" and "]". Update documentation
411 of "k" and the MDMX formats.
413 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
415 * mips.h: Update documentation of "+s" and "+S".
417 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
419 * mips.h: Document "+i".
421 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
423 * mips.h: Remove "mi" documentation. Update "mh" documentation.
424 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
426 (INSN2_WRITE_GPR_MHI): Rename to...
427 (INSN2_WRITE_GPR_MH): ...this.
429 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
431 * mips.h: Remove documentation of "+D" and "+T".
433 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
435 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
436 Use "source" rather than "destination" for microMIPS "G".
438 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
440 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
443 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
447 2013-06-17 Catherine Moore <clm@codesourcery.com>
448 Maciej W. Rozycki <macro@codesourcery.com>
449 Chao-Ying Fu <fu@mips.com>
451 * mips.h (OP_SH_EVAOFFSET): Define.
452 (OP_MASK_EVAOFFSET): Define.
453 (INSN_ASE_MASK): Delete.
455 (M_CACHEE_AB, M_CACHEE_OB): New.
456 (M_LBE_OB, M_LBE_AB): New.
457 (M_LBUE_OB, M_LBUE_AB): New.
458 (M_LHE_OB, M_LHE_AB): New.
459 (M_LHUE_OB, M_LHUE_AB): New.
460 (M_LLE_AB, M_LLE_OB): New.
461 (M_LWE_OB, M_LWE_AB): New.
462 (M_LWLE_AB, M_LWLE_OB): New.
463 (M_LWRE_AB, M_LWRE_OB): New.
464 (M_PREFE_AB, M_PREFE_OB): New.
465 (M_SCE_AB, M_SCE_OB): New.
466 (M_SBE_OB, M_SBE_AB): New.
467 (M_SHE_OB, M_SHE_AB): New.
468 (M_SWE_OB, M_SWE_AB): New.
469 (M_SWLE_AB, M_SWLE_OB): New.
470 (M_SWRE_AB, M_SWRE_OB): New.
471 (MICROMIPSOP_SH_EVAOFFSET): Define.
472 (MICROMIPSOP_MASK_EVAOFFSET): Define.
474 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
476 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
478 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
480 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
482 2013-05-09 Andrew Pinski <apinski@cavium.com>
484 * mips.h (OP_MASK_CODE10): Correct definition.
485 (OP_SH_CODE10): Likewise.
486 Add a comment that "+J" is used now for OP_*CODE10.
487 (INSN_ASE_MASK): Update.
488 (INSN_VIRT): New macro.
489 (INSN_VIRT64): New macro
491 2013-05-02 Nick Clifton <nickc@redhat.com>
493 * msp430.h: Add patterns for MSP430X instructions.
495 2013-04-06 David S. Miller <davem@davemloft.net>
497 * sparc.h (F_PREFERRED): Define.
498 (F_PREF_ALIAS): Define.
500 2013-04-03 Nick Clifton <nickc@redhat.com>
502 * v850.h (V850_INVERSE_PCREL): Define.
504 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
507 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
509 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
512 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
514 * tic6xc-opcode-table.h: Add 16-bit insns.
515 * tic6x.h: Add support for 16-bit insns.
517 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
519 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
520 and mov.b/w/l Rs,@(d:32,ERd).
522 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
525 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
526 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
527 tic6x_operand_xregpair operand coding type.
528 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
529 opcode field, usu ORXREGD1324 for the src2 operand and remove the
532 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
535 * tic6x.h (enum tic6x_coding_method): Add
536 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
537 separately the msb and lsb of a register pair. This is needed to
538 encode the opcodes in the same way as TI assembler does.
539 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
540 and rsqrdp opcodes to use the new field coding types.
542 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
544 * arm.h (CRC_EXT_ARMV8): New constant.
545 (ARCH_CRC_ARMV8): New macro.
547 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
549 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
551 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
552 Andrew Jenner <andrew@codesourcery.com>
554 Based on patches from Altera Corporation.
558 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
560 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
562 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
565 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
567 2013-01-24 Nick Clifton <nickc@redhat.com>
569 * v850.h: Add e3v5 support.
571 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
573 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
575 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
577 * ppc.h (PPC_OPCODE_POWER8): New define.
578 (PPC_OPCODE_HTM): Likewise.
580 2013-01-10 Will Newton <will.newton@imgtec.com>
584 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
586 * cr16.h (make_instruction): Rename to cr16_make_instruction.
587 (match_opcode): Rename to cr16_match_opcode.
589 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
591 * mips.h: Add support for r5900 instructions including lq and sq.
593 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
595 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
596 (make_instruction,match_opcode): Added function prototypes.
597 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
599 2012-11-23 Alan Modra <amodra@gmail.com>
601 * ppc.h (ppc_parse_cpu): Update prototype.
603 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
605 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
606 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
608 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
610 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
612 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
614 * ia64.h (ia64_opnd): Add new operand types.
616 2012-08-21 David S. Miller <davem@davemloft.net>
618 * sparc.h (F3F4): New macro.
620 2012-08-13 Ian Bolton <ian.bolton@arm.com>
621 Laurent Desnogues <laurent.desnogues@arm.com>
622 Jim MacArthur <jim.macarthur@arm.com>
623 Marcus Shawcroft <marcus.shawcroft@arm.com>
624 Nigel Stephens <nigel.stephens@arm.com>
625 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
626 Richard Earnshaw <rearnsha@arm.com>
627 Sofiane Naci <sofiane.naci@arm.com>
628 Tejas Belagod <tejas.belagod@arm.com>
629 Yufeng Zhang <yufeng.zhang@arm.com>
631 * aarch64.h: New file.
633 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
634 Maciej W. Rozycki <macro@codesourcery.com>
636 * mips.h (mips_opcode): Add the exclusions field.
637 (OPCODE_IS_MEMBER): Remove macro.
638 (cpu_is_member): New inline function.
639 (opcode_is_member): Likewise.
641 2012-07-31 Chao-Ying Fu <fu@mips.com>
642 Catherine Moore <clm@codesourcery.com>
643 Maciej W. Rozycki <macro@codesourcery.com>
645 * mips.h: Document microMIPS DSP ASE usage.
646 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
647 microMIPS DSP ASE support.
648 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
649 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
650 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
651 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
652 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
653 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
654 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
656 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
658 * mips.h: Fix a typo in description.
660 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
662 * avr.h: (AVR_ISA_XCH): New define.
663 (AVR_ISA_XMEGA): Use it.
664 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
666 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
668 * m68hc11.h: Add XGate definitions.
669 (struct m68hc11_opcode): Add xg_mask field.
671 2012-05-14 Catherine Moore <clm@codesourcery.com>
672 Maciej W. Rozycki <macro@codesourcery.com>
673 Rhonda Wittels <rhonda@codesourcery.com>
675 * ppc.h (PPC_OPCODE_VLE): New definition.
676 (PPC_OP_SA): New macro.
677 (PPC_OP_SE_VLE): New macro.
678 (PPC_OP): Use a variable shift amount.
679 (powerpc_operand): Update comments.
680 (PPC_OPSHIFT_INV): New macro.
681 (PPC_OPERAND_CR): Replace with...
682 (PPC_OPERAND_CR_BIT): ...this and
683 (PPC_OPERAND_CR_REG): ...this.
686 2012-05-03 Sean Keys <skeys@ipdatasys.com>
688 * xgate.h: Header file for XGATE assembler.
690 2012-04-27 David S. Miller <davem@davemloft.net>
692 * sparc.h: Document new arg code' )' for crypto RS3
695 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
696 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
697 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
698 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
699 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
700 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
701 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
702 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
703 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
704 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
705 HWCAP_CBCOND, HWCAP_CRC32): New defines.
707 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
709 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
711 2012-02-27 Alan Modra <amodra@gmail.com>
713 * crx.h (cst4_map): Update declaration.
715 2012-02-25 Walter Lee <walt@tilera.com>
717 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
719 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
720 TILEPRO_OPC_LW_TLS_SN.
722 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
724 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
725 (XRELEASE_PREFIX_OPCODE): Likewise.
727 2011-12-08 Andrew Pinski <apinski@cavium.com>
728 Adam Nemet <anemet@caviumnetworks.com>
730 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
731 (INSN_OCTEON2): New macro.
732 (CPU_OCTEON2): New macro.
733 (OPCODE_IS_MEMBER): Add Octeon2.
735 2011-11-29 Andrew Pinski <apinski@cavium.com>
737 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
738 (INSN_OCTEONP): New macro.
739 (CPU_OCTEONP): New macro.
740 (OPCODE_IS_MEMBER): Add Octeon+.
741 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
743 2011-11-01 DJ Delorie <dj@redhat.com>
747 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
749 * mips.h: Fix a typo in description.
751 2011-09-21 David S. Miller <davem@davemloft.net>
753 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
754 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
755 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
756 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
758 2011-08-09 Chao-ying Fu <fu@mips.com>
759 Maciej W. Rozycki <macro@codesourcery.com>
761 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
762 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
763 (INSN_ASE_MASK): Add the MCU bit.
764 (INSN_MCU): New macro.
765 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
766 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
768 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
770 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
771 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
772 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
773 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
774 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
775 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
776 (INSN2_READ_GPR_MMN): Likewise.
777 (INSN2_READ_FPR_D): Change the bit used.
778 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
779 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
780 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
781 (INSN2_COND_BRANCH): Likewise.
782 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
783 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
784 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
785 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
786 (INSN2_MOD_GPR_MN): Likewise.
788 2011-08-05 David S. Miller <davem@davemloft.net>
790 * sparc.h: Document new format codes '4', '5', and '('.
791 (OPF_LOW4, RS3): New macros.
793 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
795 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
796 order of flags documented.
798 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
800 * mips.h: Clarify the description of microMIPS instruction
802 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
804 2011-07-24 Chao-ying Fu <fu@mips.com>
805 Maciej W. Rozycki <macro@codesourcery.com>
807 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
808 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
809 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
810 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
811 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
812 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
813 (OP_MASK_RS3, OP_SH_RS3): Likewise.
814 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
815 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
816 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
817 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
818 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
819 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
820 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
821 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
822 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
823 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
824 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
825 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
826 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
827 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
828 (INSN_WRITE_GPR_S): New macro.
829 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
830 (INSN2_READ_FPR_D): Likewise.
831 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
832 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
833 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
834 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
835 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
836 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
837 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
838 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
839 (CPU_MICROMIPS): New macro.
840 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
841 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
842 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
843 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
844 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
845 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
846 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
847 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
848 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
849 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
850 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
851 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
852 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
853 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
854 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
855 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
856 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
857 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
858 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
859 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
860 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
861 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
862 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
863 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
864 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
865 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
866 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
867 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
868 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
869 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
870 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
871 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
872 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
873 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
874 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
875 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
876 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
877 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
878 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
879 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
880 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
881 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
882 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
883 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
884 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
885 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
886 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
887 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
888 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
889 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
890 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
891 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
892 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
893 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
894 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
895 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
896 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
897 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
898 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
899 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
900 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
901 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
902 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
903 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
904 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
905 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
906 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
907 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
908 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
909 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
910 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
911 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
912 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
913 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
914 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
915 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
916 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
917 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
918 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
919 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
920 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
921 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
922 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
923 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
924 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
925 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
926 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
927 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
928 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
929 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
930 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
931 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
932 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
933 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
934 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
935 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
936 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
937 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
938 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
939 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
940 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
941 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
942 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
943 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
944 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
945 (micromips_opcodes): New declaration.
946 (bfd_micromips_num_opcodes): Likewise.
948 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
950 * mips.h (INSN_TRAP): Rename to...
951 (INSN_NO_DELAY_SLOT): ... this.
952 (INSN_SYNC): Remove macro.
954 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
956 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
957 a duplicate of AVR_ISA_SPM.
959 2011-07-01 Nick Clifton <nickc@redhat.com>
961 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
963 2011-06-18 Robin Getz <robin.getz@analog.com>
965 * bfin.h (is_macmod_signed): New func
967 2011-06-18 Mike Frysinger <vapier@gentoo.org>
969 * bfin.h (is_macmod_pmove): Add missing space before func args.
970 (is_macmod_hmove): Likewise.
972 2011-06-13 Walter Lee <walt@tilera.com>
974 * tilegx.h: New file.
975 * tilepro.h: New file.
977 2011-05-31 Paul Brook <paul@codesourcery.com>
979 * arm.h (ARM_ARCH_V7R_IDIV): Define.
981 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
983 * s390.h: Replace S390_OPERAND_REG_EVEN with
984 S390_OPERAND_REG_PAIR.
986 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
988 * s390.h: Add S390_OPCODE_REG_EVEN flag.
990 2011-04-18 Julian Brown <julian@codesourcery.com>
992 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
994 2011-04-11 Dan McDonald <dan@wellkeeper.com>
997 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
999 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1001 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1002 New instruction set flags.
1003 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1005 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1007 * mips.h (M_PREF_AB): New enum value.
1009 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1011 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1013 (is_macmod_pmove, is_macmod_hmove): New functions.
1015 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1017 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1019 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1021 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1022 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1024 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1027 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1030 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1033 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1035 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1037 * mips.h: Update commentary after last commit.
1039 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1041 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1042 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1043 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1045 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1047 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1049 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1051 * mips.h: Fix previous commit.
1053 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1055 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1056 (INSN_LOONGSON_3A): Clear bit 31.
1058 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1061 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1062 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1063 (ARM_ARCH_V6M_ONLY): New define.
1065 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1067 * mips.h (INSN_LOONGSON_3A): Defined.
1068 (CPU_LOONGSON_3A): Defined.
1069 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1071 2010-10-09 Matt Rice <ratmice@gmail.com>
1073 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1074 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1076 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1078 * arm.h (ARM_EXT_VIRT): New define.
1079 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1080 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1083 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1085 * arm.h (ARM_AEXT_ADIV): New define.
1086 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1088 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1090 * arm.h (ARM_EXT_OS): New define.
1091 (ARM_AEXT_V6SM): Likewise.
1092 (ARM_ARCH_V6SM): Likewise.
1094 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1096 * arm.h (ARM_EXT_MP): Add.
1097 (ARM_ARCH_V7A_MP): Likewise.
1099 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1101 * bfin.h: Declare pseudoChr structs/defines.
1103 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1105 * bfin.h: Strip trailing whitespace.
1107 2010-07-29 DJ Delorie <dj@redhat.com>
1109 * rx.h (RX_Operand_Type): Add TwoReg.
1110 (RX_Opcode_ID): Remove ediv and ediv2.
1112 2010-07-27 DJ Delorie <dj@redhat.com>
1114 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1116 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1117 Ina Pandit <ina.pandit@kpitcummins.com>
1119 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1120 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1121 PROCESSOR_V850E2_ALL.
1122 Remove PROCESSOR_V850EA support.
1123 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1124 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1125 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1126 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1127 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1128 V850_OPERAND_PERCENT.
1129 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1131 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1134 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1136 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1137 (MIPS16_INSN_BRANCH): Rename to...
1138 (MIPS16_INSN_COND_BRANCH): ... this.
1140 2010-07-03 Alan Modra <amodra@gmail.com>
1142 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1143 Renumber other PPC_OPCODE defines.
1145 2010-07-03 Alan Modra <amodra@gmail.com>
1147 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1149 2010-06-29 Alan Modra <amodra@gmail.com>
1151 * maxq.h: Delete file.
1153 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1155 * ppc.h (PPC_OPCODE_E500): Define.
1157 2010-05-26 Catherine Moore <clm@codesourcery.com>
1159 * opcode/mips.h (INSN_MIPS16): Remove.
1161 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1163 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1165 2010-04-15 Nick Clifton <nickc@redhat.com>
1167 * alpha.h: Update copyright notice to use GPLv3.
1173 * convex.h: Likewise.
1180 * h8300.h: Likewise.
1187 * m68hc11.h: Likewise.
1193 * mn10200.h: Likewise.
1194 * mn10300.h: Likewise.
1195 * msp430.h: Likewise.
1197 * ns32k.h: Likewise.
1199 * pdp11.h: Likewise.
1206 * score-datadep.h: Likewise.
1207 * score-inst.h: Likewise.
1208 * sparc.h: Likewise.
1209 * spu-insns.h: Likewise.
1211 * tic30.h: Likewise.
1212 * tic4x.h: Likewise.
1213 * tic54x.h: Likewise.
1214 * tic80.h: Likewise.
1218 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1220 * tic6x-control-registers.h, tic6x-insn-formats.h,
1221 tic6x-opcode-table.h, tic6x.h: New.
1223 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1225 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1227 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1229 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1231 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1233 * ia64.h (ia64_find_opcode): Remove argument name.
1234 (ia64_find_next_opcode): Likewise.
1235 (ia64_dis_opcode): Likewise.
1236 (ia64_free_opcode): Likewise.
1237 (ia64_find_dependency): Likewise.
1239 2009-11-22 Doug Evans <dje@sebabeach.org>
1241 * cgen.h: Include bfd_stdint.h.
1242 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1244 2009-11-18 Paul Brook <paul@codesourcery.com>
1246 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1248 2009-11-17 Paul Brook <paul@codesourcery.com>
1249 Daniel Jacobowitz <dan@codesourcery.com>
1251 * arm.h (ARM_EXT_V6_DSP): Define.
1252 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1253 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1255 2009-11-04 DJ Delorie <dj@redhat.com>
1257 * rx.h (rx_decode_opcode) (mvtipl): Add.
1258 (mvtcp, mvfcp, opecp): Remove.
1260 2009-11-02 Paul Brook <paul@codesourcery.com>
1262 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1263 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1264 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1265 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1266 FPU_ARCH_NEON_VFP_V4): Define.
1268 2009-10-23 Doug Evans <dje@sebabeach.org>
1270 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1271 * cgen.h: Update. Improve multi-inclusion macro name.
1273 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1275 * ppc.h (PPC_OPCODE_476): Define.
1277 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1279 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1281 2009-09-29 DJ Delorie <dj@redhat.com>
1285 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1287 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1289 2009-09-21 Ben Elliston <bje@au.ibm.com>
1291 * ppc.h (PPC_OPCODE_PPCA2): New.
1293 2009-09-05 Martin Thuresson <martin@mtme.org>
1295 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1297 2009-08-29 Martin Thuresson <martin@mtme.org>
1299 * tic30.h (template): Rename type template to
1300 insn_template. Updated code to use new name.
1301 * tic54x.h (template): Rename type template to
1304 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1306 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1308 2009-06-11 Anthony Green <green@moxielogic.com>
1310 * moxie.h (MOXIE_F3_PCREL): Define.
1311 (moxie_form3_opc_info): Grow.
1313 2009-06-06 Anthony Green <green@moxielogic.com>
1315 * moxie.h (MOXIE_F1_M): Define.
1317 2009-04-15 Anthony Green <green@moxielogic.com>
1321 2009-04-06 DJ Delorie <dj@redhat.com>
1323 * h8300.h: Add relaxation attributes to MOVA opcodes.
1325 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1327 * ppc.h (ppc_parse_cpu): Declare.
1329 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1331 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1332 and _IMM11 for mbitclr and mbitset.
1333 * score-datadep.h: Update dependency information.
1335 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1337 * ppc.h (PPC_OPCODE_POWER7): New.
1339 2009-02-06 Doug Evans <dje@google.com>
1341 * i386.h: Add comment regarding sse* insns and prefixes.
1343 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1345 * mips.h (INSN_XLR): Define.
1346 (INSN_CHIP_MASK): Update.
1348 (OPCODE_IS_MEMBER): Update.
1349 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1351 2009-01-28 Doug Evans <dje@google.com>
1353 * opcode/i386.h: Add multiple inclusion protection.
1354 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1355 (EDI_REG_NUM): New macros.
1356 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1357 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1358 (REX_PREFIX_P): New macro.
1360 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1362 * ppc.h (struct powerpc_opcode): New field "deprecated".
1363 (PPC_OPCODE_NOPOWER4): Delete.
1365 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1367 * mips.h: Define CPU_R14000, CPU_R16000.
1368 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1370 2008-11-18 Catherine Moore <clm@codesourcery.com>
1372 * arm.h (FPU_NEON_FP16): New.
1373 (FPU_ARCH_NEON_FP16): New.
1375 2008-11-06 Chao-ying Fu <fu@mips.com>
1377 * mips.h: Doucument '1' for 5-bit sync type.
1379 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1381 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1384 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1386 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1388 2008-07-30 Michael J. Eager <eager@eagercon.com>
1390 * ppc.h (PPC_OPCODE_405): Define.
1391 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1393 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1395 * ppc.h (ppc_cpu_t): New typedef.
1396 (struct powerpc_opcode <flags>): Use it.
1397 (struct powerpc_operand <insert, extract>): Likewise.
1398 (struct powerpc_macro <flags>): Likewise.
1400 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1402 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1403 Update comment before MIPS16 field descriptors to mention MIPS16.
1404 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1406 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1407 New bit masks and shift counts for cins and exts.
1409 * mips.h: Document new field descriptors +Q.
1410 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1412 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1414 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1415 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1417 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1419 * ppc.h: (PPC_OPCODE_E500MC): New.
1421 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1423 * i386.h (MAX_OPERANDS): Set to 5.
1424 (MAX_MNEM_SIZE): Changed to 20.
1426 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1428 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1430 2008-03-09 Paul Brook <paul@codesourcery.com>
1432 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1434 2008-03-04 Paul Brook <paul@codesourcery.com>
1436 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1437 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1438 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1440 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1441 Nick Clifton <nickc@redhat.com>
1444 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1445 with a 32-bit displacement but without the top bit of the 4th byte
1448 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1450 * cr16.h (cr16_num_optab): Declared.
1452 2008-02-14 Hakan Ardo <hakan@debian.org>
1455 * avr.h (AVR_ISA_2xxe): Define.
1457 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1459 * mips.h: Update copyright.
1460 (INSN_CHIP_MASK): New macro.
1461 (INSN_OCTEON): New macro.
1462 (CPU_OCTEON): New macro.
1463 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1465 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1467 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1469 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1471 * avr.h (AVR_ISA_USB162): Add new opcode set.
1472 (AVR_ISA_AVR3): Likewise.
1474 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1476 * mips.h (INSN_LOONGSON_2E): New.
1477 (INSN_LOONGSON_2F): New.
1478 (CPU_LOONGSON_2E): New.
1479 (CPU_LOONGSON_2F): New.
1480 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1482 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1484 * mips.h (INSN_ISA*): Redefine certain values as an
1485 enumeration. Update comments.
1486 (mips_isa_table): New.
1487 (ISA_MIPS*): Redefine to match enumeration.
1488 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1491 2007-08-08 Ben Elliston <bje@au.ibm.com>
1493 * ppc.h (PPC_OPCODE_PPCPS): New.
1495 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1497 * m68k.h: Document j K & E.
1499 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1501 * cr16.h: New file for CR16 target.
1503 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1505 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1507 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1509 * m68k.h (mcfisa_c): New.
1510 (mcfusp, mcf_mask): Adjust.
1512 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1514 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1515 (num_powerpc_operands): Declare.
1516 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1517 (PPC_OPERAND_PLUS1): Define.
1519 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1521 * i386.h (REX_MODE64): Renamed to ...
1523 (REX_EXTX): Renamed to ...
1525 (REX_EXTY): Renamed to ...
1527 (REX_EXTZ): Renamed to ...
1530 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1532 * i386.h: Add entries from config/tc-i386.h and move tables
1533 to opcodes/i386-opc.h.
1535 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1537 * i386.h (FloatDR): Removed.
1538 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1540 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1542 * spu-insns.h: Add soma double-float insns.
1544 2007-02-20 Thiemo Seufer <ths@mips.com>
1545 Chao-Ying Fu <fu@mips.com>
1547 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1548 (INSN_DSPR2): Add flag for DSP R2 instructions.
1549 (M_BALIGN): New macro.
1551 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1553 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1554 and Seg3ShortFrom with Shortform.
1556 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1559 * i386.h (i386_optab): Put the real "test" before the pseudo
1562 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1564 * m68k.h (m68010up): OR fido_a.
1566 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1568 * m68k.h (fido_a): New.
1570 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1572 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1573 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1576 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1578 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1580 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1582 * score-inst.h (enum score_insn_type): Add Insn_internal.
1584 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1585 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1586 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1587 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1588 Alan Modra <amodra@bigpond.net.au>
1590 * spu-insns.h: New file.
1593 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1595 * ppc.h (PPC_OPCODE_CELL): Define.
1597 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1599 * i386.h : Modify opcode to support for the change in POPCNT opcode
1600 in amdfam10 architecture.
1602 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1604 * i386.h: Replace CpuMNI with CpuSSSE3.
1606 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1607 Joseph Myers <joseph@codesourcery.com>
1608 Ian Lance Taylor <ian@wasabisystems.com>
1609 Ben Elliston <bje@wasabisystems.com>
1611 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1613 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1615 * score-datadep.h: New file.
1616 * score-inst.h: New file.
1618 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1620 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1621 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1622 movdq2q and movq2dq.
1624 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1625 Michael Meissner <michael.meissner@amd.com>
1627 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1629 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1631 * i386.h (i386_optab): Add "nop" with memory reference.
1633 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1635 * i386.h (i386_optab): Update comment for 64bit NOP.
1637 2006-06-06 Ben Elliston <bje@au.ibm.com>
1638 Anton Blanchard <anton@samba.org>
1640 * ppc.h (PPC_OPCODE_POWER6): Define.
1643 2006-06-05 Thiemo Seufer <ths@mips.com>
1645 * mips.h: Improve description of MT flags.
1647 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1649 * m68k.h (mcf_mask): Define.
1651 2006-05-05 Thiemo Seufer <ths@mips.com>
1652 David Ung <davidu@mips.com>
1654 * mips.h (enum): Add macro M_CACHE_AB.
1656 2006-05-04 Thiemo Seufer <ths@mips.com>
1657 Nigel Stephens <nigel@mips.com>
1658 David Ung <davidu@mips.com>
1660 * mips.h: Add INSN_SMARTMIPS define.
1662 2006-04-30 Thiemo Seufer <ths@mips.com>
1663 David Ung <davidu@mips.com>
1665 * mips.h: Defines udi bits and masks. Add description of
1666 characters which may appear in the args field of udi
1669 2006-04-26 Thiemo Seufer <ths@networkno.de>
1671 * mips.h: Improve comments describing the bitfield instruction
1674 2006-04-26 Julian Brown <julian@codesourcery.com>
1676 * arm.h (FPU_VFP_EXT_V3): Define constant.
1677 (FPU_NEON_EXT_V1): Likewise.
1678 (FPU_VFP_HARD): Update.
1679 (FPU_VFP_V3): Define macro.
1680 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1682 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1684 * avr.h (AVR_ISA_PWMx): New.
1686 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1688 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1689 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1690 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1691 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1692 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1694 2006-03-10 Paul Brook <paul@codesourcery.com>
1696 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1698 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1700 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1701 first. Correct mask of bb "B" opcode.
1703 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1705 * i386.h (i386_optab): Support Intel Merom New Instructions.
1707 2006-02-24 Paul Brook <paul@codesourcery.com>
1709 * arm.h: Add V7 feature bits.
1711 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1713 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1715 2006-01-31 Paul Brook <paul@codesourcery.com>
1716 Richard Earnshaw <rearnsha@arm.com>
1718 * arm.h: Use ARM_CPU_FEATURE.
1719 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1720 (arm_feature_set): Change to a structure.
1721 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1722 ARM_FEATURE): New macros.
1724 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1726 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1727 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1728 (ADD_PC_INCR_OPCODE): Don't define.
1730 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1733 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1735 2005-11-14 David Ung <davidu@mips.com>
1737 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1738 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1739 save/restore encoding of the args field.
1741 2005-10-28 Dave Brolley <brolley@redhat.com>
1743 Contribute the following changes:
1744 2005-02-16 Dave Brolley <brolley@redhat.com>
1746 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1747 cgen_isa_mask_* to cgen_bitset_*.
1750 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1752 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1753 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1754 (CGEN_CPU_TABLE): Make isas a ponter.
1756 2003-09-29 Dave Brolley <brolley@redhat.com>
1758 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1759 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1760 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1762 2002-12-13 Dave Brolley <brolley@redhat.com>
1764 * cgen.h (symcat.h): #include it.
1765 (cgen-bitset.h): #include it.
1766 (CGEN_ATTR_VALUE_TYPE): Now a union.
1767 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1768 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1769 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1770 * cgen-bitset.h: New file.
1772 2005-09-30 Catherine Moore <clm@cm00re.com>
1776 2005-10-24 Jan Beulich <jbeulich@novell.com>
1778 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1781 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1783 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1784 Add FLAG_STRICT to pa10 ftest opcode.
1786 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1788 * hppa.h (pa_opcodes): Remove lha entries.
1790 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1792 * hppa.h (FLAG_STRICT): Revise comment.
1793 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1794 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1797 2005-09-30 Catherine Moore <clm@cm00re.com>
1801 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1803 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1805 2005-09-06 Chao-ying Fu <fu@mips.com>
1807 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1808 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1810 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1811 (INSN_ASE_MASK): Update to include INSN_MT.
1812 (INSN_MT): New define for MT ASE.
1814 2005-08-25 Chao-ying Fu <fu@mips.com>
1816 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1817 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1818 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1819 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1820 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1821 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1823 (INSN_DSP): New define for DSP ASE.
1825 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1829 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1831 * ppc.h (PPC_OPCODE_E300): Define.
1833 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1835 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1837 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1840 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1843 2005-07-27 Jan Beulich <jbeulich@novell.com>
1845 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1846 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1847 Add movq-s as 64-bit variants of movd-s.
1849 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1851 * hppa.h: Fix punctuation in comment.
1853 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1854 implicit space-register addressing. Set space-register bits on opcodes
1855 using implicit space-register addressing. Add various missing pa20
1856 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1857 space-register addressing. Use "fE" instead of "fe" in various
1860 2005-07-18 Jan Beulich <jbeulich@novell.com>
1862 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1864 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1866 * i386.h (i386_optab): Support Intel VMX Instructions.
1868 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1870 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1872 2005-07-05 Jan Beulich <jbeulich@novell.com>
1874 * i386.h (i386_optab): Add new insns.
1876 2005-07-01 Nick Clifton <nickc@redhat.com>
1878 * sparc.h: Add typedefs to structure declarations.
1880 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1883 * i386.h (i386_optab): Update comments for 64bit addressing on
1884 mov. Allow 64bit addressing for mov and movq.
1886 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1888 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1889 respectively, in various floating-point load and store patterns.
1891 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1893 * hppa.h (FLAG_STRICT): Correct comment.
1894 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1895 PA 2.0 mneumonics when equivalent. Entries with cache control
1896 completers now require PA 1.1. Adjust whitespace.
1898 2005-05-19 Anton Blanchard <anton@samba.org>
1900 * ppc.h (PPC_OPCODE_POWER5): Define.
1902 2005-05-10 Nick Clifton <nickc@redhat.com>
1904 * Update the address and phone number of the FSF organization in
1905 the GPL notices in the following files:
1906 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1907 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1908 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1909 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1910 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1911 tic54x.h, tic80.h, v850.h, vax.h
1913 2005-05-09 Jan Beulich <jbeulich@novell.com>
1915 * i386.h (i386_optab): Add ht and hnt.
1917 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1919 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1920 Add xcrypt-ctr. Provide aliases without hyphens.
1922 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1924 Moved from ../ChangeLog
1926 2005-04-12 Paul Brook <paul@codesourcery.com>
1927 * m88k.h: Rename psr macros to avoid conflicts.
1929 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1930 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1931 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1932 and ARM_ARCH_V6ZKT2.
1934 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1935 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1936 Remove redundant instruction types.
1937 (struct argument): X_op - new field.
1938 (struct cst4_entry): Remove.
1939 (no_op_insn): Declare.
1941 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1942 * crx.h (enum argtype): Rename types, remove unused types.
1944 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1945 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1946 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1947 (enum operand_type): Rearrange operands, edit comments.
1948 replace us<N> with ui<N> for unsigned immediate.
1949 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1950 displacements (respectively).
1951 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1952 (instruction type): Add NO_TYPE_INS.
1953 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1954 (operand_entry): New field - 'flags'.
1955 (operand flags): New.
1957 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1958 * crx.h (operand_type): Remove redundant types i3, i4,
1960 Add new unsigned immediate types us3, us4, us5, us16.
1962 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1964 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1965 adjust them accordingly.
1967 2005-04-01 Jan Beulich <jbeulich@novell.com>
1969 * i386.h (i386_optab): Add rdtscp.
1971 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1973 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1974 between memory and segment register. Allow movq for moving between
1975 general-purpose register and segment register.
1977 2005-02-09 Jan Beulich <jbeulich@novell.com>
1980 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1981 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1984 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1986 * m68k.h (m68008, m68ec030, m68882): Remove.
1988 (cpu_m68k, cpu_cf): New.
1989 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1990 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1992 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1994 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1995 * cgen.h (enum cgen_parse_operand_type): Add
1996 CGEN_PARSE_OPERAND_SYMBOLIC.
1998 2005-01-21 Fred Fish <fnf@specifixinc.com>
2000 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2001 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2002 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2004 2005-01-19 Fred Fish <fnf@specifixinc.com>
2006 * mips.h (struct mips_opcode): Add new pinfo2 member.
2007 (INSN_ALIAS): New define for opcode table entries that are
2008 specific instances of another entry, such as 'move' for an 'or'
2009 with a zero operand.
2010 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2011 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2013 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2015 * mips.h (CPU_RM9000): Define.
2016 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2018 2004-11-25 Jan Beulich <jbeulich@novell.com>
2020 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2021 to/from test registers are illegal in 64-bit mode. Add missing
2022 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2023 (previously one had to explicitly encode a rex64 prefix). Re-enable
2024 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2025 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2027 2004-11-23 Jan Beulich <jbeulich@novell.com>
2029 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2030 available only with SSE2. Change the MMX additions introduced by SSE
2031 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2032 instructions by their now designated identifier (since combining i686
2033 and 3DNow! does not really imply 3DNow!A).
2035 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2037 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2038 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2040 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2041 Vineet Sharma <vineets@noida.hcltech.com>
2043 * maxq.h: New file: Disassembly information for the maxq port.
2045 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2047 * i386.h (i386_optab): Put back "movzb".
2049 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2051 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2052 comments. Remove member cris_ver_sim. Add members
2053 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2054 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2055 (struct cris_support_reg, struct cris_cond15): New types.
2056 (cris_conds15): Declare.
2057 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2058 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2059 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2060 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2061 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2062 SIZE_FIELD_UNSIGNED.
2064 2004-11-04 Jan Beulich <jbeulich@novell.com>
2066 * i386.h (sldx_Suf): Remove.
2067 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2068 (q_FP): Define, implying no REX64.
2069 (x_FP, sl_FP): Imply FloatMF.
2070 (i386_optab): Split reg and mem forms of moving from segment registers
2071 so that the memory forms can ignore the 16-/32-bit operand size
2072 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2073 all non-floating-point instructions. Unite 32- and 64-bit forms of
2074 movsx, movzx, and movd. Adjust floating point operations for the above
2075 changes to the *FP macros. Add DefaultSize to floating point control
2076 insns operating on larger memory ranges. Remove left over comments
2077 hinting at certain insns being Intel-syntax ones where the ones
2078 actually meant are already gone.
2080 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2082 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2085 2004-09-30 Paul Brook <paul@codesourcery.com>
2087 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2088 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2090 2004-09-11 Theodore A. Roth <troth@openavr.org>
2092 * avr.h: Add support for
2093 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2095 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2097 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2099 2004-08-24 Dmitry Diky <diwil@spec.ru>
2101 * msp430.h (msp430_opc): Add new instructions.
2102 (msp430_rcodes): Declare new instructions.
2103 (msp430_hcodes): Likewise..
2105 2004-08-13 Nick Clifton <nickc@redhat.com>
2108 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2111 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2113 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2115 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2117 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2119 2004-07-21 Jan Beulich <jbeulich@novell.com>
2121 * i386.h: Adjust instruction descriptions to better match the
2124 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2126 * arm.h: Remove all old content. Replace with architecture defines
2127 from gas/config/tc-arm.c.
2129 2004-07-09 Andreas Schwab <schwab@suse.de>
2131 * m68k.h: Fix comment.
2133 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2137 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2139 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2141 2004-05-24 Peter Barada <peter@the-baradas.com>
2143 * m68k.h: Add 'size' to m68k_opcode.
2145 2004-05-05 Peter Barada <peter@the-baradas.com>
2147 * m68k.h: Switch from ColdFire chip name to core variant.
2149 2004-04-22 Peter Barada <peter@the-baradas.com>
2151 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2152 descriptions for new EMAC cases.
2153 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2154 handle Motorola MAC syntax.
2155 Allow disassembly of ColdFire V4e object files.
2157 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2159 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2161 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2163 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2165 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2167 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2169 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2171 * i386.h (i386_optab): Added xstore/xcrypt insns.
2173 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2175 * h8300.h (32bit ldc/stc): Add relaxing support.
2177 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2179 * h8300.h (BITOP): Pass MEMRELAX flag.
2181 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2183 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2186 For older changes see ChangeLog-9103
2188 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2190 Copying and distribution of this file, with or without modification,
2191 are permitted in any medium without royalty provided the copyright
2192 notice and this notice are preserved.
2198 version-control: never