include/opcode/ChangeLog

   1 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
   2
   3         * mips.h: Define CPU_R14000, CPU_R16000.
   4         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
   5
   6 2008-11-18  Catherine Moore  <clm@codesourcery.com>
   7
   8         * arm.h (FPU_NEON_FP16): New.
   9         (FPU_ARCH_NEON_FP16): New.
  10
  11 2008-11-06  Chao-ying Fu  <fu@mips.com>
  12
  13         * mips.h: Doucument '1' for 5-bit sync type.
  14
  15 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  18         IA64_RS_CR.
  19
  20 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  21
  22         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  23
  24 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  25
  26         * ppc.h (PPC_OPCODE_405): Define.
  27         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  28
  29 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  30
  31         * ppc.h (ppc_cpu_t): New typedef.
  32         (struct powerpc_opcode <flags>): Use it.
  33         (struct powerpc_operand <insert, extract>): Likewise.
  34         (struct powerpc_macro <flags>): Likewise.
  35
  36 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  37
  38         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  39         Update comment before MIPS16 field descriptors to mention MIPS16.
  40         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  41         BBIT.
  42         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  43         New bit masks and shift counts for cins and exts.
  44
  45         * mips.h: Document new field descriptors +Q.
  46         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  47
  48 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  49
  50         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  51         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  52
  53 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  54
  55         * ppc.h: (PPC_OPCODE_E500MC): New.
  56
  57 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         * i386.h (MAX_OPERANDS): Set to 5.
  60         (MAX_MNEM_SIZE): Changed to 20.
  61
  62 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  63
  64         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  65
  66 2008-03-09  Paul Brook  <paul@codesourcery.com>
  67
  68         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  69
  70 2008-03-04  Paul Brook  <paul@codesourcery.com>
  71
  72         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  73         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
  74         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  75
  76 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  77             Nick Clifton  <nickc@redhat.com>
  78
  79         PR 3134
  80         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
  81         with a 32-bit displacement but without the top bit of the 4th byte
  82         set.
  83
  84 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  85
  86         * cr16.h (cr16_num_optab): Declared.
  87
  88 2008-02-14  Hakan Ardo  <hakan@debian.org>
  89
  90         PR gas/2626
  91         * avr.h (AVR_ISA_2xxe): Define.
  92
  93 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  94
  95         * mips.h: Update copyright.
  96         (INSN_CHIP_MASK): New macro.
  97         (INSN_OCTEON): New macro.
  98         (CPU_OCTEON): New macro.
  99         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 100
 101 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 102
 103         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 104
 105 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 106
 107         * avr.h (AVR_ISA_USB162): Add new opcode set.
 108         (AVR_ISA_AVR3): Likewise.
 109
 110 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 111
 112         * mips.h (INSN_LOONGSON_2E): New.
 113         (INSN_LOONGSON_2F): New.
 114         (CPU_LOONGSON_2E): New.
 115         (CPU_LOONGSON_2F): New.
 116         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 117
 118 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 119
 120         * mips.h (INSN_ISA*): Redefine certain values as an
 121         enumeration.  Update comments.
 122         (mips_isa_table): New.
 123         (ISA_MIPS*): Redefine to match enumeration.
 124         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 125         values.
 126
 127 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 128
 129         * ppc.h (PPC_OPCODE_PPCPS): New.
 130
 131 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 132
 133         * m68k.h: Document j K & E.
 134
 135 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 136
 137         * cr16.h: New file for CR16 target.
 138
 139 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 140
 141         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 142
 143 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 144
 145         * m68k.h (mcfisa_c): New.
 146         (mcfusp, mcf_mask): Adjust.
 147
 148 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 149
 150         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 151         (num_powerpc_operands): Declare.
 152         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 153         (PPC_OPERAND_PLUS1): Define.
 154
 155 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         * i386.h (REX_MODE64): Renamed to ...
 158         (REX_W): This.
 159         (REX_EXTX): Renamed to ...
 160         (REX_R): This.
 161         (REX_EXTY): Renamed to ...
 162         (REX_X): This.
 163         (REX_EXTZ): Renamed to ...
 164         (REX_B): This.
 165
 166 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * i386.h: Add entries from config/tc-i386.h and move tables
 169         to opcodes/i386-opc.h.
 170
 171 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         * i386.h (FloatDR): Removed.
 174         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 175
 176 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 177
 178         * spu-insns.h: Add soma double-float insns.
 179
 180 2007-02-20  Thiemo Seufer  <ths@mips.com>
 181             Chao-Ying Fu  <fu@mips.com>
 182
 183         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 184         (INSN_DSPR2): Add flag for DSP R2 instructions.
 185         (M_BALIGN): New macro.
 186
 187 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 188
 189         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 190         and Seg3ShortFrom with Shortform.
 191
 192 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         PR gas/4027
 195         * i386.h (i386_optab): Put the real "test" before the pseudo
 196         one.
 197
 198 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 199
 200         * m68k.h (m68010up): OR fido_a.
 201
 202 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 203
 204         * m68k.h (fido_a): New.
 205
 206 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 207
 208         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 209         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 210         values.
 211
 212 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 215
 216 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 217
 218         * score-inst.h (enum score_insn_type): Add Insn_internal.
 219
 220 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 221             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 222             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 223             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 224             Alan Modra  <amodra@bigpond.net.au>
 225
 226         * spu-insns.h: New file.
 227         * spu.h: New file.
 228
 229 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 230
 231         * ppc.h (PPC_OPCODE_CELL): Define.
 232
 233 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 234
 235         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 236         in amdfam10 architecture.
 237
 238 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386.h: Replace CpuMNI with CpuSSSE3.
 241
 242 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 243             Joseph Myers  <joseph@codesourcery.com>
 244             Ian Lance Taylor  <ian@wasabisystems.com>
 245             Ben Elliston  <bje@wasabisystems.com>
 246
 247         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 248
 249 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 250
 251         * score-datadep.h: New file.
 252         * score-inst.h: New file.
 253
 254 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 255
 256         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 257         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 258         movdq2q and movq2dq.
 259
 260 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 261            Michael Meissner             <michael.meissner@amd.com>
 262
 263         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 264
 265 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 266
 267         * i386.h (i386_optab): Add "nop" with memory reference.
 268
 269 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         * i386.h (i386_optab): Update comment for 64bit NOP.
 272
 273 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 274             Anton Blanchard  <anton@samba.org>
 275
 276         * ppc.h (PPC_OPCODE_POWER6): Define.
 277         Adjust whitespace.
 278
 279 2006-06-05  Thiemo Seufer  <ths@mips.com>
 280
 281         * mips.h: Improve description of MT flags.
 282
 283 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 284
 285         * m68k.h (mcf_mask): Define.
 286
 287 2006-05-05  Thiemo Seufer  <ths@mips.com>
 288             David Ung  <davidu@mips.com>
 289
 290         * mips.h (enum): Add macro M_CACHE_AB.
 291
 292 2006-05-04  Thiemo Seufer  <ths@mips.com>
 293             Nigel Stephens  <nigel@mips.com>
 294             David Ung  <davidu@mips.com>
 295
 296         * mips.h: Add INSN_SMARTMIPS define.
 297
 298 2006-04-30  Thiemo Seufer  <ths@mips.com>
 299             David Ung  <davidu@mips.com>
 300
 301         * mips.h: Defines udi bits and masks.  Add description of
 302         characters which may appear in the args field of udi
 303         instructions.
 304
 305 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 306
 307         * mips.h: Improve comments describing the bitfield instruction
 308         fields.
 309
 310 2006-04-26  Julian Brown  <julian@codesourcery.com>
 311
 312         * arm.h (FPU_VFP_EXT_V3): Define constant.
 313         (FPU_NEON_EXT_V1): Likewise.
 314         (FPU_VFP_HARD): Update.
 315         (FPU_VFP_V3): Define macro.
 316         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 317
 318 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 319
 320         * avr.h (AVR_ISA_PWMx): New.
 321
 322 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 323
 324         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 325         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 326         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 327         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 328         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 329
 330 2006-03-10  Paul Brook  <paul@codesourcery.com>
 331
 332         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 333
 334 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 335
 336         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 337         first.  Correct mask of bb "B" opcode.
 338
 339 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 340
 341         * i386.h (i386_optab): Support Intel Merom New Instructions.
 342
 343 2006-02-24  Paul Brook  <paul@codesourcery.com>
 344
 345         * arm.h: Add V7 feature bits.
 346
 347 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 350
 351 2006-01-31  Paul Brook  <paul@codesourcery.com>
 352         Richard Earnshaw <rearnsha@arm.com>
 353
 354         * arm.h: Use ARM_CPU_FEATURE.
 355         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 356         (arm_feature_set): Change to a structure.
 357         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 358         ARM_FEATURE): New macros.
 359
 360 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 361
 362         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 363         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 364         (ADD_PC_INCR_OPCODE): Don't define.
 365
 366 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         PR gas/1874
 369         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 370
 371 2005-11-14  David Ung  <davidu@mips.com>
 372
 373         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 374         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 375         save/restore encoding of the args field.
 376
 377 2005-10-28  Dave Brolley  <brolley@redhat.com>
 378
 379         Contribute the following changes:
 380         2005-02-16  Dave Brolley  <brolley@redhat.com>
 381
 382         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 383         cgen_isa_mask_* to cgen_bitset_*.
 384         * cgen.h: Likewise.
 385
 386         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 387
 388         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 389         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 390         (CGEN_CPU_TABLE): Make isas a ponter.
 391
 392         2003-09-29  Dave Brolley  <brolley@redhat.com>
 393
 394         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 395         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 396         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 397
 398         2002-12-13  Dave Brolley  <brolley@redhat.com>
 399
 400         * cgen.h (symcat.h): #include it.
 401         (cgen-bitset.h): #include it.
 402         (CGEN_ATTR_VALUE_TYPE): Now a union.
 403         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 404         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 405         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 406         * cgen-bitset.h: New file.
 407
 408 2005-09-30  Catherine Moore  <clm@cm00re.com>
 409
 410         * bfin.h: New file.
 411
 412 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 413
 414         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 415         indirect operands.
 416
 417 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 418
 419         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 420         Add FLAG_STRICT to pa10 ftest opcode.
 421
 422 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (pa_opcodes): Remove lha entries.
 425
 426 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 427
 428         * hppa.h (FLAG_STRICT): Revise comment.
 429         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 430         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 431         entries for "fdc".
 432
 433 2005-09-30  Catherine Moore  <clm@cm00re.com>
 434
 435         * bfin.h: New file.
 436
 437 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 438
 439         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 440
 441 2005-09-06  Chao-ying Fu  <fu@mips.com>
 442
 443         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 444         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 445         define.
 446         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 447         (INSN_ASE_MASK): Update to include INSN_MT.
 448         (INSN_MT): New define for MT ASE.
 449
 450 2005-08-25  Chao-ying Fu  <fu@mips.com>
 451
 452         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 453         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 454         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 455         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 456         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 457         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 458         instructions.
 459         (INSN_DSP): New define for DSP ASE.
 460
 461 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 462
 463         * a29k.h: Delete.
 464
 465 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 466
 467         * ppc.h (PPC_OPCODE_E300): Define.
 468
 469 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 470
 471         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 472
 473 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 474
 475         PR gas/336
 476         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 477         and pitlb.
 478
 479 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 480
 481         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 482         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 483         Add movq-s as 64-bit variants of movd-s.
 484
 485 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 486
 487         * hppa.h: Fix punctuation in comment.
 488
 489         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 490         implicit space-register addressing.  Set space-register bits on opcodes
 491         using implicit space-register addressing.  Add various missing pa20
 492         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 493         space-register addressing.  Use "fE" instead of "fe" in various
 494         fstw opcodes.
 495
 496 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 497
 498         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 499
 500 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 501
 502         * i386.h (i386_optab): Support Intel VMX Instructions.
 503
 504 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 505
 506         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 507
 508 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 509
 510         * i386.h (i386_optab): Add new insns.
 511
 512 2005-07-01  Nick Clifton  <nickc@redhat.com>
 513
 514         * sparc.h: Add typedefs to structure declarations.
 515
 516 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         PR 1013
 519         * i386.h (i386_optab): Update comments for 64bit addressing on
 520         mov. Allow 64bit addressing for mov and movq.
 521
 522 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 523
 524         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 525         respectively, in various floating-point load and store patterns.
 526
 527 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 528
 529         * hppa.h (FLAG_STRICT): Correct comment.
 530         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 531         PA 2.0 mneumonics when equivalent.  Entries with cache control
 532         completers now require PA 1.1.  Adjust whitespace.
 533
 534 2005-05-19  Anton Blanchard  <anton@samba.org>
 535
 536         * ppc.h (PPC_OPCODE_POWER5): Define.
 537
 538 2005-05-10  Nick Clifton  <nickc@redhat.com>
 539
 540         * Update the address and phone number of the FSF organization in
 541         the GPL notices in the following files:
 542         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 543         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 544         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 545         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 546         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 547         tic54x.h, tic80.h, v850.h, vax.h
 548
 549 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 550
 551         * i386.h (i386_optab): Add ht and hnt.
 552
 553 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 554
 555         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 556         Add xcrypt-ctr.  Provide aliases without hyphens.
 557
 558 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 559
 560         Moved from ../ChangeLog
 561
 562         2005-04-12  Paul Brook  <paul@codesourcery.com>
 563         * m88k.h: Rename psr macros to avoid conflicts.
 564
 565         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 566         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 567         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 568         and ARM_ARCH_V6ZKT2.
 569
 570         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 571         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 572         Remove redundant instruction types.
 573         (struct argument): X_op - new field.
 574         (struct cst4_entry): Remove.
 575         (no_op_insn): Declare.
 576
 577         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 578         * crx.h (enum argtype): Rename types, remove unused types.
 579
 580         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 581         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 582         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 583         (enum operand_type): Rearrange operands, edit comments.
 584         replace us<N> with ui<N> for unsigned immediate.
 585         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 586         displacements (respectively).
 587         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 588         (instruction type): Add NO_TYPE_INS.
 589         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 590         (operand_entry): New field - 'flags'.
 591         (operand flags): New.
 592
 593         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 594         * crx.h (operand_type): Remove redundant types i3, i4,
 595         i5, i8, i12.
 596         Add new unsigned immediate types us3, us4, us5, us16.
 597
 598 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 599
 600         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 601         adjust them accordingly.
 602
 603 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 604
 605         * i386.h (i386_optab): Add rdtscp.
 606
 607 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 610         between memory and segment register. Allow movq for moving between
 611         general-purpose register and segment register.
 612
 613 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 614
 615         PR gas/707
 616         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 617         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 618         fnstsw.
 619
 620 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 621
 622         * m68k.h (m68008, m68ec030, m68882): Remove.
 623         (m68k_mask): New.
 624         (cpu_m68k, cpu_cf): New.
 625         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 626         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 627
 628 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 629
 630         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 631         * cgen.h (enum cgen_parse_operand_type): Add
 632         CGEN_PARSE_OPERAND_SYMBOLIC.
 633
 634 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 635
 636         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 637         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 638         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 639
 640 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 641
 642         * mips.h (struct mips_opcode): Add new pinfo2 member.
 643         (INSN_ALIAS): New define for opcode table entries that are
 644         specific instances of another entry, such as 'move' for an 'or'
 645         with a zero operand.
 646         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 647         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 648
 649 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 650
 651         * mips.h (CPU_RM9000): Define.
 652         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 653
 654 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 655
 656         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 657         to/from test registers are illegal in 64-bit mode. Add missing
 658         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 659         (previously one had to explicitly encode a rex64 prefix). Re-enable
 660         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 661         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 662
 663 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 664
 665         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 666         available only with SSE2. Change the MMX additions introduced by SSE
 667         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 668         instructions by their now designated identifier (since combining i686
 669         and 3DNow! does not really imply 3DNow!A).
 670
 671 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 672
 673         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 674         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 675
 676 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 677             Vineet Sharma      <vineets@noida.hcltech.com>
 678
 679         * maxq.h: New file: Disassembly information for the maxq port.
 680
 681 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386.h (i386_optab): Put back "movzb".
 684
 685 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 686
 687         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 688         comments.  Remove member cris_ver_sim.  Add members
 689         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 690         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 691         (struct cris_support_reg, struct cris_cond15): New types.
 692         (cris_conds15): Declare.
 693         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 694         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 695         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 696         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 697         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 698         SIZE_FIELD_UNSIGNED.
 699
 700 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 701
 702         * i386.h (sldx_Suf): Remove.
 703         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 704         (q_FP): Define, implying no REX64.
 705         (x_FP, sl_FP): Imply FloatMF.
 706         (i386_optab): Split reg and mem forms of moving from segment registers
 707         so that the memory forms can ignore the 16-/32-bit operand size
 708         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 709         all non-floating-point instructions. Unite 32- and 64-bit forms of
 710         movsx, movzx, and movd. Adjust floating point operations for the above
 711         changes to the *FP macros. Add DefaultSize to floating point control
 712         insns operating on larger memory ranges. Remove left over comments
 713         hinting at certain insns being Intel-syntax ones where the ones
 714         actually meant are already gone.
 715
 716 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 717
 718         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 719         instruction type.
 720
 721 2004-09-30  Paul Brook  <paul@codesourcery.com>
 722
 723         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 724         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 725
 726 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 727
 728         * avr.h: Add support for
 729         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 730
 731 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 732
 733         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 734
 735 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 736
 737         * msp430.h (msp430_opc): Add new instructions.
 738         (msp430_rcodes): Declare new instructions.
 739         (msp430_hcodes): Likewise..
 740
 741 2004-08-13  Nick Clifton  <nickc@redhat.com>
 742
 743         PR/301
 744         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 745         processors.
 746
 747 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 748
 749         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 750
 751 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 754
 755 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 756
 757         * i386.h: Adjust instruction descriptions to better match the
 758         specification.
 759
 760 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 761
 762         * arm.h: Remove all old content.  Replace with architecture defines
 763         from gas/config/tc-arm.c.
 764
 765 2004-07-09  Andreas Schwab  <schwab@suse.de>
 766
 767         * m68k.h: Fix comment.
 768
 769 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 770
 771         * crx.h: New file.
 772
 773 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 774
 775         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 776
 777 2004-05-24  Peter Barada  <peter@the-baradas.com>
 778
 779         * m68k.h: Add 'size' to m68k_opcode.
 780
 781 2004-05-05  Peter Barada  <peter@the-baradas.com>
 782
 783         * m68k.h: Switch from ColdFire chip name to core variant.
 784
 785 2004-04-22  Peter Barada  <peter@the-baradas.com>
 786
 787         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 788         descriptions for new EMAC cases.
 789         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 790         handle Motorola MAC syntax.
 791         Allow disassembly of ColdFire V4e object files.
 792
 793 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 794
 795         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 796
 797 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 798
 799         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 800
 801 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 802
 803         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 804
 805 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 806
 807         * i386.h (i386_optab): Added xstore/xcrypt insns.
 808
 809 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 810
 811         * h8300.h (32bit ldc/stc): Add relaxing support.
 812
 813 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 814
 815         * h8300.h (BITOP): Pass MEMRELAX flag.
 816
 817 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 818
 819         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 820         except for the H8S.
 821
 822 For older changes see ChangeLog-9103
 823 \f
 824 Local Variables:
 825 mode: change-log
 826 left-margin: 8
 827 fill-column: 74
 828 version-control: never
 829 End: