1 2013-01-10 Will Newton <will.newton@imgtec.com>
5 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
7 * cr16.h (make_instruction): Rename to cr16_make_instruction.
8 (match_opcode): Rename to cr16_match_opcode.
10 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
12 * mips.h: Add support for r5900 instructions including lq and sq.
14 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
16 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
17 (make_instruction,match_opcode): Added function prototypes.
18 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
20 2012-11-23 Alan Modra <amodra@gmail.com>
22 * ppc.h (ppc_parse_cpu): Update prototype.
24 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
26 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
27 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
29 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
31 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
33 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
35 * ia64.h (ia64_opnd): Add new operand types.
37 2012-08-21 David S. Miller <davem@davemloft.net>
39 * sparc.h (F3F4): New macro.
41 2012-08-13 Ian Bolton <ian.bolton@arm.com>
42 Laurent Desnogues <laurent.desnogues@arm.com>
43 Jim MacArthur <jim.macarthur@arm.com>
44 Marcus Shawcroft <marcus.shawcroft@arm.com>
45 Nigel Stephens <nigel.stephens@arm.com>
46 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
47 Richard Earnshaw <rearnsha@arm.com>
48 Sofiane Naci <sofiane.naci@arm.com>
49 Tejas Belagod <tejas.belagod@arm.com>
50 Yufeng Zhang <yufeng.zhang@arm.com>
52 * aarch64.h: New file.
54 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
55 Maciej W. Rozycki <macro@codesourcery.com>
57 * mips.h (mips_opcode): Add the exclusions field.
58 (OPCODE_IS_MEMBER): Remove macro.
59 (cpu_is_member): New inline function.
60 (opcode_is_member): Likewise.
62 2012-07-31 Chao-Ying Fu <fu@mips.com>
63 Catherine Moore <clm@codesourcery.com>
64 Maciej W. Rozycki <macro@codesourcery.com>
66 * mips.h: Document microMIPS DSP ASE usage.
67 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
68 microMIPS DSP ASE support.
69 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
70 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
71 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
72 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
73 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
74 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
75 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
77 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
79 * mips.h: Fix a typo in description.
81 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
83 * avr.h: (AVR_ISA_XCH): New define.
84 (AVR_ISA_XMEGA): Use it.
85 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
87 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
89 * m68hc11.h: Add XGate definitions.
90 (struct m68hc11_opcode): Add xg_mask field.
92 2012-05-14 Catherine Moore <clm@codesourcery.com>
93 Maciej W. Rozycki <macro@codesourcery.com>
94 Rhonda Wittels <rhonda@codesourcery.com>
96 * ppc.h (PPC_OPCODE_VLE): New definition.
97 (PPC_OP_SA): New macro.
98 (PPC_OP_SE_VLE): New macro.
99 (PPC_OP): Use a variable shift amount.
100 (powerpc_operand): Update comments.
101 (PPC_OPSHIFT_INV): New macro.
102 (PPC_OPERAND_CR): Replace with...
103 (PPC_OPERAND_CR_BIT): ...this and
104 (PPC_OPERAND_CR_REG): ...this.
107 2012-05-03 Sean Keys <skeys@ipdatasys.com>
109 * xgate.h: Header file for XGATE assembler.
111 2012-04-27 David S. Miller <davem@davemloft.net>
113 * sparc.h: Document new arg code' )' for crypto RS3
116 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
117 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
118 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
119 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
120 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
121 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
122 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
123 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
124 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
125 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
126 HWCAP_CBCOND, HWCAP_CRC32): New defines.
128 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
130 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
132 2012-02-27 Alan Modra <amodra@gmail.com>
134 * crx.h (cst4_map): Update declaration.
136 2012-02-25 Walter Lee <walt@tilera.com>
138 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
140 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
141 TILEPRO_OPC_LW_TLS_SN.
143 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
145 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
146 (XRELEASE_PREFIX_OPCODE): Likewise.
148 2011-12-08 Andrew Pinski <apinski@cavium.com>
149 Adam Nemet <anemet@caviumnetworks.com>
151 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
152 (INSN_OCTEON2): New macro.
153 (CPU_OCTEON2): New macro.
154 (OPCODE_IS_MEMBER): Add Octeon2.
156 2011-11-29 Andrew Pinski <apinski@cavium.com>
158 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
159 (INSN_OCTEONP): New macro.
160 (CPU_OCTEONP): New macro.
161 (OPCODE_IS_MEMBER): Add Octeon+.
162 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
164 2011-11-01 DJ Delorie <dj@redhat.com>
168 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
170 * mips.h: Fix a typo in description.
172 2011-09-21 David S. Miller <davem@davemloft.net>
174 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
175 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
176 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
177 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
179 2011-08-09 Chao-ying Fu <fu@mips.com>
180 Maciej W. Rozycki <macro@codesourcery.com>
182 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
183 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
184 (INSN_ASE_MASK): Add the MCU bit.
185 (INSN_MCU): New macro.
186 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
187 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
189 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
191 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
192 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
193 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
194 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
195 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
196 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
197 (INSN2_READ_GPR_MMN): Likewise.
198 (INSN2_READ_FPR_D): Change the bit used.
199 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
200 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
201 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
202 (INSN2_COND_BRANCH): Likewise.
203 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
204 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
205 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
206 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
207 (INSN2_MOD_GPR_MN): Likewise.
209 2011-08-05 David S. Miller <davem@davemloft.net>
211 * sparc.h: Document new format codes '4', '5', and '('.
212 (OPF_LOW4, RS3): New macros.
214 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
216 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
217 order of flags documented.
219 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
221 * mips.h: Clarify the description of microMIPS instruction
223 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
225 2011-07-24 Chao-ying Fu <fu@mips.com>
226 Maciej W. Rozycki <macro@codesourcery.com>
228 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
229 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
230 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
231 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
232 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
233 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
234 (OP_MASK_RS3, OP_SH_RS3): Likewise.
235 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
236 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
237 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
238 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
239 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
240 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
241 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
242 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
243 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
244 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
245 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
246 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
247 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
248 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
249 (INSN_WRITE_GPR_S): New macro.
250 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
251 (INSN2_READ_FPR_D): Likewise.
252 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
253 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
254 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
255 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
256 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
257 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
258 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
259 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
260 (CPU_MICROMIPS): New macro.
261 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
262 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
263 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
264 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
265 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
266 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
267 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
268 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
269 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
270 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
271 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
272 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
273 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
274 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
275 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
276 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
277 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
278 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
279 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
280 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
281 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
282 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
283 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
284 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
285 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
286 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
287 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
288 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
289 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
290 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
291 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
292 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
293 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
294 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
295 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
296 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
297 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
298 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
299 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
300 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
301 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
302 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
303 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
304 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
305 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
306 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
307 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
308 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
309 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
310 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
311 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
312 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
313 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
314 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
315 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
316 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
317 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
318 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
319 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
320 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
321 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
322 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
323 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
324 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
325 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
326 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
327 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
328 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
329 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
330 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
331 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
332 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
333 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
334 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
335 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
336 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
337 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
338 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
339 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
340 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
341 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
342 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
343 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
344 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
345 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
346 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
347 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
348 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
349 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
350 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
351 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
352 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
353 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
354 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
355 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
356 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
357 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
358 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
359 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
360 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
361 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
362 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
363 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
364 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
365 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
366 (micromips_opcodes): New declaration.
367 (bfd_micromips_num_opcodes): Likewise.
369 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
371 * mips.h (INSN_TRAP): Rename to...
372 (INSN_NO_DELAY_SLOT): ... this.
373 (INSN_SYNC): Remove macro.
375 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
377 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
378 a duplicate of AVR_ISA_SPM.
380 2011-07-01 Nick Clifton <nickc@redhat.com>
382 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
384 2011-06-18 Robin Getz <robin.getz@analog.com>
386 * bfin.h (is_macmod_signed): New func
388 2011-06-18 Mike Frysinger <vapier@gentoo.org>
390 * bfin.h (is_macmod_pmove): Add missing space before func args.
391 (is_macmod_hmove): Likewise.
393 2011-06-13 Walter Lee <walt@tilera.com>
395 * tilegx.h: New file.
396 * tilepro.h: New file.
398 2011-05-31 Paul Brook <paul@codesourcery.com>
400 * arm.h (ARM_ARCH_V7R_IDIV): Define.
402 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
404 * s390.h: Replace S390_OPERAND_REG_EVEN with
405 S390_OPERAND_REG_PAIR.
407 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
409 * s390.h: Add S390_OPCODE_REG_EVEN flag.
411 2011-04-18 Julian Brown <julian@codesourcery.com>
413 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
415 2011-04-11 Dan McDonald <dan@wellkeeper.com>
418 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
420 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
422 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
423 New instruction set flags.
424 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
426 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
428 * mips.h (M_PREF_AB): New enum value.
430 2011-02-12 Mike Frysinger <vapier@gentoo.org>
432 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
434 (is_macmod_pmove, is_macmod_hmove): New functions.
436 2011-02-11 Mike Frysinger <vapier@gentoo.org>
438 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
440 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
442 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
443 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
445 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
448 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
451 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
454 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
456 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
458 * mips.h: Update commentary after last commit.
460 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
462 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
463 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
464 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
466 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
468 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
470 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
472 * mips.h: Fix previous commit.
474 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
476 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
477 (INSN_LOONGSON_3A): Clear bit 31.
479 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
482 * arm.h (ARM_AEXT_V6M_ONLY): New define.
483 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
484 (ARM_ARCH_V6M_ONLY): New define.
486 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
488 * mips.h (INSN_LOONGSON_3A): Defined.
489 (CPU_LOONGSON_3A): Defined.
490 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
492 2010-10-09 Matt Rice <ratmice@gmail.com>
494 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
495 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
497 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
499 * arm.h (ARM_EXT_VIRT): New define.
500 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
501 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
504 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
506 * arm.h (ARM_AEXT_ADIV): New define.
507 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
509 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
511 * arm.h (ARM_EXT_OS): New define.
512 (ARM_AEXT_V6SM): Likewise.
513 (ARM_ARCH_V6SM): Likewise.
515 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
517 * arm.h (ARM_EXT_MP): Add.
518 (ARM_ARCH_V7A_MP): Likewise.
520 2010-09-22 Mike Frysinger <vapier@gentoo.org>
522 * bfin.h: Declare pseudoChr structs/defines.
524 2010-09-21 Mike Frysinger <vapier@gentoo.org>
526 * bfin.h: Strip trailing whitespace.
528 2010-07-29 DJ Delorie <dj@redhat.com>
530 * rx.h (RX_Operand_Type): Add TwoReg.
531 (RX_Opcode_ID): Remove ediv and ediv2.
533 2010-07-27 DJ Delorie <dj@redhat.com>
535 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
537 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
538 Ina Pandit <ina.pandit@kpitcummins.com>
540 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
541 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
542 PROCESSOR_V850E2_ALL.
543 Remove PROCESSOR_V850EA support.
544 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
545 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
546 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
547 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
548 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
549 V850_OPERAND_PERCENT.
550 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
552 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
555 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
557 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
558 (MIPS16_INSN_BRANCH): Rename to...
559 (MIPS16_INSN_COND_BRANCH): ... this.
561 2010-07-03 Alan Modra <amodra@gmail.com>
563 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
564 Renumber other PPC_OPCODE defines.
566 2010-07-03 Alan Modra <amodra@gmail.com>
568 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
570 2010-06-29 Alan Modra <amodra@gmail.com>
572 * maxq.h: Delete file.
574 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
576 * ppc.h (PPC_OPCODE_E500): Define.
578 2010-05-26 Catherine Moore <clm@codesourcery.com>
580 * opcode/mips.h (INSN_MIPS16): Remove.
582 2010-04-21 Joseph Myers <joseph@codesourcery.com>
584 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
586 2010-04-15 Nick Clifton <nickc@redhat.com>
588 * alpha.h: Update copyright notice to use GPLv3.
594 * convex.h: Likewise.
608 * m68hc11.h: Likewise.
614 * mn10200.h: Likewise.
615 * mn10300.h: Likewise.
616 * msp430.h: Likewise.
627 * score-datadep.h: Likewise.
628 * score-inst.h: Likewise.
630 * spu-insns.h: Likewise.
634 * tic54x.h: Likewise.
639 2010-03-25 Joseph Myers <joseph@codesourcery.com>
641 * tic6x-control-registers.h, tic6x-insn-formats.h,
642 tic6x-opcode-table.h, tic6x.h: New.
644 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
646 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
648 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
650 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
652 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
654 * ia64.h (ia64_find_opcode): Remove argument name.
655 (ia64_find_next_opcode): Likewise.
656 (ia64_dis_opcode): Likewise.
657 (ia64_free_opcode): Likewise.
658 (ia64_find_dependency): Likewise.
660 2009-11-22 Doug Evans <dje@sebabeach.org>
662 * cgen.h: Include bfd_stdint.h.
663 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
665 2009-11-18 Paul Brook <paul@codesourcery.com>
667 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
669 2009-11-17 Paul Brook <paul@codesourcery.com>
670 Daniel Jacobowitz <dan@codesourcery.com>
672 * arm.h (ARM_EXT_V6_DSP): Define.
673 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
674 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
676 2009-11-04 DJ Delorie <dj@redhat.com>
678 * rx.h (rx_decode_opcode) (mvtipl): Add.
679 (mvtcp, mvfcp, opecp): Remove.
681 2009-11-02 Paul Brook <paul@codesourcery.com>
683 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
684 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
685 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
686 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
687 FPU_ARCH_NEON_VFP_V4): Define.
689 2009-10-23 Doug Evans <dje@sebabeach.org>
691 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
692 * cgen.h: Update. Improve multi-inclusion macro name.
694 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
696 * ppc.h (PPC_OPCODE_476): Define.
698 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
700 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
702 2009-09-29 DJ Delorie <dj@redhat.com>
706 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
708 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
710 2009-09-21 Ben Elliston <bje@au.ibm.com>
712 * ppc.h (PPC_OPCODE_PPCA2): New.
714 2009-09-05 Martin Thuresson <martin@mtme.org>
716 * ia64.h (struct ia64_operand): Renamed member class to op_class.
718 2009-08-29 Martin Thuresson <martin@mtme.org>
720 * tic30.h (template): Rename type template to
721 insn_template. Updated code to use new name.
722 * tic54x.h (template): Rename type template to
725 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
727 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
729 2009-06-11 Anthony Green <green@moxielogic.com>
731 * moxie.h (MOXIE_F3_PCREL): Define.
732 (moxie_form3_opc_info): Grow.
734 2009-06-06 Anthony Green <green@moxielogic.com>
736 * moxie.h (MOXIE_F1_M): Define.
738 2009-04-15 Anthony Green <green@moxielogic.com>
742 2009-04-06 DJ Delorie <dj@redhat.com>
744 * h8300.h: Add relaxation attributes to MOVA opcodes.
746 2009-03-10 Alan Modra <amodra@bigpond.net.au>
748 * ppc.h (ppc_parse_cpu): Declare.
750 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
752 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
753 and _IMM11 for mbitclr and mbitset.
754 * score-datadep.h: Update dependency information.
756 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
758 * ppc.h (PPC_OPCODE_POWER7): New.
760 2009-02-06 Doug Evans <dje@google.com>
762 * i386.h: Add comment regarding sse* insns and prefixes.
764 2009-02-03 Sandip Matte <sandip@rmicorp.com>
766 * mips.h (INSN_XLR): Define.
767 (INSN_CHIP_MASK): Update.
769 (OPCODE_IS_MEMBER): Update.
770 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
772 2009-01-28 Doug Evans <dje@google.com>
774 * opcode/i386.h: Add multiple inclusion protection.
775 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
776 (EDI_REG_NUM): New macros.
777 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
778 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
779 (REX_PREFIX_P): New macro.
781 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
783 * ppc.h (struct powerpc_opcode): New field "deprecated".
784 (PPC_OPCODE_NOPOWER4): Delete.
786 2008-11-28 Joshua Kinard <kumba@gentoo.org>
788 * mips.h: Define CPU_R14000, CPU_R16000.
789 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
791 2008-11-18 Catherine Moore <clm@codesourcery.com>
793 * arm.h (FPU_NEON_FP16): New.
794 (FPU_ARCH_NEON_FP16): New.
796 2008-11-06 Chao-ying Fu <fu@mips.com>
798 * mips.h: Doucument '1' for 5-bit sync type.
800 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
802 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
805 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
807 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
809 2008-07-30 Michael J. Eager <eager@eagercon.com>
811 * ppc.h (PPC_OPCODE_405): Define.
812 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
814 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
816 * ppc.h (ppc_cpu_t): New typedef.
817 (struct powerpc_opcode <flags>): Use it.
818 (struct powerpc_operand <insert, extract>): Likewise.
819 (struct powerpc_macro <flags>): Likewise.
821 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
823 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
824 Update comment before MIPS16 field descriptors to mention MIPS16.
825 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
827 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
828 New bit masks and shift counts for cins and exts.
830 * mips.h: Document new field descriptors +Q.
831 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
833 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
835 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
836 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
838 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
840 * ppc.h: (PPC_OPCODE_E500MC): New.
842 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
844 * i386.h (MAX_OPERANDS): Set to 5.
845 (MAX_MNEM_SIZE): Changed to 20.
847 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
849 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
851 2008-03-09 Paul Brook <paul@codesourcery.com>
853 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
855 2008-03-04 Paul Brook <paul@codesourcery.com>
857 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
858 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
859 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
861 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
862 Nick Clifton <nickc@redhat.com>
865 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
866 with a 32-bit displacement but without the top bit of the 4th byte
869 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
871 * cr16.h (cr16_num_optab): Declared.
873 2008-02-14 Hakan Ardo <hakan@debian.org>
876 * avr.h (AVR_ISA_2xxe): Define.
878 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
880 * mips.h: Update copyright.
881 (INSN_CHIP_MASK): New macro.
882 (INSN_OCTEON): New macro.
883 (CPU_OCTEON): New macro.
884 (OPCODE_IS_MEMBER): Handle Octeon instructions.
886 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
888 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
890 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
892 * avr.h (AVR_ISA_USB162): Add new opcode set.
893 (AVR_ISA_AVR3): Likewise.
895 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
897 * mips.h (INSN_LOONGSON_2E): New.
898 (INSN_LOONGSON_2F): New.
899 (CPU_LOONGSON_2E): New.
900 (CPU_LOONGSON_2F): New.
901 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
903 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
905 * mips.h (INSN_ISA*): Redefine certain values as an
906 enumeration. Update comments.
907 (mips_isa_table): New.
908 (ISA_MIPS*): Redefine to match enumeration.
909 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
912 2007-08-08 Ben Elliston <bje@au.ibm.com>
914 * ppc.h (PPC_OPCODE_PPCPS): New.
916 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
918 * m68k.h: Document j K & E.
920 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
922 * cr16.h: New file for CR16 target.
924 2007-05-02 Alan Modra <amodra@bigpond.net.au>
926 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
928 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
930 * m68k.h (mcfisa_c): New.
931 (mcfusp, mcf_mask): Adjust.
933 2007-04-20 Alan Modra <amodra@bigpond.net.au>
935 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
936 (num_powerpc_operands): Declare.
937 (PPC_OPERAND_SIGNED et al): Redefine as hex.
938 (PPC_OPERAND_PLUS1): Define.
940 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
942 * i386.h (REX_MODE64): Renamed to ...
944 (REX_EXTX): Renamed to ...
946 (REX_EXTY): Renamed to ...
948 (REX_EXTZ): Renamed to ...
951 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
953 * i386.h: Add entries from config/tc-i386.h and move tables
954 to opcodes/i386-opc.h.
956 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
958 * i386.h (FloatDR): Removed.
959 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
961 2007-03-01 Alan Modra <amodra@bigpond.net.au>
963 * spu-insns.h: Add soma double-float insns.
965 2007-02-20 Thiemo Seufer <ths@mips.com>
966 Chao-Ying Fu <fu@mips.com>
968 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
969 (INSN_DSPR2): Add flag for DSP R2 instructions.
970 (M_BALIGN): New macro.
972 2007-02-14 Alan Modra <amodra@bigpond.net.au>
974 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
975 and Seg3ShortFrom with Shortform.
977 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
980 * i386.h (i386_optab): Put the real "test" before the pseudo
983 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
985 * m68k.h (m68010up): OR fido_a.
987 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
989 * m68k.h (fido_a): New.
991 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
993 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
994 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
997 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
999 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1001 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1003 * score-inst.h (enum score_insn_type): Add Insn_internal.
1005 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1006 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1007 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1008 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1009 Alan Modra <amodra@bigpond.net.au>
1011 * spu-insns.h: New file.
1014 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1016 * ppc.h (PPC_OPCODE_CELL): Define.
1018 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1020 * i386.h : Modify opcode to support for the change in POPCNT opcode
1021 in amdfam10 architecture.
1023 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1025 * i386.h: Replace CpuMNI with CpuSSSE3.
1027 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1028 Joseph Myers <joseph@codesourcery.com>
1029 Ian Lance Taylor <ian@wasabisystems.com>
1030 Ben Elliston <bje@wasabisystems.com>
1032 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1034 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1036 * score-datadep.h: New file.
1037 * score-inst.h: New file.
1039 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1041 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1042 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1043 movdq2q and movq2dq.
1045 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1046 Michael Meissner <michael.meissner@amd.com>
1048 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1050 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1052 * i386.h (i386_optab): Add "nop" with memory reference.
1054 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1056 * i386.h (i386_optab): Update comment for 64bit NOP.
1058 2006-06-06 Ben Elliston <bje@au.ibm.com>
1059 Anton Blanchard <anton@samba.org>
1061 * ppc.h (PPC_OPCODE_POWER6): Define.
1064 2006-06-05 Thiemo Seufer <ths@mips.com>
1066 * mips.h: Improve description of MT flags.
1068 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1070 * m68k.h (mcf_mask): Define.
1072 2006-05-05 Thiemo Seufer <ths@mips.com>
1073 David Ung <davidu@mips.com>
1075 * mips.h (enum): Add macro M_CACHE_AB.
1077 2006-05-04 Thiemo Seufer <ths@mips.com>
1078 Nigel Stephens <nigel@mips.com>
1079 David Ung <davidu@mips.com>
1081 * mips.h: Add INSN_SMARTMIPS define.
1083 2006-04-30 Thiemo Seufer <ths@mips.com>
1084 David Ung <davidu@mips.com>
1086 * mips.h: Defines udi bits and masks. Add description of
1087 characters which may appear in the args field of udi
1090 2006-04-26 Thiemo Seufer <ths@networkno.de>
1092 * mips.h: Improve comments describing the bitfield instruction
1095 2006-04-26 Julian Brown <julian@codesourcery.com>
1097 * arm.h (FPU_VFP_EXT_V3): Define constant.
1098 (FPU_NEON_EXT_V1): Likewise.
1099 (FPU_VFP_HARD): Update.
1100 (FPU_VFP_V3): Define macro.
1101 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1103 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1105 * avr.h (AVR_ISA_PWMx): New.
1107 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1109 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1110 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1111 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1112 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1113 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1115 2006-03-10 Paul Brook <paul@codesourcery.com>
1117 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1119 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1121 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1122 first. Correct mask of bb "B" opcode.
1124 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1126 * i386.h (i386_optab): Support Intel Merom New Instructions.
1128 2006-02-24 Paul Brook <paul@codesourcery.com>
1130 * arm.h: Add V7 feature bits.
1132 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1134 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1136 2006-01-31 Paul Brook <paul@codesourcery.com>
1137 Richard Earnshaw <rearnsha@arm.com>
1139 * arm.h: Use ARM_CPU_FEATURE.
1140 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1141 (arm_feature_set): Change to a structure.
1142 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1143 ARM_FEATURE): New macros.
1145 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1147 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1148 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1149 (ADD_PC_INCR_OPCODE): Don't define.
1151 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1154 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1156 2005-11-14 David Ung <davidu@mips.com>
1158 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1159 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1160 save/restore encoding of the args field.
1162 2005-10-28 Dave Brolley <brolley@redhat.com>
1164 Contribute the following changes:
1165 2005-02-16 Dave Brolley <brolley@redhat.com>
1167 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1168 cgen_isa_mask_* to cgen_bitset_*.
1171 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1173 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1174 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1175 (CGEN_CPU_TABLE): Make isas a ponter.
1177 2003-09-29 Dave Brolley <brolley@redhat.com>
1179 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1180 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1181 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1183 2002-12-13 Dave Brolley <brolley@redhat.com>
1185 * cgen.h (symcat.h): #include it.
1186 (cgen-bitset.h): #include it.
1187 (CGEN_ATTR_VALUE_TYPE): Now a union.
1188 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1189 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1190 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1191 * cgen-bitset.h: New file.
1193 2005-09-30 Catherine Moore <clm@cm00re.com>
1197 2005-10-24 Jan Beulich <jbeulich@novell.com>
1199 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1202 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1204 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1205 Add FLAG_STRICT to pa10 ftest opcode.
1207 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1209 * hppa.h (pa_opcodes): Remove lha entries.
1211 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1213 * hppa.h (FLAG_STRICT): Revise comment.
1214 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1215 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1218 2005-09-30 Catherine Moore <clm@cm00re.com>
1222 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1224 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1226 2005-09-06 Chao-ying Fu <fu@mips.com>
1228 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1229 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1231 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1232 (INSN_ASE_MASK): Update to include INSN_MT.
1233 (INSN_MT): New define for MT ASE.
1235 2005-08-25 Chao-ying Fu <fu@mips.com>
1237 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1238 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1239 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1240 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1241 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1242 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1244 (INSN_DSP): New define for DSP ASE.
1246 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1250 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1252 * ppc.h (PPC_OPCODE_E300): Define.
1254 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1256 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1258 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1261 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1264 2005-07-27 Jan Beulich <jbeulich@novell.com>
1266 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1267 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1268 Add movq-s as 64-bit variants of movd-s.
1270 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1272 * hppa.h: Fix punctuation in comment.
1274 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1275 implicit space-register addressing. Set space-register bits on opcodes
1276 using implicit space-register addressing. Add various missing pa20
1277 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1278 space-register addressing. Use "fE" instead of "fe" in various
1281 2005-07-18 Jan Beulich <jbeulich@novell.com>
1283 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1285 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1287 * i386.h (i386_optab): Support Intel VMX Instructions.
1289 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1291 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1293 2005-07-05 Jan Beulich <jbeulich@novell.com>
1295 * i386.h (i386_optab): Add new insns.
1297 2005-07-01 Nick Clifton <nickc@redhat.com>
1299 * sparc.h: Add typedefs to structure declarations.
1301 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1304 * i386.h (i386_optab): Update comments for 64bit addressing on
1305 mov. Allow 64bit addressing for mov and movq.
1307 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1309 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1310 respectively, in various floating-point load and store patterns.
1312 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1314 * hppa.h (FLAG_STRICT): Correct comment.
1315 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1316 PA 2.0 mneumonics when equivalent. Entries with cache control
1317 completers now require PA 1.1. Adjust whitespace.
1319 2005-05-19 Anton Blanchard <anton@samba.org>
1321 * ppc.h (PPC_OPCODE_POWER5): Define.
1323 2005-05-10 Nick Clifton <nickc@redhat.com>
1325 * Update the address and phone number of the FSF organization in
1326 the GPL notices in the following files:
1327 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1328 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1329 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1330 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1331 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1332 tic54x.h, tic80.h, v850.h, vax.h
1334 2005-05-09 Jan Beulich <jbeulich@novell.com>
1336 * i386.h (i386_optab): Add ht and hnt.
1338 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1340 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1341 Add xcrypt-ctr. Provide aliases without hyphens.
1343 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1345 Moved from ../ChangeLog
1347 2005-04-12 Paul Brook <paul@codesourcery.com>
1348 * m88k.h: Rename psr macros to avoid conflicts.
1350 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1351 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1352 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1353 and ARM_ARCH_V6ZKT2.
1355 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1356 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1357 Remove redundant instruction types.
1358 (struct argument): X_op - new field.
1359 (struct cst4_entry): Remove.
1360 (no_op_insn): Declare.
1362 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1363 * crx.h (enum argtype): Rename types, remove unused types.
1365 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1366 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1367 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1368 (enum operand_type): Rearrange operands, edit comments.
1369 replace us<N> with ui<N> for unsigned immediate.
1370 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1371 displacements (respectively).
1372 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1373 (instruction type): Add NO_TYPE_INS.
1374 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1375 (operand_entry): New field - 'flags'.
1376 (operand flags): New.
1378 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1379 * crx.h (operand_type): Remove redundant types i3, i4,
1381 Add new unsigned immediate types us3, us4, us5, us16.
1383 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1385 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1386 adjust them accordingly.
1388 2005-04-01 Jan Beulich <jbeulich@novell.com>
1390 * i386.h (i386_optab): Add rdtscp.
1392 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1394 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1395 between memory and segment register. Allow movq for moving between
1396 general-purpose register and segment register.
1398 2005-02-09 Jan Beulich <jbeulich@novell.com>
1401 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1402 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1405 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1407 * m68k.h (m68008, m68ec030, m68882): Remove.
1409 (cpu_m68k, cpu_cf): New.
1410 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1411 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1413 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1415 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1416 * cgen.h (enum cgen_parse_operand_type): Add
1417 CGEN_PARSE_OPERAND_SYMBOLIC.
1419 2005-01-21 Fred Fish <fnf@specifixinc.com>
1421 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1422 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1423 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1425 2005-01-19 Fred Fish <fnf@specifixinc.com>
1427 * mips.h (struct mips_opcode): Add new pinfo2 member.
1428 (INSN_ALIAS): New define for opcode table entries that are
1429 specific instances of another entry, such as 'move' for an 'or'
1430 with a zero operand.
1431 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1432 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1434 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1436 * mips.h (CPU_RM9000): Define.
1437 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1439 2004-11-25 Jan Beulich <jbeulich@novell.com>
1441 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1442 to/from test registers are illegal in 64-bit mode. Add missing
1443 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1444 (previously one had to explicitly encode a rex64 prefix). Re-enable
1445 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1446 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1448 2004-11-23 Jan Beulich <jbeulich@novell.com>
1450 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1451 available only with SSE2. Change the MMX additions introduced by SSE
1452 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1453 instructions by their now designated identifier (since combining i686
1454 and 3DNow! does not really imply 3DNow!A).
1456 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1458 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1459 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1461 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1462 Vineet Sharma <vineets@noida.hcltech.com>
1464 * maxq.h: New file: Disassembly information for the maxq port.
1466 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1468 * i386.h (i386_optab): Put back "movzb".
1470 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1472 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1473 comments. Remove member cris_ver_sim. Add members
1474 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1475 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1476 (struct cris_support_reg, struct cris_cond15): New types.
1477 (cris_conds15): Declare.
1478 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1479 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1480 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1481 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1482 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1483 SIZE_FIELD_UNSIGNED.
1485 2004-11-04 Jan Beulich <jbeulich@novell.com>
1487 * i386.h (sldx_Suf): Remove.
1488 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1489 (q_FP): Define, implying no REX64.
1490 (x_FP, sl_FP): Imply FloatMF.
1491 (i386_optab): Split reg and mem forms of moving from segment registers
1492 so that the memory forms can ignore the 16-/32-bit operand size
1493 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1494 all non-floating-point instructions. Unite 32- and 64-bit forms of
1495 movsx, movzx, and movd. Adjust floating point operations for the above
1496 changes to the *FP macros. Add DefaultSize to floating point control
1497 insns operating on larger memory ranges. Remove left over comments
1498 hinting at certain insns being Intel-syntax ones where the ones
1499 actually meant are already gone.
1501 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1503 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1506 2004-09-30 Paul Brook <paul@codesourcery.com>
1508 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1509 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1511 2004-09-11 Theodore A. Roth <troth@openavr.org>
1513 * avr.h: Add support for
1514 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1516 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1518 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1520 2004-08-24 Dmitry Diky <diwil@spec.ru>
1522 * msp430.h (msp430_opc): Add new instructions.
1523 (msp430_rcodes): Declare new instructions.
1524 (msp430_hcodes): Likewise..
1526 2004-08-13 Nick Clifton <nickc@redhat.com>
1529 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1532 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1534 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1536 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1538 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1540 2004-07-21 Jan Beulich <jbeulich@novell.com>
1542 * i386.h: Adjust instruction descriptions to better match the
1545 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1547 * arm.h: Remove all old content. Replace with architecture defines
1548 from gas/config/tc-arm.c.
1550 2004-07-09 Andreas Schwab <schwab@suse.de>
1552 * m68k.h: Fix comment.
1554 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1558 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1560 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1562 2004-05-24 Peter Barada <peter@the-baradas.com>
1564 * m68k.h: Add 'size' to m68k_opcode.
1566 2004-05-05 Peter Barada <peter@the-baradas.com>
1568 * m68k.h: Switch from ColdFire chip name to core variant.
1570 2004-04-22 Peter Barada <peter@the-baradas.com>
1572 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1573 descriptions for new EMAC cases.
1574 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1575 handle Motorola MAC syntax.
1576 Allow disassembly of ColdFire V4e object files.
1578 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1580 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1582 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1584 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1586 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1588 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1590 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1592 * i386.h (i386_optab): Added xstore/xcrypt insns.
1594 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1596 * h8300.h (32bit ldc/stc): Add relaxing support.
1598 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1600 * h8300.h (BITOP): Pass MEMRELAX flag.
1602 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1604 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1607 For older changes see ChangeLog-9103
1609 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1611 Copying and distribution of this file, with or without modification,
1612 are permitted in any medium without royalty provided the copyright
1613 notice and this notice are preserved.
1619 version-control: never