1 2012-04-27 David S. Miller <davem@davemloft.net>
3 * sparc.h: Document new arg code' )' for crypto RS3
6 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
7 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
8 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
9 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
10 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
11 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
12 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
13 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
14 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
15 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
16 HWCAP_CBCOND, HWCAP_CRC32): New defines.
18 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
20 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
22 2012-02-27 Alan Modra <amodra@gmail.com>
24 * crx.h (cst4_map): Update declaration.
26 2012-02-25 Walter Lee <walt@tilera.com>
28 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
30 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
31 TILEPRO_OPC_LW_TLS_SN.
33 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
35 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
36 (XRELEASE_PREFIX_OPCODE): Likewise.
38 2011-12-08 Andrew Pinski <apinski@cavium.com>
39 Adam Nemet <anemet@caviumnetworks.com>
41 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
42 (INSN_OCTEON2): New macro.
43 (CPU_OCTEON2): New macro.
44 (OPCODE_IS_MEMBER): Add Octeon2.
46 2011-11-29 Andrew Pinski <apinski@cavium.com>
48 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
49 (INSN_OCTEONP): New macro.
50 (CPU_OCTEONP): New macro.
51 (OPCODE_IS_MEMBER): Add Octeon+.
52 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
54 2011-11-01 DJ Delorie <dj@redhat.com>
58 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
60 * mips.h: Fix a typo in description.
62 2011-09-21 David S. Miller <davem@davemloft.net>
64 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
65 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
66 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
67 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
69 2011-08-09 Chao-ying Fu <fu@mips.com>
70 Maciej W. Rozycki <macro@codesourcery.com>
72 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
73 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
74 (INSN_ASE_MASK): Add the MCU bit.
75 (INSN_MCU): New macro.
76 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
77 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
79 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
81 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
82 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
83 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
84 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
85 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
86 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
87 (INSN2_READ_GPR_MMN): Likewise.
88 (INSN2_READ_FPR_D): Change the bit used.
89 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
90 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
91 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
92 (INSN2_COND_BRANCH): Likewise.
93 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
94 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
95 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
96 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
97 (INSN2_MOD_GPR_MN): Likewise.
99 2011-08-05 David S. Miller <davem@davemloft.net>
101 * sparc.h: Document new format codes '4', '5', and '('.
102 (OPF_LOW4, RS3): New macros.
104 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
106 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
107 order of flags documented.
109 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
111 * mips.h: Clarify the description of microMIPS instruction
113 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
115 2011-07-24 Chao-ying Fu <fu@mips.com>
116 Maciej W. Rozycki <macro@codesourcery.com>
118 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
119 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
120 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
121 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
122 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
123 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
124 (OP_MASK_RS3, OP_SH_RS3): Likewise.
125 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
126 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
127 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
128 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
129 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
130 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
131 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
132 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
133 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
134 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
135 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
136 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
137 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
138 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
139 (INSN_WRITE_GPR_S): New macro.
140 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
141 (INSN2_READ_FPR_D): Likewise.
142 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
143 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
144 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
145 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
146 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
147 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
148 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
149 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
150 (CPU_MICROMIPS): New macro.
151 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
152 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
153 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
154 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
155 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
156 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
157 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
158 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
159 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
160 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
161 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
162 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
163 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
164 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
165 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
166 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
167 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
168 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
169 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
170 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
171 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
172 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
173 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
174 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
175 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
176 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
177 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
178 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
179 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
180 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
181 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
182 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
183 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
184 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
185 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
186 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
187 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
188 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
189 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
190 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
191 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
192 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
193 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
194 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
195 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
196 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
197 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
198 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
199 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
200 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
201 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
202 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
203 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
204 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
205 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
206 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
207 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
208 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
209 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
210 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
211 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
212 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
213 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
214 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
215 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
216 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
217 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
218 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
219 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
220 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
221 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
222 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
223 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
224 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
225 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
226 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
227 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
228 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
229 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
230 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
231 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
232 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
233 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
234 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
235 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
236 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
237 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
238 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
239 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
240 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
241 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
242 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
243 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
244 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
245 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
246 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
247 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
248 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
249 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
250 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
251 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
252 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
253 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
254 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
255 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
256 (micromips_opcodes): New declaration.
257 (bfd_micromips_num_opcodes): Likewise.
259 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
261 * mips.h (INSN_TRAP): Rename to...
262 (INSN_NO_DELAY_SLOT): ... this.
263 (INSN_SYNC): Remove macro.
265 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
267 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
268 a duplicate of AVR_ISA_SPM.
270 2011-07-01 Nick Clifton <nickc@redhat.com>
272 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
274 2011-06-18 Robin Getz <robin.getz@analog.com>
276 * bfin.h (is_macmod_signed): New func
278 2011-06-18 Mike Frysinger <vapier@gentoo.org>
280 * bfin.h (is_macmod_pmove): Add missing space before func args.
281 (is_macmod_hmove): Likewise.
283 2011-06-13 Walter Lee <walt@tilera.com>
285 * tilegx.h: New file.
286 * tilepro.h: New file.
288 2011-05-31 Paul Brook <paul@codesourcery.com>
290 * arm.h (ARM_ARCH_V7R_IDIV): Define.
292 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
294 * s390.h: Replace S390_OPERAND_REG_EVEN with
295 S390_OPERAND_REG_PAIR.
297 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
299 * s390.h: Add S390_OPCODE_REG_EVEN flag.
301 2011-04-18 Julian Brown <julian@codesourcery.com>
303 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
305 2011-04-11 Dan McDonald <dan@wellkeeper.com>
308 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
310 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
312 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
313 New instruction set flags.
314 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
316 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
318 * mips.h (M_PREF_AB): New enum value.
320 2011-02-12 Mike Frysinger <vapier@gentoo.org>
322 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
324 (is_macmod_pmove, is_macmod_hmove): New functions.
326 2011-02-11 Mike Frysinger <vapier@gentoo.org>
328 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
330 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
332 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
333 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
335 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
338 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
341 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
344 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
346 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
348 * mips.h: Update commentary after last commit.
350 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
352 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
353 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
354 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
356 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
358 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
360 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
362 * mips.h: Fix previous commit.
364 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
366 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
367 (INSN_LOONGSON_3A): Clear bit 31.
369 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
372 * arm.h (ARM_AEXT_V6M_ONLY): New define.
373 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
374 (ARM_ARCH_V6M_ONLY): New define.
376 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
378 * mips.h (INSN_LOONGSON_3A): Defined.
379 (CPU_LOONGSON_3A): Defined.
380 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
382 2010-10-09 Matt Rice <ratmice@gmail.com>
384 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
385 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
387 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
389 * arm.h (ARM_EXT_VIRT): New define.
390 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
391 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
394 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
396 * arm.h (ARM_AEXT_ADIV): New define.
397 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
399 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
401 * arm.h (ARM_EXT_OS): New define.
402 (ARM_AEXT_V6SM): Likewise.
403 (ARM_ARCH_V6SM): Likewise.
405 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
407 * arm.h (ARM_EXT_MP): Add.
408 (ARM_ARCH_V7A_MP): Likewise.
410 2010-09-22 Mike Frysinger <vapier@gentoo.org>
412 * bfin.h: Declare pseudoChr structs/defines.
414 2010-09-21 Mike Frysinger <vapier@gentoo.org>
416 * bfin.h: Strip trailing whitespace.
418 2010-07-29 DJ Delorie <dj@redhat.com>
420 * rx.h (RX_Operand_Type): Add TwoReg.
421 (RX_Opcode_ID): Remove ediv and ediv2.
423 2010-07-27 DJ Delorie <dj@redhat.com>
425 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
427 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
428 Ina Pandit <ina.pandit@kpitcummins.com>
430 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
431 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
432 PROCESSOR_V850E2_ALL.
433 Remove PROCESSOR_V850EA support.
434 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
435 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
436 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
437 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
438 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
439 V850_OPERAND_PERCENT.
440 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
442 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
445 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
447 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
448 (MIPS16_INSN_BRANCH): Rename to...
449 (MIPS16_INSN_COND_BRANCH): ... this.
451 2010-07-03 Alan Modra <amodra@gmail.com>
453 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
454 Renumber other PPC_OPCODE defines.
456 2010-07-03 Alan Modra <amodra@gmail.com>
458 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
460 2010-06-29 Alan Modra <amodra@gmail.com>
462 * maxq.h: Delete file.
464 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
466 * ppc.h (PPC_OPCODE_E500): Define.
468 2010-05-26 Catherine Moore <clm@codesourcery.com>
470 * opcode/mips.h (INSN_MIPS16): Remove.
472 2010-04-21 Joseph Myers <joseph@codesourcery.com>
474 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
476 2010-04-15 Nick Clifton <nickc@redhat.com>
478 * alpha.h: Update copyright notice to use GPLv3.
484 * convex.h: Likewise.
498 * m68hc11.h: Likewise.
504 * mn10200.h: Likewise.
505 * mn10300.h: Likewise.
506 * msp430.h: Likewise.
517 * score-datadep.h: Likewise.
518 * score-inst.h: Likewise.
520 * spu-insns.h: Likewise.
524 * tic54x.h: Likewise.
529 2010-03-25 Joseph Myers <joseph@codesourcery.com>
531 * tic6x-control-registers.h, tic6x-insn-formats.h,
532 tic6x-opcode-table.h, tic6x.h: New.
534 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
536 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
538 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
540 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
542 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
544 * ia64.h (ia64_find_opcode): Remove argument name.
545 (ia64_find_next_opcode): Likewise.
546 (ia64_dis_opcode): Likewise.
547 (ia64_free_opcode): Likewise.
548 (ia64_find_dependency): Likewise.
550 2009-11-22 Doug Evans <dje@sebabeach.org>
552 * cgen.h: Include bfd_stdint.h.
553 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
555 2009-11-18 Paul Brook <paul@codesourcery.com>
557 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
559 2009-11-17 Paul Brook <paul@codesourcery.com>
560 Daniel Jacobowitz <dan@codesourcery.com>
562 * arm.h (ARM_EXT_V6_DSP): Define.
563 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
564 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
566 2009-11-04 DJ Delorie <dj@redhat.com>
568 * rx.h (rx_decode_opcode) (mvtipl): Add.
569 (mvtcp, mvfcp, opecp): Remove.
571 2009-11-02 Paul Brook <paul@codesourcery.com>
573 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
574 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
575 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
576 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
577 FPU_ARCH_NEON_VFP_V4): Define.
579 2009-10-23 Doug Evans <dje@sebabeach.org>
581 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
582 * cgen.h: Update. Improve multi-inclusion macro name.
584 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
586 * ppc.h (PPC_OPCODE_476): Define.
588 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
590 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
592 2009-09-29 DJ Delorie <dj@redhat.com>
596 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
598 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
600 2009-09-21 Ben Elliston <bje@au.ibm.com>
602 * ppc.h (PPC_OPCODE_PPCA2): New.
604 2009-09-05 Martin Thuresson <martin@mtme.org>
606 * ia64.h (struct ia64_operand): Renamed member class to op_class.
608 2009-08-29 Martin Thuresson <martin@mtme.org>
610 * tic30.h (template): Rename type template to
611 insn_template. Updated code to use new name.
612 * tic54x.h (template): Rename type template to
615 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
617 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
619 2009-06-11 Anthony Green <green@moxielogic.com>
621 * moxie.h (MOXIE_F3_PCREL): Define.
622 (moxie_form3_opc_info): Grow.
624 2009-06-06 Anthony Green <green@moxielogic.com>
626 * moxie.h (MOXIE_F1_M): Define.
628 2009-04-15 Anthony Green <green@moxielogic.com>
632 2009-04-06 DJ Delorie <dj@redhat.com>
634 * h8300.h: Add relaxation attributes to MOVA opcodes.
636 2009-03-10 Alan Modra <amodra@bigpond.net.au>
638 * ppc.h (ppc_parse_cpu): Declare.
640 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
642 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
643 and _IMM11 for mbitclr and mbitset.
644 * score-datadep.h: Update dependency information.
646 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
648 * ppc.h (PPC_OPCODE_POWER7): New.
650 2009-02-06 Doug Evans <dje@google.com>
652 * i386.h: Add comment regarding sse* insns and prefixes.
654 2009-02-03 Sandip Matte <sandip@rmicorp.com>
656 * mips.h (INSN_XLR): Define.
657 (INSN_CHIP_MASK): Update.
659 (OPCODE_IS_MEMBER): Update.
660 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
662 2009-01-28 Doug Evans <dje@google.com>
664 * opcode/i386.h: Add multiple inclusion protection.
665 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
666 (EDI_REG_NUM): New macros.
667 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
668 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
669 (REX_PREFIX_P): New macro.
671 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
673 * ppc.h (struct powerpc_opcode): New field "deprecated".
674 (PPC_OPCODE_NOPOWER4): Delete.
676 2008-11-28 Joshua Kinard <kumba@gentoo.org>
678 * mips.h: Define CPU_R14000, CPU_R16000.
679 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
681 2008-11-18 Catherine Moore <clm@codesourcery.com>
683 * arm.h (FPU_NEON_FP16): New.
684 (FPU_ARCH_NEON_FP16): New.
686 2008-11-06 Chao-ying Fu <fu@mips.com>
688 * mips.h: Doucument '1' for 5-bit sync type.
690 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
692 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
695 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
697 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
699 2008-07-30 Michael J. Eager <eager@eagercon.com>
701 * ppc.h (PPC_OPCODE_405): Define.
702 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
704 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
706 * ppc.h (ppc_cpu_t): New typedef.
707 (struct powerpc_opcode <flags>): Use it.
708 (struct powerpc_operand <insert, extract>): Likewise.
709 (struct powerpc_macro <flags>): Likewise.
711 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
713 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
714 Update comment before MIPS16 field descriptors to mention MIPS16.
715 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
717 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
718 New bit masks and shift counts for cins and exts.
720 * mips.h: Document new field descriptors +Q.
721 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
723 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
725 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
726 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
728 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
730 * ppc.h: (PPC_OPCODE_E500MC): New.
732 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
734 * i386.h (MAX_OPERANDS): Set to 5.
735 (MAX_MNEM_SIZE): Changed to 20.
737 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
739 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
741 2008-03-09 Paul Brook <paul@codesourcery.com>
743 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
745 2008-03-04 Paul Brook <paul@codesourcery.com>
747 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
748 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
749 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
751 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
752 Nick Clifton <nickc@redhat.com>
755 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
756 with a 32-bit displacement but without the top bit of the 4th byte
759 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
761 * cr16.h (cr16_num_optab): Declared.
763 2008-02-14 Hakan Ardo <hakan@debian.org>
766 * avr.h (AVR_ISA_2xxe): Define.
768 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
770 * mips.h: Update copyright.
771 (INSN_CHIP_MASK): New macro.
772 (INSN_OCTEON): New macro.
773 (CPU_OCTEON): New macro.
774 (OPCODE_IS_MEMBER): Handle Octeon instructions.
776 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
778 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
780 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
782 * avr.h (AVR_ISA_USB162): Add new opcode set.
783 (AVR_ISA_AVR3): Likewise.
785 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
787 * mips.h (INSN_LOONGSON_2E): New.
788 (INSN_LOONGSON_2F): New.
789 (CPU_LOONGSON_2E): New.
790 (CPU_LOONGSON_2F): New.
791 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
793 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
795 * mips.h (INSN_ISA*): Redefine certain values as an
796 enumeration. Update comments.
797 (mips_isa_table): New.
798 (ISA_MIPS*): Redefine to match enumeration.
799 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
802 2007-08-08 Ben Elliston <bje@au.ibm.com>
804 * ppc.h (PPC_OPCODE_PPCPS): New.
806 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
808 * m68k.h: Document j K & E.
810 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
812 * cr16.h: New file for CR16 target.
814 2007-05-02 Alan Modra <amodra@bigpond.net.au>
816 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
818 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
820 * m68k.h (mcfisa_c): New.
821 (mcfusp, mcf_mask): Adjust.
823 2007-04-20 Alan Modra <amodra@bigpond.net.au>
825 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
826 (num_powerpc_operands): Declare.
827 (PPC_OPERAND_SIGNED et al): Redefine as hex.
828 (PPC_OPERAND_PLUS1): Define.
830 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
832 * i386.h (REX_MODE64): Renamed to ...
834 (REX_EXTX): Renamed to ...
836 (REX_EXTY): Renamed to ...
838 (REX_EXTZ): Renamed to ...
841 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
843 * i386.h: Add entries from config/tc-i386.h and move tables
844 to opcodes/i386-opc.h.
846 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
848 * i386.h (FloatDR): Removed.
849 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
851 2007-03-01 Alan Modra <amodra@bigpond.net.au>
853 * spu-insns.h: Add soma double-float insns.
855 2007-02-20 Thiemo Seufer <ths@mips.com>
856 Chao-Ying Fu <fu@mips.com>
858 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
859 (INSN_DSPR2): Add flag for DSP R2 instructions.
860 (M_BALIGN): New macro.
862 2007-02-14 Alan Modra <amodra@bigpond.net.au>
864 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
865 and Seg3ShortFrom with Shortform.
867 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
870 * i386.h (i386_optab): Put the real "test" before the pseudo
873 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
875 * m68k.h (m68010up): OR fido_a.
877 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
879 * m68k.h (fido_a): New.
881 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
883 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
884 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
887 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
889 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
891 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
893 * score-inst.h (enum score_insn_type): Add Insn_internal.
895 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
896 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
897 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
898 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
899 Alan Modra <amodra@bigpond.net.au>
901 * spu-insns.h: New file.
904 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
906 * ppc.h (PPC_OPCODE_CELL): Define.
908 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
910 * i386.h : Modify opcode to support for the change in POPCNT opcode
911 in amdfam10 architecture.
913 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
915 * i386.h: Replace CpuMNI with CpuSSSE3.
917 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
918 Joseph Myers <joseph@codesourcery.com>
919 Ian Lance Taylor <ian@wasabisystems.com>
920 Ben Elliston <bje@wasabisystems.com>
922 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
924 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
926 * score-datadep.h: New file.
927 * score-inst.h: New file.
929 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
931 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
932 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
935 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
936 Michael Meissner <michael.meissner@amd.com>
938 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
940 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
942 * i386.h (i386_optab): Add "nop" with memory reference.
944 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
946 * i386.h (i386_optab): Update comment for 64bit NOP.
948 2006-06-06 Ben Elliston <bje@au.ibm.com>
949 Anton Blanchard <anton@samba.org>
951 * ppc.h (PPC_OPCODE_POWER6): Define.
954 2006-06-05 Thiemo Seufer <ths@mips.com>
956 * mips.h: Improve description of MT flags.
958 2006-05-25 Richard Sandiford <richard@codesourcery.com>
960 * m68k.h (mcf_mask): Define.
962 2006-05-05 Thiemo Seufer <ths@mips.com>
963 David Ung <davidu@mips.com>
965 * mips.h (enum): Add macro M_CACHE_AB.
967 2006-05-04 Thiemo Seufer <ths@mips.com>
968 Nigel Stephens <nigel@mips.com>
969 David Ung <davidu@mips.com>
971 * mips.h: Add INSN_SMARTMIPS define.
973 2006-04-30 Thiemo Seufer <ths@mips.com>
974 David Ung <davidu@mips.com>
976 * mips.h: Defines udi bits and masks. Add description of
977 characters which may appear in the args field of udi
980 2006-04-26 Thiemo Seufer <ths@networkno.de>
982 * mips.h: Improve comments describing the bitfield instruction
985 2006-04-26 Julian Brown <julian@codesourcery.com>
987 * arm.h (FPU_VFP_EXT_V3): Define constant.
988 (FPU_NEON_EXT_V1): Likewise.
989 (FPU_VFP_HARD): Update.
990 (FPU_VFP_V3): Define macro.
991 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
993 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
995 * avr.h (AVR_ISA_PWMx): New.
997 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
999 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1000 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1001 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1002 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1003 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1005 2006-03-10 Paul Brook <paul@codesourcery.com>
1007 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1009 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1011 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1012 first. Correct mask of bb "B" opcode.
1014 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1016 * i386.h (i386_optab): Support Intel Merom New Instructions.
1018 2006-02-24 Paul Brook <paul@codesourcery.com>
1020 * arm.h: Add V7 feature bits.
1022 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1024 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1026 2006-01-31 Paul Brook <paul@codesourcery.com>
1027 Richard Earnshaw <rearnsha@arm.com>
1029 * arm.h: Use ARM_CPU_FEATURE.
1030 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1031 (arm_feature_set): Change to a structure.
1032 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1033 ARM_FEATURE): New macros.
1035 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1037 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1038 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1039 (ADD_PC_INCR_OPCODE): Don't define.
1041 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1044 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1046 2005-11-14 David Ung <davidu@mips.com>
1048 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1049 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1050 save/restore encoding of the args field.
1052 2005-10-28 Dave Brolley <brolley@redhat.com>
1054 Contribute the following changes:
1055 2005-02-16 Dave Brolley <brolley@redhat.com>
1057 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1058 cgen_isa_mask_* to cgen_bitset_*.
1061 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1063 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1064 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1065 (CGEN_CPU_TABLE): Make isas a ponter.
1067 2003-09-29 Dave Brolley <brolley@redhat.com>
1069 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1070 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1071 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1073 2002-12-13 Dave Brolley <brolley@redhat.com>
1075 * cgen.h (symcat.h): #include it.
1076 (cgen-bitset.h): #include it.
1077 (CGEN_ATTR_VALUE_TYPE): Now a union.
1078 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1079 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1080 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1081 * cgen-bitset.h: New file.
1083 2005-09-30 Catherine Moore <clm@cm00re.com>
1087 2005-10-24 Jan Beulich <jbeulich@novell.com>
1089 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1092 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1094 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1095 Add FLAG_STRICT to pa10 ftest opcode.
1097 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1099 * hppa.h (pa_opcodes): Remove lha entries.
1101 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1103 * hppa.h (FLAG_STRICT): Revise comment.
1104 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1105 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1108 2005-09-30 Catherine Moore <clm@cm00re.com>
1112 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1114 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1116 2005-09-06 Chao-ying Fu <fu@mips.com>
1118 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1119 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1121 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1122 (INSN_ASE_MASK): Update to include INSN_MT.
1123 (INSN_MT): New define for MT ASE.
1125 2005-08-25 Chao-ying Fu <fu@mips.com>
1127 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1128 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1129 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1130 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1131 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1132 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1134 (INSN_DSP): New define for DSP ASE.
1136 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1140 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1142 * ppc.h (PPC_OPCODE_E300): Define.
1144 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1146 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1148 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1151 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1154 2005-07-27 Jan Beulich <jbeulich@novell.com>
1156 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1157 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1158 Add movq-s as 64-bit variants of movd-s.
1160 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1162 * hppa.h: Fix punctuation in comment.
1164 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1165 implicit space-register addressing. Set space-register bits on opcodes
1166 using implicit space-register addressing. Add various missing pa20
1167 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1168 space-register addressing. Use "fE" instead of "fe" in various
1171 2005-07-18 Jan Beulich <jbeulich@novell.com>
1173 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1175 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1177 * i386.h (i386_optab): Support Intel VMX Instructions.
1179 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1181 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1183 2005-07-05 Jan Beulich <jbeulich@novell.com>
1185 * i386.h (i386_optab): Add new insns.
1187 2005-07-01 Nick Clifton <nickc@redhat.com>
1189 * sparc.h: Add typedefs to structure declarations.
1191 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1194 * i386.h (i386_optab): Update comments for 64bit addressing on
1195 mov. Allow 64bit addressing for mov and movq.
1197 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1199 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1200 respectively, in various floating-point load and store patterns.
1202 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1204 * hppa.h (FLAG_STRICT): Correct comment.
1205 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1206 PA 2.0 mneumonics when equivalent. Entries with cache control
1207 completers now require PA 1.1. Adjust whitespace.
1209 2005-05-19 Anton Blanchard <anton@samba.org>
1211 * ppc.h (PPC_OPCODE_POWER5): Define.
1213 2005-05-10 Nick Clifton <nickc@redhat.com>
1215 * Update the address and phone number of the FSF organization in
1216 the GPL notices in the following files:
1217 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1218 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1219 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1220 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1221 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1222 tic54x.h, tic80.h, v850.h, vax.h
1224 2005-05-09 Jan Beulich <jbeulich@novell.com>
1226 * i386.h (i386_optab): Add ht and hnt.
1228 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1230 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1231 Add xcrypt-ctr. Provide aliases without hyphens.
1233 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1235 Moved from ../ChangeLog
1237 2005-04-12 Paul Brook <paul@codesourcery.com>
1238 * m88k.h: Rename psr macros to avoid conflicts.
1240 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1241 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1242 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1243 and ARM_ARCH_V6ZKT2.
1245 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1246 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1247 Remove redundant instruction types.
1248 (struct argument): X_op - new field.
1249 (struct cst4_entry): Remove.
1250 (no_op_insn): Declare.
1252 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1253 * crx.h (enum argtype): Rename types, remove unused types.
1255 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1256 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1257 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1258 (enum operand_type): Rearrange operands, edit comments.
1259 replace us<N> with ui<N> for unsigned immediate.
1260 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1261 displacements (respectively).
1262 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1263 (instruction type): Add NO_TYPE_INS.
1264 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1265 (operand_entry): New field - 'flags'.
1266 (operand flags): New.
1268 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1269 * crx.h (operand_type): Remove redundant types i3, i4,
1271 Add new unsigned immediate types us3, us4, us5, us16.
1273 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1275 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1276 adjust them accordingly.
1278 2005-04-01 Jan Beulich <jbeulich@novell.com>
1280 * i386.h (i386_optab): Add rdtscp.
1282 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1284 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1285 between memory and segment register. Allow movq for moving between
1286 general-purpose register and segment register.
1288 2005-02-09 Jan Beulich <jbeulich@novell.com>
1291 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1292 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1295 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1297 * m68k.h (m68008, m68ec030, m68882): Remove.
1299 (cpu_m68k, cpu_cf): New.
1300 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1301 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1303 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1305 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1306 * cgen.h (enum cgen_parse_operand_type): Add
1307 CGEN_PARSE_OPERAND_SYMBOLIC.
1309 2005-01-21 Fred Fish <fnf@specifixinc.com>
1311 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1312 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1313 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1315 2005-01-19 Fred Fish <fnf@specifixinc.com>
1317 * mips.h (struct mips_opcode): Add new pinfo2 member.
1318 (INSN_ALIAS): New define for opcode table entries that are
1319 specific instances of another entry, such as 'move' for an 'or'
1320 with a zero operand.
1321 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1322 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1324 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1326 * mips.h (CPU_RM9000): Define.
1327 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1329 2004-11-25 Jan Beulich <jbeulich@novell.com>
1331 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1332 to/from test registers are illegal in 64-bit mode. Add missing
1333 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1334 (previously one had to explicitly encode a rex64 prefix). Re-enable
1335 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1336 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1338 2004-11-23 Jan Beulich <jbeulich@novell.com>
1340 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1341 available only with SSE2. Change the MMX additions introduced by SSE
1342 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1343 instructions by their now designated identifier (since combining i686
1344 and 3DNow! does not really imply 3DNow!A).
1346 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1348 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1349 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1351 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1352 Vineet Sharma <vineets@noida.hcltech.com>
1354 * maxq.h: New file: Disassembly information for the maxq port.
1356 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1358 * i386.h (i386_optab): Put back "movzb".
1360 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1362 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1363 comments. Remove member cris_ver_sim. Add members
1364 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1365 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1366 (struct cris_support_reg, struct cris_cond15): New types.
1367 (cris_conds15): Declare.
1368 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1369 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1370 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1371 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1372 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1373 SIZE_FIELD_UNSIGNED.
1375 2004-11-04 Jan Beulich <jbeulich@novell.com>
1377 * i386.h (sldx_Suf): Remove.
1378 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1379 (q_FP): Define, implying no REX64.
1380 (x_FP, sl_FP): Imply FloatMF.
1381 (i386_optab): Split reg and mem forms of moving from segment registers
1382 so that the memory forms can ignore the 16-/32-bit operand size
1383 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1384 all non-floating-point instructions. Unite 32- and 64-bit forms of
1385 movsx, movzx, and movd. Adjust floating point operations for the above
1386 changes to the *FP macros. Add DefaultSize to floating point control
1387 insns operating on larger memory ranges. Remove left over comments
1388 hinting at certain insns being Intel-syntax ones where the ones
1389 actually meant are already gone.
1391 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1393 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1396 2004-09-30 Paul Brook <paul@codesourcery.com>
1398 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1399 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1401 2004-09-11 Theodore A. Roth <troth@openavr.org>
1403 * avr.h: Add support for
1404 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1406 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1408 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1410 2004-08-24 Dmitry Diky <diwil@spec.ru>
1412 * msp430.h (msp430_opc): Add new instructions.
1413 (msp430_rcodes): Declare new instructions.
1414 (msp430_hcodes): Likewise..
1416 2004-08-13 Nick Clifton <nickc@redhat.com>
1419 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1422 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1424 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1426 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1428 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1430 2004-07-21 Jan Beulich <jbeulich@novell.com>
1432 * i386.h: Adjust instruction descriptions to better match the
1435 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1437 * arm.h: Remove all old content. Replace with architecture defines
1438 from gas/config/tc-arm.c.
1440 2004-07-09 Andreas Schwab <schwab@suse.de>
1442 * m68k.h: Fix comment.
1444 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1448 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1450 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1452 2004-05-24 Peter Barada <peter@the-baradas.com>
1454 * m68k.h: Add 'size' to m68k_opcode.
1456 2004-05-05 Peter Barada <peter@the-baradas.com>
1458 * m68k.h: Switch from ColdFire chip name to core variant.
1460 2004-04-22 Peter Barada <peter@the-baradas.com>
1462 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1463 descriptions for new EMAC cases.
1464 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1465 handle Motorola MAC syntax.
1466 Allow disassembly of ColdFire V4e object files.
1468 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1470 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1472 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1474 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1476 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1478 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1480 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1482 * i386.h (i386_optab): Added xstore/xcrypt insns.
1484 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1486 * h8300.h (32bit ldc/stc): Add relaxing support.
1488 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1490 * h8300.h (BITOP): Pass MEMRELAX flag.
1492 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1494 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1497 For older changes see ChangeLog-9103
1503 version-control: never