include/opcode/ChangeLog

   1 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         Moved from ../ChangeLog
   4
   5         2005-04-12  Paul Brook  <paul@codesourcery.com>
   6         * m88k.h: Rename psr macros to avoid conflicts.
   7
   8         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
   9         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  10         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  11         and ARM_ARCH_V6ZKT2.
  12
  13         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  14         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  15         Remove redundant instruction types.
  16         (struct argument): X_op - new field.
  17         (struct cst4_entry): Remove.
  18         (no_op_insn): Declare.
  19
  20         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  21         * crx.h (enum argtype): Rename types, remove unused types.
  22
  23         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  24         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  25         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  26         (enum operand_type): Rearrange operands, edit comments.
  27         replace us<N> with ui<N> for unsigned immediate.
  28         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  29         displacements (respectively).
  30         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  31         (instruction type): Add NO_TYPE_INS.
  32         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  33         (operand_entry): New field - 'flags'.
  34         (operand flags): New.
  35
  36         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  37         * crx.h (operand_type): Remove redundant types i3, i4,
  38         i5, i8, i12.
  39         Add new unsigned immediate types us3, us4, us5, us16.
  40
  41 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  42
  43         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  44         adjust them accordingly.
  45
  46 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  47
  48         * i386.h (i386_optab): Add rdtscp.
  49
  50 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  53         between memory and segment register. Allow movq for moving between
  54         general-purpose register and segment register.
  55
  56 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  57
  58         PR gas/707
  59         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  60         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  61         fnstsw.
  62
  63 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  64
  65         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  66         * cgen.h (enum cgen_parse_operand_type): Add
  67         CGEN_PARSE_OPERAND_SYMBOLIC.
  68
  69 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  70
  71         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  72         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  73         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  74
  75 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  76
  77         * mips.h (struct mips_opcode): Add new pinfo2 member.
  78         (INSN_ALIAS): New define for opcode table entries that are
  79         specific instances of another entry, such as 'move' for an 'or'
  80         with a zero operand.
  81         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  82         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  83
  84 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  85
  86         * mips.h (CPU_RM9000): Define.
  87         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  88
  89 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  90
  91         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  92         to/from test registers are illegal in 64-bit mode. Add missing
  93         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  94         (previously one had to explicitly encode a rex64 prefix). Re-enable
  95         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  96         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  97
  98 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  99
 100         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 101         available only with SSE2. Change the MMX additions introduced by SSE
 102         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 103         instructions by their now designated identifier (since combining i686
 104         and 3DNow! does not really imply 3DNow!A).
 105
 106 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 107
 108         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 109         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 110
 111 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 112             Vineet Sharma      <vineets@noida.hcltech.com>
 113
 114         * maxq.h: New file: Disassembly information for the maxq port.
 115
 116 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         * i386.h (i386_optab): Put back "movzb".
 119
 120 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 121
 122         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 123         comments.  Remove member cris_ver_sim.  Add members
 124         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 125         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 126         (struct cris_support_reg, struct cris_cond15): New types.
 127         (cris_conds15): Declare.
 128         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 129         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 130         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 131         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 132         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 133         SIZE_FIELD_UNSIGNED.
 134
 135 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 136
 137         * i386.h (sldx_Suf): Remove.
 138         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 139         (q_FP): Define, implying no REX64.
 140         (x_FP, sl_FP): Imply FloatMF.
 141         (i386_optab): Split reg and mem forms of moving from segment registers
 142         so that the memory forms can ignore the 16-/32-bit operand size
 143         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 144         all non-floating-point instructions. Unite 32- and 64-bit forms of
 145         movsx, movzx, and movd. Adjust floating point operations for the above
 146         changes to the *FP macros. Add DefaultSize to floating point control
 147         insns operating on larger memory ranges. Remove left over comments
 148         hinting at certain insns being Intel-syntax ones where the ones
 149         actually meant are already gone.
 150
 151 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 152
 153         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 154         instruction type.
 155
 156 2004-09-30  Paul Brook  <paul@codesourcery.com>
 157
 158         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 159         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 160
 161 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 162
 163         * avr.h: Add support for
 164         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 165
 166 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 167
 168         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 169
 170 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 171
 172         * msp430.h (msp430_opc): Add new instructions.
 173         (msp430_rcodes): Declare new instructions.
 174         (msp430_hcodes): Likewise..
 175
 176 2004-08-13  Nick Clifton  <nickc@redhat.com>
 177
 178         PR/301
 179         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 180         processors.
 181
 182 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 183
 184         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 185
 186 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 189
 190 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 191
 192         * i386.h: Adjust instruction descriptions to better match the
 193         specification.
 194
 195 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 196
 197         * arm.h: Remove all old content.  Replace with architecture defines
 198         from gas/config/tc-arm.c.
 199
 200 2004-07-09  Andreas Schwab  <schwab@suse.de>
 201
 202         * m68k.h: Fix comment.
 203
 204 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 205
 206         * crx.h: New file.
 207
 208 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 209
 210         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 211
 212 2004-05-24  Peter Barada  <peter@the-baradas.com>
 213
 214         * m68k.h: Add 'size' to m68k_opcode.
 215
 216 2004-05-05  Peter Barada  <peter@the-baradas.com>
 217
 218         * m68k.h: Switch from ColdFire chip name to core variant.
 219
 220 2004-04-22  Peter Barada  <peter@the-baradas.com>
 221
 222         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 223         descriptions for new EMAC cases.
 224         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 225         handle Motorola MAC syntax.
 226         Allow disassembly of ColdFire V4e object files.
 227
 228 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 229
 230         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 231
 232 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 233
 234         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 235
 236 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 237
 238         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 239
 240 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 241
 242         * i386.h (i386_optab): Added xstore/xcrypt insns.
 243
 244 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 245
 246         * h8300.h (32bit ldc/stc): Add relaxing support.
 247
 248 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 249
 250         * h8300.h (BITOP): Pass MEMRELAX flag.
 251
 252 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 253
 254         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 255         except for the H8S.
 256
 257 For older changes see ChangeLog-9103
 258 \f
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